[llvm] [NewPM][CodeGen] Port selection dag isel to new pass manager (PR #83567)
via llvm-commits
llvm-commits at lists.llvm.org
Sun May 19 20:40:45 PDT 2024
https://github.com/paperchalice updated https://github.com/llvm/llvm-project/pull/83567
>From 82f6867807f9b0543c27ed259c2ac1957496fce7 Mon Sep 17 00:00:00 2001
From: PaperChalice <liujunchang97 at outlook.com>
Date: Wed, 10 Apr 2024 21:22:59 +0800
Subject: [PATCH 01/26] [NewPM][CodeGen] Port `SelectionDAGISel` to new pass
manager
---
llvm/include/llvm/CodeGen/SelectionDAG.h | 12 +
llvm/include/llvm/CodeGen/SelectionDAGISel.h | 43 +++-
llvm/include/llvm/CodeGen/StackProtector.h | 2 +
.../CodeGen/SelectionDAG/SelectionDAGISel.cpp | 230 +++++++++++++-----
4 files changed, 227 insertions(+), 60 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/SelectionDAG.h b/llvm/include/llvm/CodeGen/SelectionDAG.h
index 979ef8033eb5e..538f1e99ce33e 100644
--- a/llvm/include/llvm/CodeGen/SelectionDAG.h
+++ b/llvm/include/llvm/CodeGen/SelectionDAG.h
@@ -29,6 +29,7 @@
#include "llvm/CodeGen/ISDOpcodes.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineMemOperand.h"
+#include "llvm/CodeGen/MachinePassManager.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/CodeGenTypes/MachineValueType.h"
@@ -229,6 +230,7 @@ class SelectionDAG {
const TargetLibraryInfo *LibInfo = nullptr;
const FunctionVarLocs *FnVarLocs = nullptr;
MachineFunction *MF;
+ MachineFunctionAnalysisManager *MFAM = nullptr;
Pass *SDAGISelPass = nullptr;
LLVMContext *Context;
CodeGenOptLevel OptLevel;
@@ -458,6 +460,15 @@ class SelectionDAG {
UniformityInfo *UA, ProfileSummaryInfo *PSIin,
BlockFrequencyInfo *BFIin, FunctionVarLocs const *FnVarLocs);
+ void init(MachineFunction &NewMF, OptimizationRemarkEmitter &NewORE,
+ MachineFunctionAnalysisManager &AM,
+ const TargetLibraryInfo *LibraryInfo, UniformityInfo *UA,
+ ProfileSummaryInfo *PSIin, BlockFrequencyInfo *BFIin,
+ FunctionVarLocs const *FnVarLocs) {
+ init(NewMF, NewORE, nullptr, LibraryInfo, UA, PSIin, BFIin, FnVarLocs);
+ MFAM = &AM;
+ }
+
void setFunctionLoweringInfo(FunctionLoweringInfo * FuncInfo) {
FLI = FuncInfo;
}
@@ -468,6 +479,7 @@ class SelectionDAG {
MachineFunction &getMachineFunction() const { return *MF; }
const Pass *getPass() const { return SDAGISelPass; }
+ MachineFunctionAnalysisManager *getMFAM() { return MFAM; }
const DataLayout &getDataLayout() const { return MF->getDataLayout(); }
const TargetMachine &getTarget() const { return TM; }
diff --git a/llvm/include/llvm/CodeGen/SelectionDAGISel.h b/llvm/include/llvm/CodeGen/SelectionDAGISel.h
index 837f8bf7263ea..fe655543a4705 100644
--- a/llvm/include/llvm/CodeGen/SelectionDAGISel.h
+++ b/llvm/include/llvm/CodeGen/SelectionDAGISel.h
@@ -15,6 +15,7 @@
#define LLVM_CODEGEN_SELECTIONDAGISEL_H
#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachinePassManager.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/IR/BasicBlock.h"
#include <memory>
@@ -24,6 +25,7 @@ class AAResults;
class AssumptionCache;
class TargetInstrInfo;
class TargetMachine;
+class SSPLayoutInfo;
class SelectionDAGBuilder;
class SDValue;
class MachineRegisterInfo;
@@ -31,6 +33,7 @@ class MachineFunction;
class OptimizationRemarkEmitter;
class TargetLowering;
class TargetLibraryInfo;
+class TargetTransformInfo;
class FunctionLoweringInfo;
class SwiftErrorValueTracking;
class GCFunctionInfo;
@@ -38,7 +41,7 @@ class ScheduleDAGSDNodes;
/// SelectionDAGISel - This is the common base class used for SelectionDAG-based
/// pattern-matching instruction selectors.
-class SelectionDAGISel : public MachineFunctionPass {
+class SelectionDAGISel {
public:
TargetMachine &TM;
const TargetLibraryInfo *LibInfo;
@@ -51,6 +54,10 @@ class SelectionDAGISel : public MachineFunctionPass {
AAResults *AA = nullptr;
AssumptionCache *AC = nullptr;
GCFunctionInfo *GFI = nullptr;
+ SSPLayoutInfo *SP = nullptr;
+#ifndef NDEBUG
+ TargetTransformInfo *TTI = nullptr;
+#endif
CodeGenOptLevel OptLevel;
const TargetInstrInfo *TII;
const TargetLowering *TLI;
@@ -67,16 +74,18 @@ class SelectionDAGISel : public MachineFunctionPass {
/// functions. Storing the filter result here so that we only need to do the
/// filtering once.
bool MatchFilterFuncName = false;
+ StringRef FuncName;
- explicit SelectionDAGISel(char &ID, TargetMachine &tm,
+ explicit SelectionDAGISel(TargetMachine &tm,
CodeGenOptLevel OL = CodeGenOptLevel::Default);
- ~SelectionDAGISel() override;
+ ~SelectionDAGISel();
const TargetLowering *getTargetLowering() const { return TLI; }
- void getAnalysisUsage(AnalysisUsage &AU) const override;
+ void initializeAnalysisResults(MachineFunctionAnalysisManager &MFAM);
+ void initializeAnalysisResults(MachineFunctionPass &MFP);
- bool runOnMachineFunction(MachineFunction &MF) override;
+ virtual bool runOnMachineFunction(MachineFunction &mf);
virtual void emitFunctionEntryCode() {}
@@ -517,6 +526,30 @@ class SelectionDAGISel : public MachineFunctionPass {
bool isMorphNodeTo);
};
+class SelectionDAGISelLegacy : public MachineFunctionPass {
+ std::unique_ptr<SelectionDAGISel> Selector;
+
+public:
+ SelectionDAGISelLegacy(char &ID, std::unique_ptr<SelectionDAGISel> S);
+
+ ~SelectionDAGISelLegacy() override = default;
+
+ void getAnalysisUsage(AnalysisUsage &AU) const override;
+
+ bool runOnMachineFunction(MachineFunction &MF) override;
+};
+
+class SelectionDAGISelPass : public PassInfoMixin<SelectionDAGISelPass> {
+ std::unique_ptr<SelectionDAGISel> Selector;
+
+protected:
+ SelectionDAGISelPass(std::unique_ptr<SelectionDAGISel> Selector)
+ : Selector(std::move(Selector)) {}
+
+public:
+ PreservedAnalyses run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM);
+};
}
#endif /* LLVM_CODEGEN_SELECTIONDAGISEL_H */
diff --git a/llvm/include/llvm/CodeGen/StackProtector.h b/llvm/include/llvm/CodeGen/StackProtector.h
index eb5d9d0caebc6..dfafc781067d7 100644
--- a/llvm/include/llvm/CodeGen/StackProtector.h
+++ b/llvm/include/llvm/CodeGen/StackProtector.h
@@ -109,6 +109,8 @@ class StackProtector : public FunctionPass {
StackProtector();
+ SSPLayoutInfo &getLayoutInfo() { return LayoutInfo; }
+
void getAnalysisUsage(AnalysisUsage &AU) const override;
// Return true if StackProtector is supposed to be handled by SelectionDAG.
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index b5694c955b8c8..98b1238974a6e 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -341,9 +341,49 @@ void TargetLowering::AdjustInstrPostInstrSelection(MachineInstr &MI,
// SelectionDAGISel code
//===----------------------------------------------------------------------===//
-SelectionDAGISel::SelectionDAGISel(char &ID, TargetMachine &tm,
- CodeGenOptLevel OL)
- : MachineFunctionPass(ID), TM(tm), FuncInfo(new FunctionLoweringInfo()),
+SelectionDAGISelLegacy::SelectionDAGISelLegacy(
+ char &ID, std::unique_ptr<SelectionDAGISel> S)
+ : MachineFunctionPass(ID), Selector(std::move(S)) {
+ initializeGCModuleInfoPass(*PassRegistry::getPassRegistry());
+ initializeBranchProbabilityInfoWrapperPassPass(
+ *PassRegistry::getPassRegistry());
+ initializeAAResultsWrapperPassPass(*PassRegistry::getPassRegistry());
+ initializeTargetLibraryInfoWrapperPassPass(*PassRegistry::getPassRegistry());
+}
+
+bool SelectionDAGISelLegacy::runOnMachineFunction(MachineFunction &MF) {
+ // If we already selected that function, we do not need to run SDISel.
+ if (MF.getProperties().hasProperty(
+ MachineFunctionProperties::Property::Selected))
+ return false;
+
+ // Do some sanity-checking on the command-line options.
+ if (EnableFastISelAbort && !Selector->TM.Options.EnableFastISel)
+ report_fatal_error("-fast-isel-abort > 0 requires -fast-isel");
+
+ // Decide what flavour of variable location debug-info will be used, before
+ // we change the optimisation level.
+ MF.setUseDebugInstrRef(MF.shouldUseDebugInstrRef());
+
+ // Reset the target options before resetting the optimization
+ // level below.
+ // FIXME: This is a horrible hack and should be processed via
+ // codegen looking at the optimization level explicitly when
+ // it wants to look at it.
+ Selector->TM.resetTargetOptions(MF.getFunction());
+ // Reset OptLevel to None for optnone functions.
+ CodeGenOptLevel NewOptLevel = skipFunction(MF.getFunction())
+ ? CodeGenOptLevel::None
+ : Selector->OptLevel;
+
+ Selector->MF = &MF;
+ OptLevelChanger OLC(*Selector, NewOptLevel);
+ Selector->initializeAnalysisResults(*this);
+ return Selector->runOnMachineFunction(MF);
+}
+
+SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, CodeGenOptLevel OL)
+ : TM(tm), FuncInfo(new FunctionLoweringInfo()),
SwiftError(new SwiftErrorValueTracking()),
CurDAG(new SelectionDAG(tm, OL)),
SDB(std::make_unique<SelectionDAGBuilder>(*CurDAG, *FuncInfo, *SwiftError,
@@ -361,14 +401,17 @@ SelectionDAGISel::~SelectionDAGISel() {
delete SwiftError;
}
-void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
+void SelectionDAGISelLegacy::getAnalysisUsage(AnalysisUsage &AU) const {
+ CodeGenOptLevel OptLevel = Selector->OptLevel;
if (OptLevel != CodeGenOptLevel::None)
AU.addRequired<AAResultsWrapperPass>();
AU.addRequired<GCModuleInfo>();
AU.addRequired<StackProtector>();
AU.addPreserved<GCModuleInfo>();
AU.addRequired<TargetLibraryInfoWrapperPass>();
+#ifndef NDEBUG
AU.addRequired<TargetTransformInfoWrapperPass>();
+#endif
AU.addRequired<AssumptionCacheTracker>();
if (UseMBPI && OptLevel != CodeGenOptLevel::None)
AU.addRequired<BranchProbabilityInfoWrapperPass>();
@@ -406,65 +449,129 @@ static void computeUsesMSVCFloatingPoint(const Triple &TT, const Function &F,
}
}
-bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
+PreservedAnalyses
+SelectionDAGISelPass::run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM) {
// If we already selected that function, we do not need to run SDISel.
- if (mf.getProperties().hasProperty(
+ if (MF.getProperties().hasProperty(
MachineFunctionProperties::Property::Selected))
- return false;
- // Do some sanity-checking on the command-line options.
- assert((!EnableFastISelAbort || TM.Options.EnableFastISel) &&
- "-fast-isel-abort > 0 requires -fast-isel");
-
- const Function &Fn = mf.getFunction();
- MF = &mf;
+ return PreservedAnalyses::all();
-#ifndef NDEBUG
- StringRef FuncName = Fn.getName();
- MatchFilterFuncName = isFunctionInPrintList(FuncName);
-#else
- (void)MatchFilterFuncName;
-#endif
+ // Do some sanity-checking on the command-line options.
+ if (EnableFastISelAbort && !Selector->TM.Options.EnableFastISel)
+ report_fatal_error("-fast-isel-abort > 0 requires -fast-isel");
// Decide what flavour of variable location debug-info will be used, before
// we change the optimisation level.
- bool InstrRef = mf.shouldUseDebugInstrRef();
- mf.setUseDebugInstrRef(InstrRef);
+ MF.setUseDebugInstrRef(MF.shouldUseDebugInstrRef());
// Reset the target options before resetting the optimization
// level below.
// FIXME: This is a horrible hack and should be processed via
// codegen looking at the optimization level explicitly when
// it wants to look at it.
- TM.resetTargetOptions(Fn);
+ Selector->TM.resetTargetOptions(MF.getFunction());
+ // Reset OptLevel to None for optnone functions.
+ // TODO: Add a function analysis to handle this.
+ Selector->MF = &MF;
// Reset OptLevel to None for optnone functions.
- CodeGenOptLevel NewOptLevel = OptLevel;
- if (OptLevel != CodeGenOptLevel::None && skipFunction(Fn))
- NewOptLevel = CodeGenOptLevel::None;
- OptLevelChanger OLC(*this, NewOptLevel);
+ CodeGenOptLevel NewOptLevel = MF.getFunction().hasOptNone()
+ ? CodeGenOptLevel::None
+ : Selector->OptLevel;
+
+ OptLevelChanger OLC(*Selector, NewOptLevel);
+ Selector->initializeAnalysisResults(MFAM);
+ Selector->runOnMachineFunction(MF);
+
+ return getMachineFunctionPassPreservedAnalyses();
+}
+
+void SelectionDAGISel::initializeAnalysisResults(
+ MachineFunctionAnalysisManager &MFAM) {
+ auto &FAM = MFAM.getResult<FunctionAnalysisManagerMachineFunctionProxy>(*MF)
+ .getManager();
+ auto &MAMP = MFAM.getResult<ModuleAnalysisManagerMachineFunctionProxy>(*MF);
+ Function &Fn = MF->getFunction();
+#ifndef NDEBUG
+ FuncName = Fn.getName();
+ MatchFilterFuncName = isFunctionInPrintList(FuncName);
+#else
+ (void)MatchFilterFuncName;
+#endif
TII = MF->getSubtarget().getInstrInfo();
TLI = MF->getSubtarget().getTargetLowering();
RegInfo = &MF->getRegInfo();
- LibInfo = &getAnalysis<TargetLibraryInfoWrapperPass>().getTLI(Fn);
- GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : nullptr;
+ LibInfo = &FAM.getResult<TargetLibraryAnalysis>(Fn);
+ GFI = Fn.hasGC() ? &FAM.getResult<GCFunctionAnalysis>(Fn) : nullptr;
ORE = std::make_unique<OptimizationRemarkEmitter>(&Fn);
- AC = &getAnalysis<AssumptionCacheTracker>().getAssumptionCache(mf.getFunction());
- auto *PSI = &getAnalysis<ProfileSummaryInfoWrapperPass>().getPSI();
+ AC = &FAM.getResult<AssumptionAnalysis>(Fn);
+ auto *PSI = MAMP.getCachedResult<ProfileSummaryAnalysis>(*Fn.getParent());
BlockFrequencyInfo *BFI = nullptr;
+ FAM.getResult<BlockFrequencyAnalysis>(Fn);
if (PSI && PSI->hasProfileSummary() && OptLevel != CodeGenOptLevel::None)
- BFI = &getAnalysis<LazyBlockFrequencyInfoPass>().getBFI();
+ BFI = &FAM.getResult<BlockFrequencyAnalysis>(Fn);
FunctionVarLocs const *FnVarLocs = nullptr;
if (isAssignmentTrackingEnabled(*Fn.getParent()))
- FnVarLocs = getAnalysis<AssignmentTrackingAnalysis>().getResults();
+ FnVarLocs = &FAM.getResult<DebugAssignmentTrackingAnalysis>(Fn);
- ISEL_DUMP(dbgs() << "\n\n\n=== " << FuncName << "\n");
+ auto *UA = FAM.getCachedResult<UniformityInfoAnalysis>(Fn);
+ CurDAG->init(*MF, *ORE, MFAM, LibInfo, UA, PSI, BFI, FnVarLocs);
+ SwiftError->setFunction(*MF);
+
+ // Now get the optional analyzes if we want to.
+ // This is based on the possibly changed OptLevel (after optnone is taken
+ // into account). That's unfortunate but OK because it just means we won't
+ // ask for passes that have been required anyway.
+
+ if (UseMBPI && OptLevel != CodeGenOptLevel::None)
+ FuncInfo->BPI = &FAM.getResult<BranchProbabilityAnalysis>(Fn);
+ else
+ FuncInfo->BPI = nullptr;
+
+ if (OptLevel != CodeGenOptLevel::None)
+ AA = &FAM.getResult<AAManager>(Fn);
+ else
+ AA = nullptr;
+
+ SP = &FAM.getResult<SSPLayoutAnalysis>(Fn);
+
+#ifndef NDEBUG
+ TTI = &FAM.getResult<TargetIRAnalysis>(Fn);
+#endif
+}
+
+void SelectionDAGISel::initializeAnalysisResults(MachineFunctionPass &MFP) {
+ Function &Fn = MF->getFunction();
+#ifndef NDEBUG
+ FuncName = Fn.getName();
+ MatchFilterFuncName = isFunctionInPrintList(FuncName);
+#else
+ (void)MatchFilterFuncName;
+#endif
+
+ TII = MF->getSubtarget().getInstrInfo();
+ TLI = MF->getSubtarget().getTargetLowering();
+ RegInfo = &MF->getRegInfo();
+ LibInfo = &MFP.getAnalysis<TargetLibraryInfoWrapperPass>().getTLI(Fn);
+ GFI = Fn.hasGC() ? &MFP.getAnalysis<GCModuleInfo>().getFunctionInfo(Fn)
+ : nullptr;
+ ORE = std::make_unique<OptimizationRemarkEmitter>(&Fn);
+ AC = &MFP.getAnalysis<AssumptionCacheTracker>().getAssumptionCache(Fn);
+ auto *PSI = &MFP.getAnalysis<ProfileSummaryInfoWrapperPass>().getPSI();
+ BlockFrequencyInfo *BFI = nullptr;
+ if (PSI && PSI->hasProfileSummary() && OptLevel != CodeGenOptLevel::None)
+ BFI = &MFP.getAnalysis<LazyBlockFrequencyInfoPass>().getBFI();
+
+ FunctionVarLocs const *FnVarLocs = nullptr;
+ if (isAssignmentTrackingEnabled(*Fn.getParent()))
+ FnVarLocs = MFP.getAnalysis<AssignmentTrackingAnalysis>().getResults();
UniformityInfo *UA = nullptr;
- if (auto *UAPass = getAnalysisIfAvailable<UniformityInfoWrapperPass>())
+ if (auto *UAPass = MFP.getAnalysisIfAvailable<UniformityInfoWrapperPass>())
UA = &UAPass->getUniformityInfo();
- CurDAG->init(*MF, *ORE, this, LibInfo, UA, PSI, BFI, FnVarLocs);
- FuncInfo->set(Fn, *MF, CurDAG);
+ CurDAG->init(*MF, *ORE, &MFP, LibInfo, UA, PSI, BFI, FnVarLocs);
SwiftError->setFunction(*MF);
// Now get the optional analyzes if we want to.
@@ -473,15 +580,32 @@ bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
// ask for passes that have been required anyway.
if (UseMBPI && OptLevel != CodeGenOptLevel::None)
- FuncInfo->BPI = &getAnalysis<BranchProbabilityInfoWrapperPass>().getBPI();
+ FuncInfo->BPI =
+ &MFP.getAnalysis<BranchProbabilityInfoWrapperPass>().getBPI();
else
FuncInfo->BPI = nullptr;
if (OptLevel != CodeGenOptLevel::None)
- AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
+ AA = &MFP.getAnalysis<AAResultsWrapperPass>().getAAResults();
else
AA = nullptr;
+ SP = &MFP.getAnalysis<StackProtector>().getLayoutInfo();
+
+#ifndef NDEBUG
+ TTI = &MFP.getAnalysis<TargetTransformInfoWrapperPass>().getTTI(Fn);
+#endif
+}
+
+bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
+ const Function &Fn = mf.getFunction();
+
+ bool InstrRef = mf.shouldUseDebugInstrRef();
+
+ FuncInfo->set(MF->getFunction(), *MF, CurDAG);
+
+ ISEL_DUMP(dbgs() << "\n\n\n=== " << FuncName << '\n');
+
SDB->init(GFI, AA, AC, LibInfo);
MF->setHasInlineAsm(false);
@@ -779,11 +903,8 @@ void SelectionDAGISel::CodeGenAndEmitDAG() {
StringRef GroupName = "sdag";
StringRef GroupDescription = "Instruction Selection and Scheduling";
std::string BlockName;
- bool MatchFilterBB = false; (void)MatchFilterBB;
-#ifndef NDEBUG
- TargetTransformInfo &TTI =
- getAnalysis<TargetTransformInfoWrapperPass>().getTTI(*FuncInfo->Fn);
-#endif
+ bool MatchFilterBB = false;
+ (void)MatchFilterBB;
// Pre-type legalization allow creation of any node types.
CurDAG->NewNodesMustHaveLegalTypes = false;
@@ -808,7 +929,7 @@ void SelectionDAGISel::CodeGenAndEmitDAG() {
CurDAG->dump());
#ifndef NDEBUG
- if (TTI.hasBranchDivergence())
+ if (TTI->hasBranchDivergence())
CurDAG->VerifyDAGDivergence();
#endif
@@ -828,7 +949,7 @@ void SelectionDAGISel::CodeGenAndEmitDAG() {
CurDAG->dump());
#ifndef NDEBUG
- if (TTI.hasBranchDivergence())
+ if (TTI->hasBranchDivergence())
CurDAG->VerifyDAGDivergence();
#endif
@@ -850,7 +971,7 @@ void SelectionDAGISel::CodeGenAndEmitDAG() {
CurDAG->dump());
#ifndef NDEBUG
- if (TTI.hasBranchDivergence())
+ if (TTI->hasBranchDivergence())
CurDAG->VerifyDAGDivergence();
#endif
@@ -874,7 +995,7 @@ void SelectionDAGISel::CodeGenAndEmitDAG() {
CurDAG->dump());
#ifndef NDEBUG
- if (TTI.hasBranchDivergence())
+ if (TTI->hasBranchDivergence())
CurDAG->VerifyDAGDivergence();
#endif
}
@@ -892,7 +1013,7 @@ void SelectionDAGISel::CodeGenAndEmitDAG() {
CurDAG->dump());
#ifndef NDEBUG
- if (TTI.hasBranchDivergence())
+ if (TTI->hasBranchDivergence())
CurDAG->VerifyDAGDivergence();
#endif
@@ -908,7 +1029,7 @@ void SelectionDAGISel::CodeGenAndEmitDAG() {
CurDAG->dump());
#ifndef NDEBUG
- if (TTI.hasBranchDivergence())
+ if (TTI->hasBranchDivergence())
CurDAG->VerifyDAGDivergence();
#endif
@@ -928,7 +1049,7 @@ void SelectionDAGISel::CodeGenAndEmitDAG() {
CurDAG->dump());
#ifndef NDEBUG
- if (TTI.hasBranchDivergence())
+ if (TTI->hasBranchDivergence())
CurDAG->VerifyDAGDivergence();
#endif
}
@@ -948,7 +1069,7 @@ void SelectionDAGISel::CodeGenAndEmitDAG() {
CurDAG->dump());
#ifndef NDEBUG
- if (TTI.hasBranchDivergence())
+ if (TTI->hasBranchDivergence())
CurDAG->VerifyDAGDivergence();
#endif
@@ -968,7 +1089,7 @@ void SelectionDAGISel::CodeGenAndEmitDAG() {
CurDAG->dump());
#ifndef NDEBUG
- if (TTI.hasBranchDivergence())
+ if (TTI->hasBranchDivergence())
CurDAG->VerifyDAGDivergence();
#endif
@@ -1556,7 +1677,6 @@ void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
}
// Iterate over all basic blocks in the function.
- StackProtector &SP = getAnalysis<StackProtector>();
for (const BasicBlock *LLVMBB : RPOT) {
if (OptLevel != CodeGenOptLevel::None) {
bool AllPredsVisited = true;
@@ -1732,7 +1852,7 @@ void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
FastIS->recomputeInsertPt();
}
- if (SP.shouldEmitSDCheck(*LLVMBB)) {
+ if (SP->shouldEmitSDCheck(*LLVMBB)) {
bool FunctionBasedInstrumentation =
TLI->getSSPStackGuardCheck(*Fn.getParent());
SDB->SPDescriptor.initialize(LLVMBB, FuncInfo->MBBMap[LLVMBB],
@@ -1769,7 +1889,7 @@ void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
if (Fn.getParent()->getModuleFlag("eh-asynch"))
reportIPToStateForBlocks(MF);
- SP.copyToMachineFrameInfo(MF->getFrameInfo());
+ SP->copyToMachineFrameInfo(MF->getFrameInfo());
SwiftError->propagateVRegs();
>From 9a888884b3146b2a2aa44bc6792d6fe4cc44bd55 Mon Sep 17 00:00:00 2001
From: PaperChalice <liujunchang97 at outlook.com>
Date: Thu, 11 Apr 2024 19:55:40 +0800
Subject: [PATCH 02/26] AArch64 part
---
llvm/lib/Target/AArch64/AArch64.h | 2 +-
.../Target/AArch64/AArch64ISelDAGToDAG.cpp | 19 +++++++++++++------
.../Target/AArch64/AArch64TargetMachine.cpp | 2 +-
3 files changed, 15 insertions(+), 8 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64.h b/llvm/lib/Target/AArch64/AArch64.h
index b70fbe42fe5fc..0f0a22ec82936 100644
--- a/llvm/lib/Target/AArch64/AArch64.h
+++ b/llvm/lib/Target/AArch64/AArch64.h
@@ -85,7 +85,7 @@ void initializeAArch64CompressJumpTablesPass(PassRegistry&);
void initializeAArch64CondBrTuningPass(PassRegistry &);
void initializeAArch64ConditionOptimizerPass(PassRegistry&);
void initializeAArch64ConditionalComparesPass(PassRegistry &);
-void initializeAArch64DAGToDAGISelPass(PassRegistry &);
+void initializeAArch64DAGToDAGISelLegacyPass(PassRegistry &);
void initializeAArch64DeadRegisterDefinitionsPass(PassRegistry&);
void initializeAArch64ExpandPseudoPass(PassRegistry &);
void initializeAArch64GlobalsTaggingPass(PassRegistry &);
diff --git a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
index 25f2e4d7c4de6..95867a3b95b45 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
@@ -44,13 +44,11 @@ class AArch64DAGToDAGISel : public SelectionDAGISel {
const AArch64Subtarget *Subtarget;
public:
- static char ID;
-
AArch64DAGToDAGISel() = delete;
explicit AArch64DAGToDAGISel(AArch64TargetMachine &tm,
CodeGenOptLevel OptLevel)
- : SelectionDAGISel(ID, tm, OptLevel), Subtarget(nullptr) {}
+ : SelectionDAGISel(tm, OptLevel), Subtarget(nullptr) {}
bool runOnMachineFunction(MachineFunction &MF) override {
Subtarget = &MF.getSubtarget<AArch64Subtarget>();
@@ -507,11 +505,20 @@ class AArch64DAGToDAGISel : public SelectionDAGISel {
bool SelectAllActivePredicate(SDValue N);
bool SelectAnyPredicate(SDValue N);
};
+
+class AArch64DAGToDAGISelLegacy : public SelectionDAGISelLegacy {
+public:
+ static char ID;
+ explicit AArch64DAGToDAGISelLegacy(AArch64TargetMachine &tm,
+ CodeGenOptLevel OptLevel)
+ : SelectionDAGISelLegacy(
+ ID, std::make_unique<AArch64DAGToDAGISel>(tm, OptLevel)) {}
+};
} // end anonymous namespace
-char AArch64DAGToDAGISel::ID = 0;
+char AArch64DAGToDAGISelLegacy::ID = 0;
-INITIALIZE_PASS(AArch64DAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false)
+INITIALIZE_PASS(AArch64DAGToDAGISelLegacy, DEBUG_TYPE, PASS_NAME, false, false)
/// isIntImmediate - This method tests to see if the node is a constant
/// operand. If so Imm will receive the 32-bit value.
@@ -6855,7 +6862,7 @@ void AArch64DAGToDAGISel::Select(SDNode *Node) {
/// AArch64-specific DAG, ready for instruction scheduling.
FunctionPass *llvm::createAArch64ISelDag(AArch64TargetMachine &TM,
CodeGenOptLevel OptLevel) {
- return new AArch64DAGToDAGISel(TM, OptLevel);
+ return new AArch64DAGToDAGISelLegacy(TM, OptLevel);
}
/// When \p PredVT is a scalable vector predicate in the form
diff --git a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
index df802cf42526d..2f46a8ecb9ea7 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
+++ b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
@@ -253,7 +253,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64Target() {
initializeAArch64StackTaggingPass(*PR);
initializeAArch64StackTaggingPreRAPass(*PR);
initializeAArch64LowerHomogeneousPrologEpilogPass(*PR);
- initializeAArch64DAGToDAGISelPass(*PR);
+ initializeAArch64DAGToDAGISelLegacyPass(*PR);
initializeAArch64GlobalsTaggingPass(*PR);
}
>From 35ad0531adf19104561695866e0df1c8007df8f5 Mon Sep 17 00:00:00 2001
From: PaperChalice <liujunchang97 at outlook.com>
Date: Thu, 11 Apr 2024 19:55:45 +0800
Subject: [PATCH 03/26] AMDGPU part
---
llvm/lib/Target/AMDGPU/AMDGPU.h | 2 +-
llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp | 27 ++++++++++++-------
llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h | 19 +++++++------
.../lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 2 +-
llvm/lib/Target/AMDGPU/R600ISelDAGToDAG.cpp | 13 ++++++++-
5 files changed, 42 insertions(+), 21 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.h b/llvm/lib/Target/AMDGPU/AMDGPU.h
index 6016bd5187d88..46cc5f349555a 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.h
@@ -81,7 +81,7 @@ struct AMDGPUUseNativeCallsPass : PassInfoMixin<AMDGPUUseNativeCallsPass> {
PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
};
-void initializeAMDGPUDAGToDAGISelPass(PassRegistry&);
+void initializeAMDGPUDAGToDAGISelLegacyPass(PassRegistry &);
void initializeAMDGPUMachineCFGStructurizerPass(PassRegistry&);
extern char &AMDGPUMachineCFGStructurizerID;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
index c11c7a57e0596..5bdd0815c925f 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
@@ -98,8 +98,9 @@ static SDValue stripExtractLoElt(SDValue In) {
} // end anonymous namespace
-INITIALIZE_PASS_BEGIN(AMDGPUDAGToDAGISel, "amdgpu-isel",
- "AMDGPU DAG->DAG Pattern Instruction Selection", false, false)
+INITIALIZE_PASS_BEGIN(AMDGPUDAGToDAGISelLegacy, "amdgpu-isel",
+ "AMDGPU DAG->DAG Pattern Instruction Selection", false,
+ false)
INITIALIZE_PASS_DEPENDENCY(AMDGPUArgumentUsageInfo)
INITIALIZE_PASS_DEPENDENCY(AMDGPUPerfHintAnalysis)
INITIALIZE_PASS_DEPENDENCY(UniformityInfoWrapperPass)
@@ -107,19 +108,20 @@ INITIALIZE_PASS_DEPENDENCY(UniformityInfoWrapperPass)
INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass)
INITIALIZE_PASS_DEPENDENCY(LoopInfoWrapperPass)
#endif
-INITIALIZE_PASS_END(AMDGPUDAGToDAGISel, "amdgpu-isel",
- "AMDGPU DAG->DAG Pattern Instruction Selection", false, false)
+INITIALIZE_PASS_END(AMDGPUDAGToDAGISelLegacy, "amdgpu-isel",
+ "AMDGPU DAG->DAG Pattern Instruction Selection", false,
+ false)
/// This pass converts a legalized DAG into a AMDGPU-specific
// DAG, ready for instruction scheduling.
FunctionPass *llvm::createAMDGPUISelDag(TargetMachine &TM,
CodeGenOptLevel OptLevel) {
- return new AMDGPUDAGToDAGISel(TM, OptLevel);
+ return new AMDGPUDAGToDAGISelLegacy(TM, OptLevel);
}
AMDGPUDAGToDAGISel::AMDGPUDAGToDAGISel(TargetMachine &TM,
CodeGenOptLevel OptLevel)
- : SelectionDAGISel(ID, TM, OptLevel) {
+ : SelectionDAGISel(TM, OptLevel) {
EnableLateStructurizeCFG = AMDGPUTargetMachine::EnableLateStructurizeCFG;
}
@@ -200,14 +202,14 @@ bool AMDGPUDAGToDAGISel::fp16SrcZerosHighBits(unsigned Opc) const {
}
}
-void AMDGPUDAGToDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
+void AMDGPUDAGToDAGISelLegacy::getAnalysisUsage(AnalysisUsage &AU) const {
AU.addRequired<AMDGPUArgumentUsageInfo>();
AU.addRequired<UniformityInfoWrapperPass>();
#ifdef EXPENSIVE_CHECKS
AU.addRequired<DominatorTreeWrapperPass>();
AU.addRequired<LoopInfoWrapperPass>();
#endif
- SelectionDAGISel::getAnalysisUsage(AU);
+ SelectionDAGISelLegacy::getAnalysisUsage(AU);
}
bool AMDGPUDAGToDAGISel::matchLoadD16FromBuildVector(SDNode *N) const {
@@ -771,7 +773,7 @@ bool AMDGPUDAGToDAGISel::isBaseWithConstantOffset64(SDValue Addr, SDValue &LHS,
return false;
}
-StringRef AMDGPUDAGToDAGISel::getPassName() const {
+StringRef AMDGPUDAGToDAGISelLegacy::getPassName() const {
return "AMDGPU DAG->DAG Pattern Instruction Selection";
}
@@ -3596,4 +3598,9 @@ void AMDGPUDAGToDAGISel::PostprocessISelDAG() {
} while (IsModified);
}
-char AMDGPUDAGToDAGISel::ID = 0;
+AMDGPUDAGToDAGISelLegacy::AMDGPUDAGToDAGISelLegacy(TargetMachine &TM,
+ CodeGenOptLevel OptLevel)
+ : SelectionDAGISelLegacy(
+ ID, std::make_unique<AMDGPUDAGToDAGISel>(TM, OptLevel)) {}
+
+char AMDGPUDAGToDAGISelLegacy::ID = 0;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
index f987b747c0e21..7d13bf6fda5e3 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
@@ -83,21 +83,14 @@ class AMDGPUDAGToDAGISel : public SelectionDAGISel {
bool fp16SrcZerosHighBits(unsigned Opc) const;
public:
- static char ID;
-
AMDGPUDAGToDAGISel() = delete;
explicit AMDGPUDAGToDAGISel(TargetMachine &TM, CodeGenOptLevel OptLevel);
- ~AMDGPUDAGToDAGISel() override = default;
-
- void getAnalysisUsage(AnalysisUsage &AU) const override;
-
- bool matchLoadD16FromBuildVector(SDNode *N) const;
bool runOnMachineFunction(MachineFunction &MF) override;
+ bool matchLoadD16FromBuildVector(SDNode *N) const;
void PreprocessISelDAG() override;
void Select(SDNode *N) override;
- StringRef getPassName() const override;
void PostprocessISelDAG() override;
protected:
@@ -287,4 +280,14 @@ class AMDGPUDAGToDAGISel : public SelectionDAGISel {
#include "AMDGPUGenDAGISel.inc"
};
+class AMDGPUDAGToDAGISelLegacy : public SelectionDAGISelLegacy {
+public:
+ static char ID;
+
+ AMDGPUDAGToDAGISelLegacy(TargetMachine &TM, CodeGenOptLevel OptLevel);
+
+ void getAnalysisUsage(AnalysisUsage &AU) const override;
+ StringRef getPassName() const override;
+};
+
#endif // LLVM_LIB_TARGET_AMDGPU_AMDGPUISELDAGTODAG_H
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index 20329dea60275..d5117ff0481c7 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -386,7 +386,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTarget() {
initializeR600ExpandSpecialInstrsPassPass(*PR);
initializeR600VectorRegMergerPass(*PR);
initializeGlobalISel(*PR);
- initializeAMDGPUDAGToDAGISelPass(*PR);
+ initializeAMDGPUDAGToDAGISelLegacyPass(*PR);
initializeGCNDPPCombinePass(*PR);
initializeSILowerI1CopiesPass(*PR);
initializeAMDGPUGlobalISelDivergenceLoweringPass(*PR);
diff --git a/llvm/lib/Target/AMDGPU/R600ISelDAGToDAG.cpp b/llvm/lib/Target/AMDGPU/R600ISelDAGToDAG.cpp
index 293db13f34f6c..28bcf72b3b091 100644
--- a/llvm/lib/Target/AMDGPU/R600ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AMDGPU/R600ISelDAGToDAG.cpp
@@ -48,6 +48,17 @@ class R600DAGToDAGISel : public AMDGPUDAGToDAGISel {
// Include the pieces autogenerated from the target description.
#include "R600GenDAGISel.inc"
};
+
+class R600DAGToDAGISelLegacy : public SelectionDAGISelLegacy {
+public:
+ static char ID;
+ explicit R600DAGToDAGISelLegacy(TargetMachine &TM, CodeGenOptLevel OptLevel)
+ : SelectionDAGISelLegacy(
+ ID, std::make_unique<R600DAGToDAGISel>(TM, OptLevel)) {}
+};
+
+char R600DAGToDAGISelLegacy::ID = 0;
+
} // namespace
bool R600DAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
@@ -184,5 +195,5 @@ bool R600DAGToDAGISel::SelectADDRVTX_READ(SDValue Addr, SDValue &Base,
// DAG, ready for instruction scheduling.
FunctionPass *llvm::createR600ISelDag(TargetMachine &TM,
CodeGenOptLevel OptLevel) {
- return new R600DAGToDAGISel(TM, OptLevel);
+ return new R600DAGToDAGISelLegacy(TM, OptLevel);
}
>From 88f5c3274e701744e980f5217cf1cd6450a33487 Mon Sep 17 00:00:00 2001
From: PaperChalice <liujunchang97 at outlook.com>
Date: Thu, 11 Apr 2024 19:55:49 +0800
Subject: [PATCH 04/26] ARC part
---
llvm/lib/Target/ARC/ARC.h | 2 +-
llvm/lib/Target/ARC/ARCISelDAGToDAG.cpp | 18 ++++++++++++------
llvm/lib/Target/ARC/ARCTargetMachine.cpp | 2 +-
3 files changed, 14 insertions(+), 8 deletions(-)
diff --git a/llvm/lib/Target/ARC/ARC.h b/llvm/lib/Target/ARC/ARC.h
index b81016d0cee40..459f79c6eaccd 100644
--- a/llvm/lib/Target/ARC/ARC.h
+++ b/llvm/lib/Target/ARC/ARC.h
@@ -27,7 +27,7 @@ FunctionPass *createARCISelDag(ARCTargetMachine &TM, CodeGenOptLevel OptLevel);
FunctionPass *createARCExpandPseudosPass();
FunctionPass *createARCOptAddrMode();
FunctionPass *createARCBranchFinalizePass();
-void initializeARCDAGToDAGISelPass(PassRegistry &);
+void initializeARCDAGToDAGISelLegacyPass(PassRegistry &);
} // end namespace llvm
diff --git a/llvm/lib/Target/ARC/ARCISelDAGToDAG.cpp b/llvm/lib/Target/ARC/ARCISelDAGToDAG.cpp
index 17c2d7bb13b47..5e6cfa539b6d8 100644
--- a/llvm/lib/Target/ARC/ARCISelDAGToDAG.cpp
+++ b/llvm/lib/Target/ARC/ARCISelDAGToDAG.cpp
@@ -41,12 +41,10 @@ namespace {
class ARCDAGToDAGISel : public SelectionDAGISel {
public:
- static char ID;
-
ARCDAGToDAGISel() = delete;
ARCDAGToDAGISel(ARCTargetMachine &TM, CodeGenOptLevel OptLevel)
- : SelectionDAGISel(ID, TM, OptLevel) {}
+ : SelectionDAGISel(TM, OptLevel) {}
void Select(SDNode *N) override;
@@ -60,17 +58,25 @@ class ARCDAGToDAGISel : public SelectionDAGISel {
#include "ARCGenDAGISel.inc"
};
-char ARCDAGToDAGISel::ID;
+class ARCDAGToDAGISelLegacy : public SelectionDAGISelLegacy {
+public:
+ static char ID;
+ explicit ARCDAGToDAGISelLegacy(ARCTargetMachine &TM, CodeGenOptLevel OptLevel)
+ : SelectionDAGISelLegacy(
+ ID, std::make_unique<ARCDAGToDAGISel>(TM, OptLevel)) {}
+};
+
+char ARCDAGToDAGISelLegacy::ID;
} // end anonymous namespace
-INITIALIZE_PASS(ARCDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false)
+INITIALIZE_PASS(ARCDAGToDAGISelLegacy, DEBUG_TYPE, PASS_NAME, false, false)
/// This pass converts a legalized DAG into a ARC-specific DAG, ready for
/// instruction scheduling.
FunctionPass *llvm::createARCISelDag(ARCTargetMachine &TM,
CodeGenOptLevel OptLevel) {
- return new ARCDAGToDAGISel(TM, OptLevel);
+ return new ARCDAGToDAGISelLegacy(TM, OptLevel);
}
bool ARCDAGToDAGISel::SelectAddrModeImm(SDValue Addr, SDValue &Base,
diff --git a/llvm/lib/Target/ARC/ARCTargetMachine.cpp b/llvm/lib/Target/ARC/ARCTargetMachine.cpp
index f50c3c0265e34..5f021cf1f442e 100644
--- a/llvm/lib/Target/ARC/ARCTargetMachine.cpp
+++ b/llvm/lib/Target/ARC/ARCTargetMachine.cpp
@@ -97,7 +97,7 @@ MachineFunctionInfo *ARCTargetMachine::createMachineFunctionInfo(
extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARCTarget() {
RegisterTargetMachine<ARCTargetMachine> X(getTheARCTarget());
PassRegistry &PR = *PassRegistry::getPassRegistry();
- initializeARCDAGToDAGISelPass(PR);
+ initializeARCDAGToDAGISelLegacyPass(PR);
}
TargetTransformInfo
>From 5d28355a8fc96e8b30cfc67780f09d69024d9cb4 Mon Sep 17 00:00:00 2001
From: PaperChalice <liujunchang97 at outlook.com>
Date: Thu, 11 Apr 2024 19:55:54 +0800
Subject: [PATCH 05/26] ARM part
---
llvm/lib/Target/ARM/ARM.h | 2 +-
llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp | 18 ++++++++++++------
llvm/lib/Target/ARM/ARMTargetMachine.cpp | 2 +-
3 files changed, 14 insertions(+), 8 deletions(-)
diff --git a/llvm/lib/Target/ARM/ARM.h b/llvm/lib/Target/ARM/ARM.h
index b96e018229852..0b7045eadde7f 100644
--- a/llvm/lib/Target/ARM/ARM.h
+++ b/llvm/lib/Target/ARM/ARM.h
@@ -64,7 +64,7 @@ void LowerARMMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
void initializeARMBlockPlacementPass(PassRegistry &);
void initializeARMBranchTargetsPass(PassRegistry &);
void initializeARMConstantIslandsPass(PassRegistry &);
-void initializeARMDAGToDAGISelPass(PassRegistry &);
+void initializeARMDAGToDAGISelLegacyPass(PassRegistry &);
void initializeARMExpandPseudoPass(PassRegistry &);
void initializeARMFixCortexA57AES1742098Pass(PassRegistry &);
void initializeARMLoadStoreOptPass(PassRegistry &);
diff --git a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
index 20dd3e7baf849..7ffc64378ef4b 100644
--- a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -59,12 +59,10 @@ class ARMDAGToDAGISel : public SelectionDAGISel {
const ARMSubtarget *Subtarget;
public:
- static char ID;
-
ARMDAGToDAGISel() = delete;
explicit ARMDAGToDAGISel(ARMBaseTargetMachine &tm, CodeGenOptLevel OptLevel)
- : SelectionDAGISel(ID, tm, OptLevel) {}
+ : SelectionDAGISel(tm, OptLevel) {}
bool runOnMachineFunction(MachineFunction &MF) override {
// Reset the subtarget each time through.
@@ -362,11 +360,19 @@ class ARMDAGToDAGISel : public SelectionDAGISel {
/// selected when N would have been selected.
void replaceDAGValue(const SDValue &N, SDValue M);
};
+
+class ARMDAGToDAGISelLegacy : public SelectionDAGISelLegacy {
+public:
+ static char ID;
+ ARMDAGToDAGISelLegacy(ARMBaseTargetMachine &tm, CodeGenOptLevel OptLevel)
+ : SelectionDAGISelLegacy(
+ ID, std::make_unique<ARMDAGToDAGISel>(tm, OptLevel)) {}
+};
}
-char ARMDAGToDAGISel::ID = 0;
+char ARMDAGToDAGISelLegacy::ID = 0;
-INITIALIZE_PASS(ARMDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false)
+INITIALIZE_PASS(ARMDAGToDAGISelLegacy, DEBUG_TYPE, PASS_NAME, false, false)
/// isInt32Immediate - This method tests to see if the node is a 32-bit constant
/// operand. If so Imm will receive the 32-bit value.
@@ -5886,5 +5892,5 @@ bool ARMDAGToDAGISel::SelectInlineAsmMemoryOperand(
///
FunctionPass *llvm::createARMISelDag(ARMBaseTargetMachine &TM,
CodeGenOptLevel OptLevel) {
- return new ARMDAGToDAGISel(TM, OptLevel);
+ return new ARMDAGToDAGISelLegacy(TM, OptLevel);
}
diff --git a/llvm/lib/Target/ARM/ARMTargetMachine.cpp b/llvm/lib/Target/ARM/ARMTargetMachine.cpp
index 4ef00df57ef9a..7553778c57403 100644
--- a/llvm/lib/Target/ARM/ARMTargetMachine.cpp
+++ b/llvm/lib/Target/ARM/ARMTargetMachine.cpp
@@ -110,7 +110,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARMTarget() {
initializeARMSLSHardeningPass(Registry);
initializeMVELaneInterleavingPass(Registry);
initializeARMFixCortexA57AES1742098Pass(Registry);
- initializeARMDAGToDAGISelPass(Registry);
+ initializeARMDAGToDAGISelLegacyPass(Registry);
}
static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
>From 214eaacba8cb28215e023765341a5b83f17546b0 Mon Sep 17 00:00:00 2001
From: PaperChalice <liujunchang97 at outlook.com>
Date: Thu, 11 Apr 2024 19:55:59 +0800
Subject: [PATCH 06/26] AVR part
---
llvm/lib/Target/AVR/AVR.h | 2 +-
llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp | 16 ++++++++++++----
llvm/lib/Target/AVR/AVRTargetMachine.cpp | 2 +-
3 files changed, 14 insertions(+), 6 deletions(-)
diff --git a/llvm/lib/Target/AVR/AVR.h b/llvm/lib/Target/AVR/AVR.h
index 4b1336ecd6618..0e67bb4eb50c2 100644
--- a/llvm/lib/Target/AVR/AVR.h
+++ b/llvm/lib/Target/AVR/AVR.h
@@ -31,7 +31,7 @@ FunctionPass *createAVRExpandPseudoPass();
FunctionPass *createAVRFrameAnalyzerPass();
FunctionPass *createAVRBranchSelectionPass();
-void initializeAVRDAGToDAGISelPass(PassRegistry &);
+void initializeAVRDAGToDAGISelLegacyPass(PassRegistry &);
void initializeAVRExpandPseudoPass(PassRegistry &);
void initializeAVRShiftExpandPass(PassRegistry &);
diff --git a/llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp b/llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp
index e67a1e2ed5090..d6712eb0b78db 100644
--- a/llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp
@@ -34,7 +34,7 @@ class AVRDAGToDAGISel : public SelectionDAGISel {
AVRDAGToDAGISel() = delete;
AVRDAGToDAGISel(AVRTargetMachine &TM, CodeGenOptLevel OptLevel)
- : SelectionDAGISel(ID, TM, OptLevel), Subtarget(nullptr) {}
+ : SelectionDAGISel(TM, OptLevel), Subtarget(nullptr) {}
bool runOnMachineFunction(MachineFunction &MF) override;
@@ -60,11 +60,19 @@ class AVRDAGToDAGISel : public SelectionDAGISel {
const AVRSubtarget *Subtarget;
};
+class AVRDAGToDAGISelLegacy : public SelectionDAGISelLegacy {
+public:
+ static char ID;
+ AVRDAGToDAGISelLegacy(AVRTargetMachine &TM, CodeGenOptLevel OptLevel)
+ : SelectionDAGISelLegacy(
+ ID, std::make_unique<AVRDAGToDAGISel>(TM, OptLevel)) {}
+};
+
} // namespace
-char AVRDAGToDAGISel::ID = 0;
+char AVRDAGToDAGISelLegacy::ID = 0;
-INITIALIZE_PASS(AVRDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false)
+INITIALIZE_PASS(AVRDAGToDAGISelLegacy, DEBUG_TYPE, PASS_NAME, false, false)
bool AVRDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
Subtarget = &MF.getSubtarget<AVRSubtarget>();
@@ -586,5 +594,5 @@ bool AVRDAGToDAGISel::trySelect(SDNode *N) {
FunctionPass *llvm::createAVRISelDag(AVRTargetMachine &TM,
CodeGenOptLevel OptLevel) {
- return new AVRDAGToDAGISel(TM, OptLevel);
+ return new AVRDAGToDAGISelLegacy(TM, OptLevel);
}
diff --git a/llvm/lib/Target/AVR/AVRTargetMachine.cpp b/llvm/lib/Target/AVR/AVRTargetMachine.cpp
index e0776a6cab432..a8c967f865c0c 100644
--- a/llvm/lib/Target/AVR/AVRTargetMachine.cpp
+++ b/llvm/lib/Target/AVR/AVRTargetMachine.cpp
@@ -95,7 +95,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAVRTarget() {
auto &PR = *PassRegistry::getPassRegistry();
initializeAVRExpandPseudoPass(PR);
initializeAVRShiftExpandPass(PR);
- initializeAVRDAGToDAGISelPass(PR);
+ initializeAVRDAGToDAGISelLegacyPass(PR);
}
const AVRSubtarget *AVRTargetMachine::getSubtargetImpl() const {
>From 8d1108e8cf6e3814694f710916fd4f597d353c45 Mon Sep 17 00:00:00 2001
From: PaperChalice <liujunchang97 at outlook.com>
Date: Thu, 11 Apr 2024 19:56:06 +0800
Subject: [PATCH 07/26] BPF part
---
llvm/lib/Target/BPF/BPF.h | 2 +-
llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp | 15 +++++++++++----
llvm/lib/Target/BPF/BPFTargetMachine.cpp | 2 +-
3 files changed, 13 insertions(+), 6 deletions(-)
diff --git a/llvm/lib/Target/BPF/BPF.h b/llvm/lib/Target/BPF/BPF.h
index bbdbdbbde5322..694d7bacf6421 100644
--- a/llvm/lib/Target/BPF/BPF.h
+++ b/llvm/lib/Target/BPF/BPF.h
@@ -35,7 +35,7 @@ InstructionSelector *createBPFInstructionSelector(const BPFTargetMachine &,
const BPFRegisterBankInfo &);
void initializeBPFCheckAndAdjustIRPass(PassRegistry&);
-void initializeBPFDAGToDAGISelPass(PassRegistry &);
+void initializeBPFDAGToDAGISelLegacyPass(PassRegistry &);
void initializeBPFMIPeepholePass(PassRegistry &);
void initializeBPFMIPreEmitCheckingPass(PassRegistry&);
void initializeBPFMIPreEmitPeepholePass(PassRegistry &);
diff --git a/llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp b/llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp
index 7b8bcb2c5866d..4cc209bf8ae8d 100644
--- a/llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp
+++ b/llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp
@@ -51,7 +51,7 @@ class BPFDAGToDAGISel : public SelectionDAGISel {
BPFDAGToDAGISel() = delete;
explicit BPFDAGToDAGISel(BPFTargetMachine &TM)
- : SelectionDAGISel(ID, TM), Subtarget(nullptr) {}
+ : SelectionDAGISel(TM), Subtarget(nullptr) {}
bool runOnMachineFunction(MachineFunction &MF) override {
// Reset the subtarget each time through.
@@ -94,11 +94,18 @@ class BPFDAGToDAGISel : public SelectionDAGISel {
// Mapping from ConstantStruct global value to corresponding byte-list values
std::map<const void *, val_vec_type> cs_vals_;
};
+
+class BPFDAGToDAGISelLegacy : public SelectionDAGISelLegacy {
+public:
+ static char ID;
+ BPFDAGToDAGISelLegacy(BPFTargetMachine &TM)
+ : SelectionDAGISelLegacy(ID, std::make_unique<BPFDAGToDAGISel>(TM)) {}
+};
} // namespace
-char BPFDAGToDAGISel::ID = 0;
+char BPFDAGToDAGISelLegacy::ID = 0;
-INITIALIZE_PASS(BPFDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false)
+INITIALIZE_PASS(BPFDAGToDAGISelLegacy, DEBUG_TYPE, PASS_NAME, false, false)
// ComplexPattern used on BPF Load/Store instructions
bool BPFDAGToDAGISel::SelectAddr(SDValue Addr, SDValue &Base, SDValue &Offset) {
@@ -489,5 +496,5 @@ void BPFDAGToDAGISel::PreprocessTrunc(SDNode *Node,
}
FunctionPass *llvm::createBPFISelDag(BPFTargetMachine &TM) {
- return new BPFDAGToDAGISel(TM);
+ return new BPFDAGToDAGISelLegacy(TM);
}
diff --git a/llvm/lib/Target/BPF/BPFTargetMachine.cpp b/llvm/lib/Target/BPF/BPFTargetMachine.cpp
index a7bed69b0f2ab..7b73c9f4a1e4c 100644
--- a/llvm/lib/Target/BPF/BPFTargetMachine.cpp
+++ b/llvm/lib/Target/BPF/BPFTargetMachine.cpp
@@ -48,7 +48,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeBPFTarget() {
initializeGlobalISel(PR);
initializeBPFCheckAndAdjustIRPass(PR);
initializeBPFMIPeepholePass(PR);
- initializeBPFDAGToDAGISelPass(PR);
+ initializeBPFDAGToDAGISelLegacyPass(PR);
}
// DataLayout: little or big endian
>From c506269170f42ead95bf7fef1b64c1eaf685152e Mon Sep 17 00:00:00 2001
From: PaperChalice <liujunchang97 at outlook.com>
Date: Thu, 11 Apr 2024 19:56:12 +0800
Subject: [PATCH 08/26] CSKY part
---
llvm/lib/Target/CSKY/CSKY.h | 2 +-
llvm/lib/Target/CSKY/CSKYISelDAGToDAG.cpp | 19 +++++++++++++------
llvm/lib/Target/CSKY/CSKYTargetMachine.cpp | 2 +-
3 files changed, 15 insertions(+), 8 deletions(-)
diff --git a/llvm/lib/Target/CSKY/CSKY.h b/llvm/lib/Target/CSKY/CSKY.h
index 7ca630c9abaaf..21ebf13f20644 100644
--- a/llvm/lib/Target/CSKY/CSKY.h
+++ b/llvm/lib/Target/CSKY/CSKY.h
@@ -27,7 +27,7 @@ FunctionPass *createCSKYISelDag(CSKYTargetMachine &TM,
FunctionPass *createCSKYConstantIslandPass();
void initializeCSKYConstantIslandsPass(PassRegistry &);
-void initializeCSKYDAGToDAGISelPass(PassRegistry &);
+void initializeCSKYDAGToDAGISelLegacyPass(PassRegistry &);
} // namespace llvm
diff --git a/llvm/lib/Target/CSKY/CSKYISelDAGToDAG.cpp b/llvm/lib/Target/CSKY/CSKYISelDAGToDAG.cpp
index c0c23a45d1551..22da80b3eddcc 100644
--- a/llvm/lib/Target/CSKY/CSKYISelDAGToDAG.cpp
+++ b/llvm/lib/Target/CSKY/CSKYISelDAGToDAG.cpp
@@ -28,10 +28,8 @@ class CSKYDAGToDAGISel : public SelectionDAGISel {
const CSKYSubtarget *Subtarget;
public:
- static char ID;
-
explicit CSKYDAGToDAGISel(CSKYTargetMachine &TM, CodeGenOptLevel OptLevel)
- : SelectionDAGISel(ID, TM, OptLevel) {}
+ : SelectionDAGISel(TM, OptLevel) {}
bool runOnMachineFunction(MachineFunction &MF) override {
// Reset the subtarget each time through.
@@ -54,11 +52,20 @@ class CSKYDAGToDAGISel : public SelectionDAGISel {
#include "CSKYGenDAGISel.inc"
};
+
+class CSKYDAGToDAGISelLegacy : public SelectionDAGISelLegacy {
+public:
+ static char ID;
+ explicit CSKYDAGToDAGISelLegacy(CSKYTargetMachine &TM,
+ CodeGenOptLevel OptLevel)
+ : SelectionDAGISelLegacy(
+ ID, std::make_unique<CSKYDAGToDAGISel>(TM, OptLevel)) {}
+};
} // namespace
-char CSKYDAGToDAGISel::ID = 0;
+char CSKYDAGToDAGISelLegacy::ID = 0;
-INITIALIZE_PASS(CSKYDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false)
+INITIALIZE_PASS(CSKYDAGToDAGISelLegacy, DEBUG_TYPE, PASS_NAME, false, false)
void CSKYDAGToDAGISel::Select(SDNode *N) {
// If we have a custom node, we have already selected
@@ -401,5 +408,5 @@ bool CSKYDAGToDAGISel::SelectInlineAsmMemoryOperand(
FunctionPass *llvm::createCSKYISelDag(CSKYTargetMachine &TM,
CodeGenOptLevel OptLevel) {
- return new CSKYDAGToDAGISel(TM, OptLevel);
+ return new CSKYDAGToDAGISelLegacy(TM, OptLevel);
}
diff --git a/llvm/lib/Target/CSKY/CSKYTargetMachine.cpp b/llvm/lib/Target/CSKY/CSKYTargetMachine.cpp
index 0bbfabe93147c..a756061e307a4 100644
--- a/llvm/lib/Target/CSKY/CSKYTargetMachine.cpp
+++ b/llvm/lib/Target/CSKY/CSKYTargetMachine.cpp
@@ -30,7 +30,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeCSKYTarget() {
PassRegistry *Registry = PassRegistry::getPassRegistry();
initializeCSKYConstantIslandsPass(*Registry);
- initializeCSKYDAGToDAGISelPass(*Registry);
+ initializeCSKYDAGToDAGISelLegacyPass(*Registry);
}
static std::string computeDataLayout(const Triple &TT) {
>From a2fa570ed61a1ec189f97b65bdef0d814d5cae35 Mon Sep 17 00:00:00 2001
From: PaperChalice <liujunchang97 at outlook.com>
Date: Thu, 11 Apr 2024 19:56:17 +0800
Subject: [PATCH 09/26] Hexagon part
---
llvm/lib/Target/Hexagon/Hexagon.h | 2 +-
llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp | 11 ++++++++---
llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.h | 12 +++++++++---
llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp | 2 +-
4 files changed, 19 insertions(+), 8 deletions(-)
diff --git a/llvm/lib/Target/Hexagon/Hexagon.h b/llvm/lib/Target/Hexagon/Hexagon.h
index 861f61a0bfd23..4a290c798c27e 100644
--- a/llvm/lib/Target/Hexagon/Hexagon.h
+++ b/llvm/lib/Target/Hexagon/Hexagon.h
@@ -22,7 +22,7 @@ namespace llvm {
/// Creates a Hexagon-specific Target Transformation Info pass.
ImmutablePass *createHexagonTargetTransformInfoPass(const HexagonTargetMachine *TM);
- void initializeHexagonDAGToDAGISelPass(PassRegistry &);
+ void initializeHexagonDAGToDAGISelLegacyPass(PassRegistry &);
} // end namespace llvm;
#endif
diff --git a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
index 6fe3fe0d36b9e..febbc95ec0db4 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
@@ -60,13 +60,18 @@ namespace llvm {
/// Hexagon-specific DAG, ready for instruction scheduling.
FunctionPass *createHexagonISelDag(HexagonTargetMachine &TM,
CodeGenOptLevel OptLevel) {
- return new HexagonDAGToDAGISel(TM, OptLevel);
+ return new HexagonDAGToDAGISelLegacy(TM, OptLevel);
}
}
-char HexagonDAGToDAGISel::ID = 0;
+HexagonDAGToDAGISelLegacy::HexagonDAGToDAGISelLegacy(HexagonTargetMachine &tm,
+ CodeGenOptLevel OptLevel)
+ : SelectionDAGISelLegacy(
+ ID, std::make_unique<HexagonDAGToDAGISel>(tm, OptLevel)) {}
-INITIALIZE_PASS(HexagonDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false)
+char HexagonDAGToDAGISelLegacy::ID = 0;
+
+INITIALIZE_PASS(HexagonDAGToDAGISelLegacy, DEBUG_TYPE, PASS_NAME, false, false)
void HexagonDAGToDAGISel::SelectIndexedLoad(LoadSDNode *LD, const SDLoc &dl) {
SDValue Chain = LD->getChain();
diff --git a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.h b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.h
index 50162b1079964..2d23aeecda6d8 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.h
+++ b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.h
@@ -29,14 +29,13 @@ class HexagonDAGToDAGISel : public SelectionDAGISel {
const HexagonSubtarget *HST;
const HexagonInstrInfo *HII;
const HexagonRegisterInfo *HRI;
-public:
- static char ID;
+public:
HexagonDAGToDAGISel() = delete;
explicit HexagonDAGToDAGISel(HexagonTargetMachine &tm,
CodeGenOptLevel OptLevel)
- : SelectionDAGISel(ID, tm, OptLevel), HST(nullptr), HII(nullptr),
+ : SelectionDAGISel(tm, OptLevel), HST(nullptr), HII(nullptr),
HRI(nullptr) {}
bool runOnMachineFunction(MachineFunction &MF) override {
@@ -162,6 +161,13 @@ class HexagonDAGToDAGISel : public SelectionDAGISel {
SDValue balanceSubTree(SDNode *N, bool Factorize = false);
void rebalanceAddressTrees();
}; // end HexagonDAGToDAGISel
+
+class HexagonDAGToDAGISelLegacy : public SelectionDAGISelLegacy {
+public:
+ static char ID;
+ explicit HexagonDAGToDAGISelLegacy(HexagonTargetMachine &tm,
+ CodeGenOptLevel OptLevel);
+};
}
#endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONISELDAGTODAG_H
diff --git a/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp b/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
index 3a792ecfd03d5..e4886506de19c 100644
--- a/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
@@ -254,7 +254,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeHexagonTarget() {
initializeHexagonVectorCombineLegacyPass(PR);
initializeHexagonVectorLoopCarriedReuseLegacyPassPass(PR);
initializeHexagonVExtractPass(PR);
- initializeHexagonDAGToDAGISelPass(PR);
+ initializeHexagonDAGToDAGISelLegacyPass(PR);
}
HexagonTargetMachine::HexagonTargetMachine(const Target &T, const Triple &TT,
>From 8695efbf368fa8419897489186312c16ad81620f Mon Sep 17 00:00:00 2001
From: PaperChalice <liujunchang97 at outlook.com>
Date: Thu, 11 Apr 2024 19:56:23 +0800
Subject: [PATCH 10/26] Lanai part
---
llvm/lib/Target/Lanai/Lanai.h | 2 +-
llvm/lib/Target/Lanai/LanaiISelDAGToDAG.cpp | 19 +++++++++++--------
llvm/lib/Target/Lanai/LanaiTargetMachine.cpp | 2 +-
3 files changed, 13 insertions(+), 10 deletions(-)
diff --git a/llvm/lib/Target/Lanai/Lanai.h b/llvm/lib/Target/Lanai/Lanai.h
index 0f87b17b773e3..72a7efc58062d 100644
--- a/llvm/lib/Target/Lanai/Lanai.h
+++ b/llvm/lib/Target/Lanai/Lanai.h
@@ -37,7 +37,7 @@ FunctionPass *createLanaiMemAluCombinerPass();
// operations.
FunctionPass *createLanaiSetflagAluCombinerPass();
-void initializeLanaiDAGToDAGISelPass(PassRegistry &);
+void initializeLanaiDAGToDAGISelLegacyPass(PassRegistry &);
} // namespace llvm
diff --git a/llvm/lib/Target/Lanai/LanaiISelDAGToDAG.cpp b/llvm/lib/Target/Lanai/LanaiISelDAGToDAG.cpp
index 6f5495ac00e15..84b57d90af899 100644
--- a/llvm/lib/Target/Lanai/LanaiISelDAGToDAG.cpp
+++ b/llvm/lib/Target/Lanai/LanaiISelDAGToDAG.cpp
@@ -53,11 +53,7 @@ class LanaiDAGToDAGISel : public SelectionDAGISel {
LanaiDAGToDAGISel() = delete;
explicit LanaiDAGToDAGISel(LanaiTargetMachine &TargetMachine)
- : SelectionDAGISel(ID, TargetMachine) {}
-
- bool runOnMachineFunction(MachineFunction &MF) override {
- return SelectionDAGISel::runOnMachineFunction(MF);
- }
+ : SelectionDAGISel(TargetMachine) {}
bool SelectInlineAsmMemoryOperand(const SDValue &Op,
InlineAsm::ConstraintCode ConstraintCode,
@@ -97,11 +93,18 @@ bool canBeRepresentedAsSls(const ConstantSDNode &CN) {
return isInt<21>(CN.getSExtValue()) && ((CN.getSExtValue() & 0x3) == 0);
}
+class LanaiDAGToDAGISelLegacy : public SelectionDAGISelLegacy {
+public:
+ static char ID;
+ explicit LanaiDAGToDAGISelLegacy(LanaiTargetMachine &TM)
+ : SelectionDAGISelLegacy(ID, std::make_unique<LanaiDAGToDAGISel>(TM)) {}
+};
+
} // namespace
-char LanaiDAGToDAGISel::ID = 0;
+char LanaiDAGToDAGISelLegacy::ID = 0;
-INITIALIZE_PASS(LanaiDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false)
+INITIALIZE_PASS(LanaiDAGToDAGISelLegacy, DEBUG_TYPE, PASS_NAME, false, false)
// Helper functions for ComplexPattern used on LanaiInstrInfo
// Used on Lanai Load/Store instructions.
@@ -366,5 +369,5 @@ void LanaiDAGToDAGISel::selectFrameIndex(SDNode *Node) {
// createLanaiISelDag - This pass converts a legalized DAG into a
// Lanai-specific DAG, ready for instruction scheduling.
FunctionPass *llvm::createLanaiISelDag(LanaiTargetMachine &TM) {
- return new LanaiDAGToDAGISel(TM);
+ return new LanaiDAGToDAGISelLegacy(TM);
}
diff --git a/llvm/lib/Target/Lanai/LanaiTargetMachine.cpp b/llvm/lib/Target/Lanai/LanaiTargetMachine.cpp
index 2357221b0120f..68eb12f87d89a 100644
--- a/llvm/lib/Target/Lanai/LanaiTargetMachine.cpp
+++ b/llvm/lib/Target/Lanai/LanaiTargetMachine.cpp
@@ -37,7 +37,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeLanaiTarget() {
RegisterTargetMachine<LanaiTargetMachine> registered_target(
getTheLanaiTarget());
PassRegistry &PR = *PassRegistry::getPassRegistry();
- initializeLanaiDAGToDAGISelPass(PR);
+ initializeLanaiDAGToDAGISelLegacyPass(PR);
}
static std::string computeDataLayout() {
>From f40c54fdf07598c7c5ceeae3e02c4cea3b8dcef5 Mon Sep 17 00:00:00 2001
From: PaperChalice <liujunchang97 at outlook.com>
Date: Thu, 11 Apr 2024 19:56:29 +0800
Subject: [PATCH 11/26] LoongArch part
---
llvm/lib/Target/LoongArch/LoongArch.h | 2 +-
llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.cpp | 11 ++++++++---
llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.h | 8 +++++++-
llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp | 2 +-
4 files changed, 17 insertions(+), 6 deletions(-)
diff --git a/llvm/lib/Target/LoongArch/LoongArch.h b/llvm/lib/Target/LoongArch/LoongArch.h
index 2109176d49982..0928ea31054a4 100644
--- a/llvm/lib/Target/LoongArch/LoongArch.h
+++ b/llvm/lib/Target/LoongArch/LoongArch.h
@@ -38,7 +38,7 @@ FunctionPass *createLoongArchISelDag(LoongArchTargetMachine &TM);
FunctionPass *createLoongArchOptWInstrsPass();
FunctionPass *createLoongArchPreRAExpandPseudoPass();
FunctionPass *createLoongArchExpandPseudoPass();
-void initializeLoongArchDAGToDAGISelPass(PassRegistry &);
+void initializeLoongArchDAGToDAGISelLegacyPass(PassRegistry &);
void initializeLoongArchExpandAtomicPseudoPass(PassRegistry &);
void initializeLoongArchOptWInstrsPass(PassRegistry &);
void initializeLoongArchPreRAExpandPseudoPass(PassRegistry &);
diff --git a/llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.cpp b/llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.cpp
index 726856bda5dc5..b6ade6b978d2c 100644
--- a/llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.cpp
+++ b/llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.cpp
@@ -22,9 +22,14 @@ using namespace llvm;
#define DEBUG_TYPE "loongarch-isel"
#define PASS_NAME "LoongArch DAG->DAG Pattern Instruction Selection"
-char LoongArchDAGToDAGISel::ID;
+char LoongArchDAGToDAGISelLegacy::ID;
-INITIALIZE_PASS(LoongArchDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false)
+LoongArchDAGToDAGISelLegacy::LoongArchDAGToDAGISelLegacy(
+ LoongArchTargetMachine &TM)
+ : SelectionDAGISelLegacy(ID, std::make_unique<LoongArchDAGToDAGISel>(TM)) {}
+
+INITIALIZE_PASS(LoongArchDAGToDAGISelLegacy, DEBUG_TYPE, PASS_NAME, false,
+ false)
void LoongArchDAGToDAGISel::Select(SDNode *Node) {
// If we have a custom node, we have already selected.
@@ -414,5 +419,5 @@ bool LoongArchDAGToDAGISel::selectVSplatUimmPow2(SDValue N,
// This pass converts a legalized DAG into a LoongArch-specific DAG, ready
// for instruction scheduling.
FunctionPass *llvm::createLoongArchISelDag(LoongArchTargetMachine &TM) {
- return new LoongArchDAGToDAGISel(TM);
+ return new LoongArchDAGToDAGISelLegacy(TM);
}
diff --git a/llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.h b/llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.h
index 48a178bfeb95f..5c199a57de48a 100644
--- a/llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.h
+++ b/llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.h
@@ -29,7 +29,7 @@ class LoongArchDAGToDAGISel : public SelectionDAGISel {
LoongArchDAGToDAGISel() = delete;
explicit LoongArchDAGToDAGISel(LoongArchTargetMachine &TM)
- : SelectionDAGISel(ID, TM) {}
+ : SelectionDAGISel(TM) {}
bool runOnMachineFunction(MachineFunction &MF) override {
Subtarget = &MF.getSubtarget<LoongArchSubtarget>();
@@ -69,6 +69,12 @@ class LoongArchDAGToDAGISel : public SelectionDAGISel {
#include "LoongArchGenDAGISel.inc"
};
+class LoongArchDAGToDAGISelLegacy : public SelectionDAGISelLegacy {
+public:
+ static char ID;
+ explicit LoongArchDAGToDAGISelLegacy(LoongArchTargetMachine &TM);
+};
+
} // end namespace llvm
#endif // LLVM_LIB_TARGET_LOONGARCH_LOONGARCHISELDAGTODAG_H
diff --git a/llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp b/llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp
index 2b2d4e478cc82..83466d53f84dd 100644
--- a/llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp
+++ b/llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp
@@ -36,7 +36,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeLoongArchTarget() {
auto *PR = PassRegistry::getPassRegistry();
initializeLoongArchOptWInstrsPass(*PR);
initializeLoongArchPreRAExpandPseudoPass(*PR);
- initializeLoongArchDAGToDAGISelPass(*PR);
+ initializeLoongArchDAGToDAGISelLegacyPass(*PR);
}
static cl::opt<bool>
>From cdda2aece3b7576b1b9682b0d58aee5131d586b8 Mon Sep 17 00:00:00 2001
From: PaperChalice <liujunchang97 at outlook.com>
Date: Thu, 11 Apr 2024 19:56:36 +0800
Subject: [PATCH 12/26] M68k part
---
llvm/lib/Target/M68k/M68k.h | 2 +-
llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp | 17 +++++++++++------
llvm/lib/Target/M68k/M68kTargetMachine.cpp | 2 +-
3 files changed, 13 insertions(+), 8 deletions(-)
diff --git a/llvm/lib/Target/M68k/M68k.h b/llvm/lib/Target/M68k/M68k.h
index 1d0f383dc5c94..5db9d796d1d3c 100644
--- a/llvm/lib/Target/M68k/M68k.h
+++ b/llvm/lib/Target/M68k/M68k.h
@@ -46,7 +46,7 @@ InstructionSelector *
createM68kInstructionSelector(const M68kTargetMachine &, const M68kSubtarget &,
const M68kRegisterBankInfo &);
-void initializeM68kDAGToDAGISelPass(PassRegistry &);
+void initializeM68kDAGToDAGISelLegacyPass(PassRegistry &);
void initializeM68kExpandPseudoPass(PassRegistry &);
void initializeM68kGlobalBaseRegPass(PassRegistry &);
void initializeM68kCollapseMOVEMPass(PassRegistry &);
diff --git a/llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp b/llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp
index e3aa9cb508479..dc89fec8108c2 100644
--- a/llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp
+++ b/llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp
@@ -174,12 +174,10 @@ namespace {
class M68kDAGToDAGISel : public SelectionDAGISel {
public:
- static char ID;
-
M68kDAGToDAGISel() = delete;
explicit M68kDAGToDAGISel(M68kTargetMachine &TM)
- : SelectionDAGISel(ID, TM), Subtarget(nullptr) {}
+ : SelectionDAGISel(TM), Subtarget(nullptr) {}
bool runOnMachineFunction(MachineFunction &MF) override;
bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const override;
@@ -316,11 +314,18 @@ class M68kDAGToDAGISel : public SelectionDAGISel {
SDNode *getGlobalBaseReg();
};
-char M68kDAGToDAGISel::ID;
+class M68kDAGToDAGISelLegacy : public SelectionDAGISelLegacy {
+public:
+ static char ID;
+ explicit M68kDAGToDAGISelLegacy(M68kTargetMachine &TM)
+ : SelectionDAGISelLegacy(ID, std::make_unique<M68kDAGToDAGISel>(TM)) {}
+};
+
+char M68kDAGToDAGISelLegacy::ID;
} // namespace
-INITIALIZE_PASS(M68kDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false)
+INITIALIZE_PASS(M68kDAGToDAGISelLegacy, DEBUG_TYPE, PASS_NAME, false, false)
bool M68kDAGToDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
SDNode *Root) const {
@@ -357,7 +362,7 @@ bool M68kDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
/// This pass converts a legalized DAG into a M68k-specific DAG,
/// ready for instruction scheduling.
FunctionPass *llvm::createM68kISelDag(M68kTargetMachine &TM) {
- return new M68kDAGToDAGISel(TM);
+ return new M68kDAGToDAGISelLegacy(TM);
}
static bool doesDispFitFI(M68kISelAddressMode &AM) {
diff --git a/llvm/lib/Target/M68k/M68kTargetMachine.cpp b/llvm/lib/Target/M68k/M68kTargetMachine.cpp
index bbbcb1556ed55..b65de5e177b53 100644
--- a/llvm/lib/Target/M68k/M68kTargetMachine.cpp
+++ b/llvm/lib/Target/M68k/M68kTargetMachine.cpp
@@ -37,7 +37,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeM68kTarget() {
RegisterTargetMachine<M68kTargetMachine> X(getTheM68kTarget());
auto *PR = PassRegistry::getPassRegistry();
initializeGlobalISel(*PR);
- initializeM68kDAGToDAGISelPass(*PR);
+ initializeM68kDAGToDAGISelLegacyPass(*PR);
initializeM68kExpandPseudoPass(*PR);
initializeM68kGlobalBaseRegPass(*PR);
initializeM68kCollapseMOVEMPass(*PR);
>From 2563d4c2e82ffe98cb86741e889bdba0d45fd8e0 Mon Sep 17 00:00:00 2001
From: PaperChalice <liujunchang97 at outlook.com>
Date: Thu, 11 Apr 2024 19:56:41 +0800
Subject: [PATCH 13/26] Mips part
---
llvm/lib/Target/Mips/Mips.h | 2 +-
llvm/lib/Target/Mips/Mips16ISelDAGToDAG.cpp | 6 +++++-
llvm/lib/Target/Mips/Mips16ISelDAGToDAG.h | 5 +++++
llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp | 12 ++++++++----
llvm/lib/Target/Mips/MipsISelDAGToDAG.h | 13 ++++++++-----
llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp | 10 +++++++---
llvm/lib/Target/Mips/MipsSEISelDAGToDAG.h | 8 ++++++--
llvm/lib/Target/Mips/MipsTargetMachine.cpp | 2 +-
8 files changed, 41 insertions(+), 17 deletions(-)
diff --git a/llvm/lib/Target/Mips/Mips.h b/llvm/lib/Target/Mips/Mips.h
index f0cf039928c17..36a17334ae3b9 100644
--- a/llvm/lib/Target/Mips/Mips.h
+++ b/llvm/lib/Target/Mips/Mips.h
@@ -47,7 +47,7 @@ InstructionSelector *createMipsInstructionSelector(const MipsTargetMachine &,
void initializeMicroMipsSizeReducePass(PassRegistry &);
void initializeMipsBranchExpansionPass(PassRegistry &);
-void initializeMipsDAGToDAGISelPass(PassRegistry &);
+void initializeMipsDAGToDAGISelLegacyPass(PassRegistry &);
void initializeMipsDelaySlotFillerPass(PassRegistry &);
void initializeMipsMulMulBugFixPass(PassRegistry &);
void initializeMipsPostLegalizerCombinerPass(PassRegistry &);
diff --git a/llvm/lib/Target/Mips/Mips16ISelDAGToDAG.cpp b/llvm/lib/Target/Mips/Mips16ISelDAGToDAG.cpp
index 0be9b94187a2e..b8e6dcefe622a 100644
--- a/llvm/lib/Target/Mips/Mips16ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/Mips/Mips16ISelDAGToDAG.cpp
@@ -219,7 +219,11 @@ bool Mips16DAGToDAGISel::trySelect(SDNode *Node) {
return false;
}
+Mips16DAGToDAGISelLegacy::Mips16DAGToDAGISelLegacy(MipsTargetMachine &TM,
+ CodeGenOptLevel OL)
+ : MipsDAGToDAGISelLegacy(std::make_unique<Mips16DAGToDAGISel>(TM, OL)) {}
+
FunctionPass *llvm::createMips16ISelDag(MipsTargetMachine &TM,
CodeGenOptLevel OptLevel) {
- return new Mips16DAGToDAGISel(TM, OptLevel);
+ return new Mips16DAGToDAGISelLegacy(TM, OptLevel);
}
diff --git a/llvm/lib/Target/Mips/Mips16ISelDAGToDAG.h b/llvm/lib/Target/Mips/Mips16ISelDAGToDAG.h
index c6d3bde68806e..ec6e74568c561 100644
--- a/llvm/lib/Target/Mips/Mips16ISelDAGToDAG.h
+++ b/llvm/lib/Target/Mips/Mips16ISelDAGToDAG.h
@@ -47,6 +47,11 @@ class Mips16DAGToDAGISel : public MipsDAGToDAGISel {
void initMips16SPAliasReg(MachineFunction &MF);
};
+class Mips16DAGToDAGISelLegacy : public MipsDAGToDAGISelLegacy {
+public:
+ explicit Mips16DAGToDAGISelLegacy(MipsTargetMachine &TM, CodeGenOptLevel OL);
+};
+
FunctionPass *createMips16ISelDag(MipsTargetMachine &TM,
CodeGenOptLevel OptLevel);
}
diff --git a/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp b/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
index 01b41f3b21593..f6f32fde3b777 100644
--- a/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
+++ b/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
@@ -49,11 +49,11 @@ using namespace llvm;
// instructions for SelectionDAG operations.
//===----------------------------------------------------------------------===//
-void MipsDAGToDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
+void MipsDAGToDAGISelLegacy::getAnalysisUsage(AnalysisUsage &AU) const {
// There are multiple MipsDAGToDAGISel instances added to the pass pipeline.
// We need to preserve StackProtector for the next one.
AU.addPreserved<StackProtector>();
- SelectionDAGISel::getAnalysisUsage(AU);
+ SelectionDAGISelLegacy::getAnalysisUsage(AU);
}
bool MipsDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
@@ -344,6 +344,10 @@ bool MipsDAGToDAGISel::isUnneededShiftMask(SDNode *N,
return (Known.Zero | RHS).countr_one() >= ShAmtBits;
}
-char MipsDAGToDAGISel::ID = 0;
+char MipsDAGToDAGISelLegacy::ID = 0;
-INITIALIZE_PASS(MipsDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false)
+MipsDAGToDAGISelLegacy::MipsDAGToDAGISelLegacy(
+ std::unique_ptr<SelectionDAGISel> S)
+ : SelectionDAGISelLegacy(ID, std::move(S)) {}
+
+INITIALIZE_PASS(MipsDAGToDAGISelLegacy, DEBUG_TYPE, PASS_NAME, false, false)
diff --git a/llvm/lib/Target/Mips/MipsISelDAGToDAG.h b/llvm/lib/Target/Mips/MipsISelDAGToDAG.h
index 52207d0f62849..6135f96807854 100644
--- a/llvm/lib/Target/Mips/MipsISelDAGToDAG.h
+++ b/llvm/lib/Target/Mips/MipsISelDAGToDAG.h
@@ -30,17 +30,13 @@ namespace llvm {
class MipsDAGToDAGISel : public SelectionDAGISel {
public:
- static char ID;
-
MipsDAGToDAGISel() = delete;
explicit MipsDAGToDAGISel(MipsTargetMachine &TM, CodeGenOptLevel OL)
- : SelectionDAGISel(ID, TM, OL), Subtarget(nullptr) {}
+ : SelectionDAGISel(TM, OL), Subtarget(nullptr) {}
bool runOnMachineFunction(MachineFunction &MF) override;
- void getAnalysisUsage(AnalysisUsage &AU) const override;
-
protected:
SDNode *getGlobalBaseReg();
@@ -145,6 +141,13 @@ class MipsDAGToDAGISel : public SelectionDAGISel {
std::vector<SDValue> &OutOps) override;
bool isUnneededShiftMask(SDNode *N, unsigned ShAmtBits) const;
};
+
+class MipsDAGToDAGISelLegacy : public SelectionDAGISelLegacy {
+public:
+ static char ID;
+ MipsDAGToDAGISelLegacy(std::unique_ptr<SelectionDAGISel> S);
+ void getAnalysisUsage(AnalysisUsage &AU) const override;
+};
}
#endif
diff --git a/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp b/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
index ab39d1b661ef9..7ad300c6cccd4 100644
--- a/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
+++ b/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
@@ -44,9 +44,9 @@ bool MipsSEDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
return MipsDAGToDAGISel::runOnMachineFunction(MF);
}
-void MipsSEDAGToDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
+void MipsSEDAGToDAGISelLegacy::getAnalysisUsage(AnalysisUsage &AU) const {
AU.addRequired<DominatorTreeWrapperPass>();
- SelectionDAGISel::getAnalysisUsage(AU);
+ SelectionDAGISelLegacy::getAnalysisUsage(AU);
}
void MipsSEDAGToDAGISel::addDSPCtrlRegOperands(bool IsDef, MachineInstr &MI,
@@ -1439,7 +1439,11 @@ bool MipsSEDAGToDAGISel::SelectInlineAsmMemoryOperand(
return true;
}
+MipsSEDAGToDAGISelLegacy::MipsSEDAGToDAGISelLegacy(MipsTargetMachine &TM,
+ CodeGenOptLevel OL)
+ : MipsDAGToDAGISelLegacy(std::make_unique<MipsSEDAGToDAGISel>(TM, OL)) {}
+
FunctionPass *llvm::createMipsSEISelDag(MipsTargetMachine &TM,
CodeGenOptLevel OptLevel) {
- return new MipsSEDAGToDAGISel(TM, OptLevel);
+ return new MipsSEDAGToDAGISelLegacy(TM, OptLevel);
}
diff --git a/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.h b/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.h
index 96dc876cb753e..7b843b0e0b255 100644
--- a/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.h
+++ b/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.h
@@ -27,8 +27,6 @@ class MipsSEDAGToDAGISel : public MipsDAGToDAGISel {
bool runOnMachineFunction(MachineFunction &MF) override;
- void getAnalysisUsage(AnalysisUsage &AU) const override;
-
void addDSPCtrlRegOperands(bool IsDef, MachineInstr &MI,
MachineFunction &MF);
@@ -139,6 +137,12 @@ class MipsSEDAGToDAGISel : public MipsDAGToDAGISel {
std::vector<SDValue> &OutOps) override;
};
+class MipsSEDAGToDAGISelLegacy : public MipsDAGToDAGISelLegacy {
+public:
+ explicit MipsSEDAGToDAGISelLegacy(MipsTargetMachine &TM, CodeGenOptLevel OL);
+ void getAnalysisUsage(AnalysisUsage &AU) const override;
+};
+
FunctionPass *createMipsSEISelDag(MipsTargetMachine &TM,
CodeGenOptLevel OptLevel);
}
diff --git a/llvm/lib/Target/Mips/MipsTargetMachine.cpp b/llvm/lib/Target/Mips/MipsTargetMachine.cpp
index 4c4bf70e22c6c..9515e506c73e5 100644
--- a/llvm/lib/Target/Mips/MipsTargetMachine.cpp
+++ b/llvm/lib/Target/Mips/MipsTargetMachine.cpp
@@ -67,7 +67,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeMipsTarget() {
initializeMipsPreLegalizerCombinerPass(*PR);
initializeMipsPostLegalizerCombinerPass(*PR);
initializeMipsMulMulBugFixPass(*PR);
- initializeMipsDAGToDAGISelPass(*PR);
+ initializeMipsDAGToDAGISelLegacyPass(*PR);
}
static std::string computeDataLayout(const Triple &TT, StringRef CPU,
>From ef5087e4fa31f2a05aeca56f30cc24331b2db6ba Mon Sep 17 00:00:00 2001
From: PaperChalice <liujunchang97 at outlook.com>
Date: Thu, 11 Apr 2024 19:56:47 +0800
Subject: [PATCH 14/26] MSP430 part
---
llvm/lib/Target/MSP430/MSP430.h | 2 +-
llvm/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp | 18 ++++++++++++------
llvm/lib/Target/MSP430/MSP430TargetMachine.cpp | 2 +-
3 files changed, 14 insertions(+), 8 deletions(-)
diff --git a/llvm/lib/Target/MSP430/MSP430.h b/llvm/lib/Target/MSP430/MSP430.h
index 60685b6704ba2..019835908db81 100644
--- a/llvm/lib/Target/MSP430/MSP430.h
+++ b/llvm/lib/Target/MSP430/MSP430.h
@@ -43,7 +43,7 @@ FunctionPass *createMSP430ISelDag(MSP430TargetMachine &TM,
FunctionPass *createMSP430BranchSelectionPass();
-void initializeMSP430DAGToDAGISelPass(PassRegistry &);
+void initializeMSP430DAGToDAGISelLegacyPass(PassRegistry &);
} // namespace llvm
diff --git a/llvm/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp b/llvm/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp
index efb23b1a4e3f5..7be51d98d97d5 100644
--- a/llvm/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp
@@ -91,12 +91,10 @@ namespace {
namespace {
class MSP430DAGToDAGISel : public SelectionDAGISel {
public:
- static char ID;
-
MSP430DAGToDAGISel() = delete;
MSP430DAGToDAGISel(MSP430TargetMachine &TM, CodeGenOptLevel OptLevel)
- : SelectionDAGISel(ID, TM, OptLevel) {}
+ : SelectionDAGISel(TM, OptLevel) {}
private:
bool MatchAddress(SDValue N, MSP430ISelAddressMode &AM);
@@ -119,18 +117,26 @@ namespace {
bool SelectAddr(SDValue Addr, SDValue &Base, SDValue &Disp);
};
+
+ class MSP430DAGToDAGISelLegacy : public SelectionDAGISelLegacy {
+ public:
+ static char ID;
+ MSP430DAGToDAGISelLegacy(MSP430TargetMachine &TM, CodeGenOptLevel OptLevel)
+ : SelectionDAGISelLegacy(
+ ID, std::make_unique<MSP430DAGToDAGISel>(TM, OptLevel)) {}
+ };
} // end anonymous namespace
-char MSP430DAGToDAGISel::ID;
+char MSP430DAGToDAGISelLegacy::ID;
-INITIALIZE_PASS(MSP430DAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false)
+INITIALIZE_PASS(MSP430DAGToDAGISelLegacy, DEBUG_TYPE, PASS_NAME, false, false)
/// createMSP430ISelDag - This pass converts a legalized DAG into a
/// MSP430-specific DAG, ready for instruction scheduling.
///
FunctionPass *llvm::createMSP430ISelDag(MSP430TargetMachine &TM,
CodeGenOptLevel OptLevel) {
- return new MSP430DAGToDAGISel(TM, OptLevel);
+ return new MSP430DAGToDAGISelLegacy(TM, OptLevel);
}
/// MatchWrapper - Try to match MSP430ISD::Wrapper node into an addressing mode.
diff --git a/llvm/lib/Target/MSP430/MSP430TargetMachine.cpp b/llvm/lib/Target/MSP430/MSP430TargetMachine.cpp
index ed0fcf7110b78..f307c37651507 100644
--- a/llvm/lib/Target/MSP430/MSP430TargetMachine.cpp
+++ b/llvm/lib/Target/MSP430/MSP430TargetMachine.cpp
@@ -26,7 +26,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeMSP430Target() {
// Register the target.
RegisterTargetMachine<MSP430TargetMachine> X(getTheMSP430Target());
PassRegistry &PR = *PassRegistry::getPassRegistry();
- initializeMSP430DAGToDAGISelPass(PR);
+ initializeMSP430DAGToDAGISelLegacyPass(PR);
}
static Reloc::Model getEffectiveRelocModel(std::optional<Reloc::Model> RM) {
>From ada2394139c5892c267d8ca0c44162167ffaf7d9 Mon Sep 17 00:00:00 2001
From: PaperChalice <liujunchang97 at outlook.com>
Date: Thu, 11 Apr 2024 19:56:52 +0800
Subject: [PATCH 15/26] NVPTX part
---
llvm/lib/Target/NVPTX/NVPTX.h | 2 +-
llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp | 13 +++++++++----
llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h | 9 +++++++--
llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp | 2 +-
4 files changed, 18 insertions(+), 8 deletions(-)
diff --git a/llvm/lib/Target/NVPTX/NVPTX.h b/llvm/lib/Target/NVPTX/NVPTX.h
index 07ee34968b023..5eefab59a6ab5 100644
--- a/llvm/lib/Target/NVPTX/NVPTX.h
+++ b/llvm/lib/Target/NVPTX/NVPTX.h
@@ -194,7 +194,7 @@ enum PrmtMode {
};
}
}
-void initializeNVPTXDAGToDAGISelPass(PassRegistry &);
+void initializeNVPTXDAGToDAGISelLegacyPass(PassRegistry &);
} // namespace llvm
// Defines symbolic names for NVPTX registers. This defines a mapping from
diff --git a/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp b/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
index 2713b6859ff3b..1e1cbb15e33d4 100644
--- a/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
@@ -38,16 +38,21 @@ static cl::opt<bool>
/// NVPTX-specific DAG, ready for instruction scheduling.
FunctionPass *llvm::createNVPTXISelDag(NVPTXTargetMachine &TM,
llvm::CodeGenOptLevel OptLevel) {
- return new NVPTXDAGToDAGISel(TM, OptLevel);
+ return new NVPTXDAGToDAGISelLegacy(TM, OptLevel);
}
-char NVPTXDAGToDAGISel::ID = 0;
+NVPTXDAGToDAGISelLegacy::NVPTXDAGToDAGISelLegacy(NVPTXTargetMachine &tm,
+ CodeGenOptLevel OptLevel)
+ : SelectionDAGISelLegacy(
+ ID, std::make_unique<NVPTXDAGToDAGISel>(tm, OptLevel)) {}
-INITIALIZE_PASS(NVPTXDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false)
+char NVPTXDAGToDAGISelLegacy::ID = 0;
+
+INITIALIZE_PASS(NVPTXDAGToDAGISelLegacy, DEBUG_TYPE, PASS_NAME, false, false)
NVPTXDAGToDAGISel::NVPTXDAGToDAGISel(NVPTXTargetMachine &tm,
CodeGenOptLevel OptLevel)
- : SelectionDAGISel(ID, tm, OptLevel), TM(tm) {
+ : SelectionDAGISel(tm, OptLevel), TM(tm) {
doMulWide = (OptLevel > CodeGenOptLevel::None);
}
diff --git a/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h b/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h
index 7a7774744bc71..c5524351f2ff9 100644
--- a/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h
+++ b/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h
@@ -39,8 +39,6 @@ class LLVM_LIBRARY_VISIBILITY NVPTXDAGToDAGISel : public SelectionDAGISel {
bool doRsqrtOpt() const;
public:
- static char ID;
-
NVPTXDAGToDAGISel() = delete;
explicit NVPTXDAGToDAGISel(NVPTXTargetMachine &tm, CodeGenOptLevel OptLevel);
@@ -101,6 +99,13 @@ class LLVM_LIBRARY_VISIBILITY NVPTXDAGToDAGISel : public SelectionDAGISel {
static unsigned GetConvertOpcode(MVT DestTy, MVT SrcTy, LoadSDNode *N);
};
+
+class NVPTXDAGToDAGISelLegacy : public SelectionDAGISelLegacy {
+public:
+ static char ID;
+ explicit NVPTXDAGToDAGISelLegacy(NVPTXTargetMachine &tm,
+ CodeGenOptLevel OptLevel);
+};
} // end namespace llvm
#endif
diff --git a/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp b/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp
index 2a47c16a6bce5..4dc3cea4bd8e7 100644
--- a/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp
@@ -103,7 +103,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeNVPTXTarget() {
initializeNVPTXCtorDtorLoweringLegacyPass(PR);
initializeNVPTXLowerAggrCopiesPass(PR);
initializeNVPTXProxyRegErasurePass(PR);
- initializeNVPTXDAGToDAGISelPass(PR);
+ initializeNVPTXDAGToDAGISelLegacyPass(PR);
initializeNVPTXAAWrapperPassPass(PR);
initializeNVPTXExternalAAWrapperPass(PR);
}
>From 86ae5381ac113546a4039354ef302b77618fd663 Mon Sep 17 00:00:00 2001
From: PaperChalice <liujunchang97 at outlook.com>
Date: Thu, 11 Apr 2024 19:56:58 +0800
Subject: [PATCH 16/26] PowerPC part
---
llvm/lib/Target/PowerPC/PPC.h | 2 +-
llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp | 18 ++++++++++++------
llvm/lib/Target/PowerPC/PPCTargetMachine.cpp | 2 +-
3 files changed, 14 insertions(+), 8 deletions(-)
diff --git a/llvm/lib/Target/PowerPC/PPC.h b/llvm/lib/Target/PowerPC/PPC.h
index eb8886dcc9075..94a59d14601b2 100644
--- a/llvm/lib/Target/PowerPC/PPC.h
+++ b/llvm/lib/Target/PowerPC/PPC.h
@@ -78,7 +78,7 @@ class ModulePass;
void initializePPCMIPeepholePass(PassRegistry&);
void initializePPCExpandAtomicPseudoPass(PassRegistry &);
void initializePPCCTRLoopsPass(PassRegistry &);
- void initializePPCDAGToDAGISelPass(PassRegistry &);
+ void initializePPCDAGToDAGISelLegacyPass(PassRegistry &);
void initializePPCMergeStringPoolPass(PassRegistry &);
extern char &PPCVSXFMAMutateID;
diff --git a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
index 68621558e3fa0..cd23d1077f85f 100644
--- a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -147,12 +147,10 @@ namespace {
unsigned GlobalBaseReg = 0;
public:
- static char ID;
-
PPCDAGToDAGISel() = delete;
explicit PPCDAGToDAGISel(PPCTargetMachine &tm, CodeGenOptLevel OptLevel)
- : SelectionDAGISel(ID, tm, OptLevel), TM(tm) {}
+ : SelectionDAGISel(tm, OptLevel), TM(tm) {}
bool runOnMachineFunction(MachineFunction &MF) override {
// Make sure we re-emit a set of the global base reg if necessary
@@ -447,11 +445,19 @@ namespace {
void transferMemOperands(SDNode *N, SDNode *Result);
};
+ class PPCDAGToDAGISelLegacy : public SelectionDAGISelLegacy {
+ public:
+ static char ID;
+ explicit PPCDAGToDAGISelLegacy(PPCTargetMachine &tm,
+ CodeGenOptLevel OptLevel)
+ : SelectionDAGISelLegacy(
+ ID, std::make_unique<PPCDAGToDAGISel>(tm, OptLevel)) {}
+ };
} // end anonymous namespace
-char PPCDAGToDAGISel::ID = 0;
+char PPCDAGToDAGISelLegacy::ID = 0;
-INITIALIZE_PASS(PPCDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false)
+INITIALIZE_PASS(PPCDAGToDAGISelLegacy, DEBUG_TYPE, PASS_NAME, false, false)
/// getGlobalBaseReg - Output the instructions required to put the
/// base address to use for accessing globals into a register.
@@ -7920,5 +7926,5 @@ void PPCDAGToDAGISel::PeepholePPC64() {
///
FunctionPass *llvm::createPPCISelDag(PPCTargetMachine &TM,
CodeGenOptLevel OptLevel) {
- return new PPCDAGToDAGISel(TM, OptLevel);
+ return new PPCDAGToDAGISelLegacy(TM, OptLevel);
}
diff --git a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
index 714cf69827a1e..1ef891d1b677a 100644
--- a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
+++ b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
@@ -141,7 +141,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializePowerPCTarget() {
initializePPCExpandAtomicPseudoPass(PR);
initializeGlobalISel(PR);
initializePPCCTRLoopsPass(PR);
- initializePPCDAGToDAGISelPass(PR);
+ initializePPCDAGToDAGISelLegacyPass(PR);
initializePPCMergeStringPoolPass(PR);
}
>From 0cad39f2b04c70eee79fc9eb154b905f5829cf74 Mon Sep 17 00:00:00 2001
From: PaperChalice <liujunchang97 at outlook.com>
Date: Thu, 11 Apr 2024 19:57:03 +0800
Subject: [PATCH 17/26] RISCV part
---
llvm/lib/Target/RISCV/RISCV.h | 2 +-
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp | 11 ++++++++---
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h | 11 ++++++++---
llvm/lib/Target/RISCV/RISCVTargetMachine.cpp | 2 +-
4 files changed, 18 insertions(+), 8 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCV.h b/llvm/lib/Target/RISCV/RISCV.h
index 2b8688c5de61f..ee3e9df418a82 100644
--- a/llvm/lib/Target/RISCV/RISCV.h
+++ b/llvm/lib/Target/RISCV/RISCV.h
@@ -85,7 +85,7 @@ void initializeRISCVPushPopOptPass(PassRegistry &);
InstructionSelector *createRISCVInstructionSelector(const RISCVTargetMachine &,
RISCVSubtarget &,
RISCVRegisterBankInfo &);
-void initializeRISCVDAGToDAGISelPass(PassRegistry &);
+void initializeRISCVDAGToDAGISelLegacyPass(PassRegistry &);
FunctionPass *createRISCVPostLegalizerCombiner();
void initializeRISCVPostLegalizerCombinerPass(PassRegistry &);
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index d965dd4fc9a95..251401db3e281 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -3912,9 +3912,14 @@ bool RISCVDAGToDAGISel::doPeepholeNoRegPassThru() {
// for instruction scheduling.
FunctionPass *llvm::createRISCVISelDag(RISCVTargetMachine &TM,
CodeGenOptLevel OptLevel) {
- return new RISCVDAGToDAGISel(TM, OptLevel);
+ return new RISCVDAGToDAGISelLegacy(TM, OptLevel);
}
-char RISCVDAGToDAGISel::ID = 0;
+char RISCVDAGToDAGISelLegacy::ID = 0;
-INITIALIZE_PASS(RISCVDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false)
+RISCVDAGToDAGISelLegacy::RISCVDAGToDAGISelLegacy(RISCVTargetMachine &TM,
+ CodeGenOptLevel OptLevel)
+ : SelectionDAGISelLegacy(
+ ID, std::make_unique<RISCVDAGToDAGISel>(TM, OptLevel)) {}
+
+INITIALIZE_PASS(RISCVDAGToDAGISelLegacy, DEBUG_TYPE, PASS_NAME, false, false)
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
index ece04dd7f4b75..5d70245c0c557 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
@@ -25,13 +25,11 @@ class RISCVDAGToDAGISel : public SelectionDAGISel {
const RISCVSubtarget *Subtarget = nullptr;
public:
- static char ID;
-
RISCVDAGToDAGISel() = delete;
explicit RISCVDAGToDAGISel(RISCVTargetMachine &TargetMachine,
CodeGenOptLevel OptLevel)
- : SelectionDAGISel(ID, TargetMachine, OptLevel) {}
+ : SelectionDAGISel(TargetMachine, OptLevel) {}
bool runOnMachineFunction(MachineFunction &MF) override {
Subtarget = &MF.getSubtarget<RISCVSubtarget>();
@@ -196,6 +194,13 @@ class RISCVDAGToDAGISel : public SelectionDAGISel {
bool performCombineVMergeAndVOps(SDNode *N);
};
+class RISCVDAGToDAGISelLegacy : public SelectionDAGISelLegacy {
+public:
+ static char ID;
+ explicit RISCVDAGToDAGISelLegacy(RISCVTargetMachine &TargetMachine,
+ CodeGenOptLevel OptLevel);
+};
+
namespace RISCV {
struct VLSEGPseudo {
uint16_t NF : 4;
diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
index 5aab138dae408..6b68634d7ae5b 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
@@ -119,7 +119,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget() {
initializeRISCVCoalesceVSETVLIPass(*PR);
initializeRISCVInsertReadWriteCSRPass(*PR);
initializeRISCVInsertWriteVXRMPass(*PR);
- initializeRISCVDAGToDAGISelPass(*PR);
+ initializeRISCVDAGToDAGISelLegacyPass(*PR);
initializeRISCVMoveMergePass(*PR);
initializeRISCVPushPopOptPass(*PR);
}
>From 512520b87d14c9a66b24d0233ffb8b239dcd590c Mon Sep 17 00:00:00 2001
From: PaperChalice <liujunchang97 at outlook.com>
Date: Thu, 11 Apr 2024 19:57:08 +0800
Subject: [PATCH 18/26] Sparc part
---
llvm/lib/Target/Sparc/Sparc.h | 2 +-
llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp | 18 ++++++++++++------
llvm/lib/Target/Sparc/SparcTargetMachine.cpp | 2 +-
3 files changed, 14 insertions(+), 8 deletions(-)
diff --git a/llvm/lib/Target/Sparc/Sparc.h b/llvm/lib/Target/Sparc/Sparc.h
index fca7657871e86..33a803469603b 100644
--- a/llvm/lib/Target/Sparc/Sparc.h
+++ b/llvm/lib/Target/Sparc/Sparc.h
@@ -31,7 +31,7 @@ FunctionPass *createSparcDelaySlotFillerPass();
void LowerSparcMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
AsmPrinter &AP);
-void initializeSparcDAGToDAGISelPass(PassRegistry &);
+void initializeSparcDAGToDAGISelLegacyPass(PassRegistry &);
} // namespace llvm
namespace llvm {
diff --git a/llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp b/llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
index 3c9841d81b4f3..2531611948191 100644
--- a/llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
+++ b/llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
@@ -35,12 +35,11 @@ class SparcDAGToDAGISel : public SelectionDAGISel {
/// Subtarget - Keep a pointer to the Sparc Subtarget around so that we can
/// make the right decision when generating code for different targets.
const SparcSubtarget *Subtarget = nullptr;
-public:
- static char ID;
+public:
SparcDAGToDAGISel() = delete;
- explicit SparcDAGToDAGISel(SparcTargetMachine &tm) : SelectionDAGISel(ID, tm) {}
+ explicit SparcDAGToDAGISel(SparcTargetMachine &tm) : SelectionDAGISel(tm) {}
bool runOnMachineFunction(MachineFunction &MF) override {
Subtarget = &MF.getSubtarget<SparcSubtarget>();
@@ -66,11 +65,18 @@ class SparcDAGToDAGISel : public SelectionDAGISel {
SDNode* getGlobalBaseReg();
bool tryInlineAsm(SDNode *N);
};
+
+class SparcDAGToDAGISelLegacy : public SelectionDAGISelLegacy {
+public:
+ static char ID;
+ explicit SparcDAGToDAGISelLegacy(SparcTargetMachine &tm)
+ : SelectionDAGISelLegacy(ID, std::make_unique<SparcDAGToDAGISel>(tm)) {}
+};
} // end anonymous namespace
-char SparcDAGToDAGISel::ID = 0;
+char SparcDAGToDAGISelLegacy::ID = 0;
-INITIALIZE_PASS(SparcDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false)
+INITIALIZE_PASS(SparcDAGToDAGISelLegacy, DEBUG_TYPE, PASS_NAME, false, false)
SDNode* SparcDAGToDAGISel::getGlobalBaseReg() {
Register GlobalBaseReg = Subtarget->getInstrInfo()->getGlobalBaseReg(MF);
@@ -397,5 +403,5 @@ bool SparcDAGToDAGISel::SelectInlineAsmMemoryOperand(
/// SPARC-specific DAG, ready for instruction scheduling.
///
FunctionPass *llvm::createSparcISelDag(SparcTargetMachine &TM) {
- return new SparcDAGToDAGISel(TM);
+ return new SparcDAGToDAGISelLegacy(TM);
}
diff --git a/llvm/lib/Target/Sparc/SparcTargetMachine.cpp b/llvm/lib/Target/Sparc/SparcTargetMachine.cpp
index 20ddafb0e43d0..ea403230bea89 100644
--- a/llvm/lib/Target/Sparc/SparcTargetMachine.cpp
+++ b/llvm/lib/Target/Sparc/SparcTargetMachine.cpp
@@ -28,7 +28,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSparcTarget() {
RegisterTargetMachine<SparcelTargetMachine> Z(getTheSparcelTarget());
PassRegistry &PR = *PassRegistry::getPassRegistry();
- initializeSparcDAGToDAGISelPass(PR);
+ initializeSparcDAGToDAGISelLegacyPass(PR);
}
static cl::opt<bool>
>From a64964e6303c35fd73c0ec559cd28d9ed0fb6278 Mon Sep 17 00:00:00 2001
From: PaperChalice <liujunchang97 at outlook.com>
Date: Thu, 11 Apr 2024 19:57:14 +0800
Subject: [PATCH 19/26] SystemZ part
---
llvm/lib/Target/SystemZ/SystemZ.h | 2 +-
.../Target/SystemZ/SystemZISelDAGToDAG.cpp | 19 +++++++++++++------
.../Target/SystemZ/SystemZTargetMachine.cpp | 2 +-
3 files changed, 15 insertions(+), 8 deletions(-)
diff --git a/llvm/lib/Target/SystemZ/SystemZ.h b/llvm/lib/Target/SystemZ/SystemZ.h
index d7aa9e4e18cbb..8824954ce4481 100644
--- a/llvm/lib/Target/SystemZ/SystemZ.h
+++ b/llvm/lib/Target/SystemZ/SystemZ.h
@@ -199,7 +199,7 @@ FunctionPass *createSystemZPostRewritePass(SystemZTargetMachine &TM);
FunctionPass *createSystemZTDCPass();
void initializeSystemZCopyPhysRegsPass(PassRegistry &);
-void initializeSystemZDAGToDAGISelPass(PassRegistry &);
+void initializeSystemZDAGToDAGISelLegacyPass(PassRegistry &);
void initializeSystemZElimComparePass(PassRegistry &);
void initializeSystemZLDCleanupPass(PassRegistry &);
void initializeSystemZLongBranchPass(PassRegistry &);
diff --git a/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp b/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
index 1bf23c2e8e412..6c6a9b490d917 100644
--- a/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
@@ -356,12 +356,10 @@ class SystemZDAGToDAGISel : public SelectionDAGISel {
bool shouldSelectForReassoc(SDNode *N) const;
public:
- static char ID;
-
SystemZDAGToDAGISel() = delete;
SystemZDAGToDAGISel(SystemZTargetMachine &TM, CodeGenOptLevel OptLevel)
- : SelectionDAGISel(ID, TM, OptLevel) {}
+ : SelectionDAGISel(TM, OptLevel) {}
bool runOnMachineFunction(MachineFunction &MF) override {
const Function &F = MF.getFunction();
@@ -387,15 +385,24 @@ class SystemZDAGToDAGISel : public SelectionDAGISel {
// Include the pieces autogenerated from the target description.
#include "SystemZGenDAGISel.inc"
};
+
+class SystemZDAGToDAGISelLegacy : public SelectionDAGISelLegacy {
+public:
+ static char ID;
+ explicit SystemZDAGToDAGISelLegacy(SystemZTargetMachine &TM,
+ CodeGenOptLevel OptLevel)
+ : SelectionDAGISelLegacy(
+ ID, std::make_unique<SystemZDAGToDAGISel>(TM, OptLevel)) {}
+};
} // end anonymous namespace
-char SystemZDAGToDAGISel::ID = 0;
+char SystemZDAGToDAGISelLegacy::ID = 0;
-INITIALIZE_PASS(SystemZDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false)
+INITIALIZE_PASS(SystemZDAGToDAGISelLegacy, DEBUG_TYPE, PASS_NAME, false, false)
FunctionPass *llvm::createSystemZISelDag(SystemZTargetMachine &TM,
CodeGenOptLevel OptLevel) {
- return new SystemZDAGToDAGISel(TM, OptLevel);
+ return new SystemZDAGToDAGISelLegacy(TM, OptLevel);
}
// Return true if Val should be selected as a displacement for an address
diff --git a/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp b/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp
index dced64d6b21ac..6f76839724ee9 100644
--- a/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp
@@ -47,7 +47,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSystemZTarget() {
initializeSystemZShortenInstPass(PR);
initializeSystemZPostRewritePass(PR);
initializeSystemZTDCPassPass(PR);
- initializeSystemZDAGToDAGISelPass(PR);
+ initializeSystemZDAGToDAGISelLegacyPass(PR);
}
static std::string computeDataLayout(const Triple &TT) {
>From 6527c9793db0d3fa3040ad52f2b53b271d85317d Mon Sep 17 00:00:00 2001
From: PaperChalice <liujunchang97 at outlook.com>
Date: Thu, 11 Apr 2024 19:57:19 +0800
Subject: [PATCH 20/26] VE part
---
llvm/lib/Target/VE/VE.h | 2 +-
llvm/lib/Target/VE/VEISelDAGToDAG.cpp | 17 +++++++++++------
llvm/lib/Target/VE/VETargetMachine.cpp | 2 +-
3 files changed, 13 insertions(+), 8 deletions(-)
diff --git a/llvm/lib/Target/VE/VE.h b/llvm/lib/Target/VE/VE.h
index 6f0243010ba08..ee76c5121d362 100644
--- a/llvm/lib/Target/VE/VE.h
+++ b/llvm/lib/Target/VE/VE.h
@@ -29,7 +29,7 @@ class VETargetMachine;
FunctionPass *createVEISelDag(VETargetMachine &TM);
FunctionPass *createLVLGenPass();
-void initializeVEDAGToDAGISelPass(PassRegistry &);
+void initializeVEDAGToDAGISelLegacyPass(PassRegistry &);
void LowerVEMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
AsmPrinter &AP);
diff --git a/llvm/lib/Target/VE/VEISelDAGToDAG.cpp b/llvm/lib/Target/VE/VEISelDAGToDAG.cpp
index 87646bc1a12ff..680bd12fb4b62 100644
--- a/llvm/lib/Target/VE/VEISelDAGToDAG.cpp
+++ b/llvm/lib/Target/VE/VEISelDAGToDAG.cpp
@@ -34,11 +34,9 @@ class VEDAGToDAGISel : public SelectionDAGISel {
const VESubtarget *Subtarget;
public:
- static char ID;
-
VEDAGToDAGISel() = delete;
- explicit VEDAGToDAGISel(VETargetMachine &tm) : SelectionDAGISel(ID, tm) {}
+ explicit VEDAGToDAGISel(VETargetMachine &tm) : SelectionDAGISel(tm) {}
bool runOnMachineFunction(MachineFunction &MF) override {
Subtarget = &MF.getSubtarget<VESubtarget>();
@@ -70,11 +68,18 @@ class VEDAGToDAGISel : public SelectionDAGISel {
bool matchADDRrr(SDValue N, SDValue &Base, SDValue &Index);
bool matchADDRri(SDValue N, SDValue &Base, SDValue &Offset);
};
+
+class VEDAGToDAGISelLegacy : public SelectionDAGISelLegacy {
+public:
+ static char ID;
+ explicit VEDAGToDAGISelLegacy(VETargetMachine &tm)
+ : SelectionDAGISelLegacy(ID, std::make_unique<VEDAGToDAGISel>(tm)) {}
+};
} // end anonymous namespace
-char VEDAGToDAGISel::ID = 0;
+char VEDAGToDAGISelLegacy::ID = 0;
-INITIALIZE_PASS(VEDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false)
+INITIALIZE_PASS(VEDAGToDAGISelLegacy, DEBUG_TYPE, PASS_NAME, false, false)
bool VEDAGToDAGISel::selectADDRrri(SDValue Addr, SDValue &Base, SDValue &Index,
SDValue &Offset) {
@@ -336,5 +341,5 @@ SDNode *VEDAGToDAGISel::getGlobalBaseReg() {
/// VE-specific DAG, ready for instruction scheduling.
///
FunctionPass *llvm::createVEISelDag(VETargetMachine &TM) {
- return new VEDAGToDAGISel(TM);
+ return new VEDAGToDAGISelLegacy(TM);
}
diff --git a/llvm/lib/Target/VE/VETargetMachine.cpp b/llvm/lib/Target/VE/VETargetMachine.cpp
index 6f4e137e4d2f1..383667bf79e1b 100644
--- a/llvm/lib/Target/VE/VETargetMachine.cpp
+++ b/llvm/lib/Target/VE/VETargetMachine.cpp
@@ -30,7 +30,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeVETarget() {
RegisterTargetMachine<VETargetMachine> X(getTheVETarget());
PassRegistry &PR = *PassRegistry::getPassRegistry();
- initializeVEDAGToDAGISelPass(PR);
+ initializeVEDAGToDAGISelLegacyPass(PR);
}
static std::string computeDataLayout(const Triple &T) {
>From 724b12be787784b6aa6408f75bbeb6b78f0b0f77 Mon Sep 17 00:00:00 2001
From: PaperChalice <liujunchang97 at outlook.com>
Date: Thu, 11 Apr 2024 19:57:27 +0800
Subject: [PATCH 21/26] WebAssembly part
---
llvm/lib/Target/WebAssembly/WebAssembly.h | 2 +-
.../WebAssembly/WebAssemblyISelDAGToDAG.cpp | 20 +++++++++++++------
.../WebAssembly/WebAssemblyTargetMachine.cpp | 2 +-
3 files changed, 16 insertions(+), 8 deletions(-)
diff --git a/llvm/lib/Target/WebAssembly/WebAssembly.h b/llvm/lib/Target/WebAssembly/WebAssembly.h
index 7fc8546248f16..8f142fa0928ca 100644
--- a/llvm/lib/Target/WebAssembly/WebAssembly.h
+++ b/llvm/lib/Target/WebAssembly/WebAssembly.h
@@ -67,7 +67,7 @@ void initializeWebAssemblyArgumentMovePass(PassRegistry &);
void initializeWebAssemblyCleanCodeAfterTrapPass(PassRegistry &);
void initializeWebAssemblyCFGSortPass(PassRegistry &);
void initializeWebAssemblyCFGStackifyPass(PassRegistry &);
-void initializeWebAssemblyDAGToDAGISelPass(PassRegistry &);
+void initializeWebAssemblyDAGToDAGISelLegacyPass(PassRegistry &);
void initializeWebAssemblyDebugFixupPass(PassRegistry &);
void initializeWebAssemblyExceptionInfoPass(PassRegistry &);
void initializeWebAssemblyExplicitLocalsPass(PassRegistry &);
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp
index 8833aee02a6a9..0f06f54f219f9 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp
@@ -42,13 +42,11 @@ class WebAssemblyDAGToDAGISel final : public SelectionDAGISel {
const WebAssemblySubtarget *Subtarget;
public:
- static char ID;
-
WebAssemblyDAGToDAGISel() = delete;
WebAssemblyDAGToDAGISel(WebAssemblyTargetMachine &TM,
CodeGenOptLevel OptLevel)
- : SelectionDAGISel(ID, TM, OptLevel), Subtarget(nullptr) {}
+ : SelectionDAGISel(TM, OptLevel), Subtarget(nullptr) {}
bool runOnMachineFunction(MachineFunction &MF) override {
LLVM_DEBUG(dbgs() << "********** ISelDAGToDAG **********\n"
@@ -82,11 +80,21 @@ class WebAssemblyDAGToDAGISel final : public SelectionDAGISel {
bool SelectAddrAddOperands(MVT OffsetType, SDValue N, SDValue &Offset,
SDValue &Addr);
};
+
+class WebAssemblyDAGToDAGISelLegacy : public SelectionDAGISelLegacy {
+public:
+ static char ID;
+ explicit WebAssemblyDAGToDAGISelLegacy(WebAssemblyTargetMachine &TM,
+ CodeGenOptLevel OptLevel)
+ : SelectionDAGISelLegacy(
+ ID, std::make_unique<WebAssemblyDAGToDAGISel>(TM, OptLevel)) {}
+};
} // end anonymous namespace
-char WebAssemblyDAGToDAGISel::ID;
+char WebAssemblyDAGToDAGISelLegacy::ID;
-INITIALIZE_PASS(WebAssemblyDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false)
+INITIALIZE_PASS(WebAssemblyDAGToDAGISelLegacy, DEBUG_TYPE, PASS_NAME, false,
+ false)
void WebAssemblyDAGToDAGISel::PreprocessISelDAG() {
// Stack objects that should be allocated to locals are hoisted to WebAssembly
@@ -409,5 +417,5 @@ bool WebAssemblyDAGToDAGISel::SelectAddrOperands64(SDValue Op, SDValue &Offset,
/// for instruction scheduling.
FunctionPass *llvm::createWebAssemblyISelDag(WebAssemblyTargetMachine &TM,
CodeGenOptLevel OptLevel) {
- return new WebAssemblyDAGToDAGISel(TM, OptLevel);
+ return new WebAssemblyDAGToDAGISelLegacy(TM, OptLevel);
}
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
index de342e8965736..0465a2a6b0753 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
@@ -90,7 +90,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeWebAssemblyTarget() {
initializeWebAssemblyMCLowerPrePassPass(PR);
initializeWebAssemblyLowerRefTypesIntPtrConvPass(PR);
initializeWebAssemblyFixBrTableDefaultsPass(PR);
- initializeWebAssemblyDAGToDAGISelPass(PR);
+ initializeWebAssemblyDAGToDAGISelLegacyPass(PR);
}
//===----------------------------------------------------------------------===//
>From df82570f7ef12404115f639ee22eea1a99065635 Mon Sep 17 00:00:00 2001
From: PaperChalice <liujunchang97 at outlook.com>
Date: Thu, 11 Apr 2024 19:57:34 +0800
Subject: [PATCH 22/26] X86 part
---
llvm/lib/Target/X86/X86.h | 2 +-
llvm/lib/Target/X86/X86CodeGenPassBuilder.cpp | 11 +++++++-
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp | 28 +++++++++++++------
llvm/lib/Target/X86/X86ISelDAGToDAG.h | 25 +++++++++++++++++
llvm/lib/Target/X86/X86PassRegistry.def | 19 +++++++++++++
llvm/lib/Target/X86/X86TargetMachine.cpp | 2 +-
llvm/lib/Target/X86/X86TargetMachine.h | 3 ++
llvm/test/CodeGen/X86/apx/no-rex2-general.ll | 2 ++
.../CodeGen/X86/apx/no-rex2-pseudo-amx.ll | 1 +
.../CodeGen/X86/apx/no-rex2-pseudo-x87.ll | 1 +
llvm/test/CodeGen/X86/apx/no-rex2-special.ll | 1 +
11 files changed, 83 insertions(+), 12 deletions(-)
create mode 100644 llvm/lib/Target/X86/X86ISelDAGToDAG.h
create mode 100644 llvm/lib/Target/X86/X86PassRegistry.def
diff --git a/llvm/lib/Target/X86/X86.h b/llvm/lib/Target/X86/X86.h
index 21623a805f556..fdb9e4cad5e89 100644
--- a/llvm/lib/Target/X86/X86.h
+++ b/llvm/lib/Target/X86/X86.h
@@ -179,7 +179,7 @@ void initializeX86AvoidSFBPassPass(PassRegistry &);
void initializeX86AvoidTrailingCallPassPass(PassRegistry &);
void initializeX86CallFrameOptimizationPass(PassRegistry &);
void initializeX86CmovConverterPassPass(PassRegistry &);
-void initializeX86DAGToDAGISelPass(PassRegistry &);
+void initializeX86DAGToDAGISelLegacyPass(PassRegistry &);
void initializeX86DomainReassignmentPass(PassRegistry &);
void initializeX86ExecutionDomainFixPass(PassRegistry &);
void initializeX86ExpandPseudoPass(PassRegistry &);
diff --git a/llvm/lib/Target/X86/X86CodeGenPassBuilder.cpp b/llvm/lib/Target/X86/X86CodeGenPassBuilder.cpp
index 7c1fb0b99f413..cc5937d0bda6e 100644
--- a/llvm/lib/Target/X86/X86CodeGenPassBuilder.cpp
+++ b/llvm/lib/Target/X86/X86CodeGenPassBuilder.cpp
@@ -10,10 +10,12 @@
/// TODO: Port CodeGen passes to new pass manager.
//===----------------------------------------------------------------------===//
+#include "X86ISelDAGToDAG.h"
#include "X86TargetMachine.h"
#include "llvm/MC/MCStreamer.h"
#include "llvm/Passes/CodeGenPassBuilder.h"
+#include "llvm/Passes/PassBuilder.h"
using namespace llvm;
@@ -40,13 +42,20 @@ void X86CodeGenPassBuilder::addAsmPrinter(AddMachinePass &addPass,
// TODO: Add AsmPrinter.
}
-Error X86CodeGenPassBuilder::addInstSelector(AddMachinePass &) const {
+Error X86CodeGenPassBuilder::addInstSelector(AddMachinePass &addPass) const {
// TODO: Add instruction selector.
+ addPass(X86ISelDAGToDAGPass(static_cast<X86TargetMachine &>(TM)));
return Error::success();
}
} // namespace
+void X86TargetMachine::registerPassBuilderCallbacks(
+ PassBuilder &PB, bool PopulateClassToPassNames) {
+#define GET_PASS_REGISTRY "X86PassRegistry.def"
+#include "llvm/Passes/TargetPassRegistry.inc"
+}
+
Error X86TargetMachine::buildCodeGenPipeline(
ModulePassManager &MPM, raw_pwrite_stream &Out, raw_pwrite_stream *DwoOut,
CodeGenFileType FileType, const CGPassBuilderOption &Opt,
diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
index 7f76324fa5705..6bcc806fff524 100644
--- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -11,6 +11,7 @@
//
//===----------------------------------------------------------------------===//
+#include "X86ISelDAGToDAG.h"
#include "X86.h"
#include "X86MachineFunctionInfo.h"
#include "X86RegisterInfo.h"
@@ -169,12 +170,10 @@ namespace {
bool IndirectTlsSegRefs;
public:
- static char ID;
-
X86DAGToDAGISel() = delete;
explicit X86DAGToDAGISel(X86TargetMachine &tm, CodeGenOptLevel OptLevel)
- : SelectionDAGISel(ID, tm, OptLevel), Subtarget(nullptr),
+ : SelectionDAGISel(tm, OptLevel), Subtarget(nullptr),
OptForMinSize(false), IndirectTlsSegRefs(false) {}
bool runOnMachineFunction(MachineFunction &MF) override {
@@ -187,9 +186,7 @@ namespace {
OptForMinSize = MF.getFunction().hasMinSize();
assert((!OptForMinSize || MF.getFunction().hasOptSize()) &&
"OptForMinSize implies OptForSize");
-
- SelectionDAGISel::runOnMachineFunction(MF);
- return true;
+ return SelectionDAGISel::runOnMachineFunction(MF);
}
void emitFunctionEntryCode() override;
@@ -577,11 +574,20 @@ namespace {
bool hasNoSignFlagUses(SDValue Flags) const;
bool hasNoCarryFlagUses(SDValue Flags) const;
};
+
+ class X86DAGToDAGISelLegacy : public SelectionDAGISelLegacy {
+ public:
+ static char ID;
+ explicit X86DAGToDAGISelLegacy(X86TargetMachine &tm,
+ CodeGenOptLevel OptLevel)
+ : SelectionDAGISelLegacy(
+ ID, std::make_unique<X86DAGToDAGISel>(tm, OptLevel)) {}
+ };
}
-char X86DAGToDAGISel::ID = 0;
+char X86DAGToDAGISelLegacy::ID = 0;
-INITIALIZE_PASS(X86DAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false)
+INITIALIZE_PASS(X86DAGToDAGISelLegacy, DEBUG_TYPE, PASS_NAME, false, false)
// Returns true if this masked compare can be implemented legally with this
// type.
@@ -6574,9 +6580,13 @@ bool X86DAGToDAGISel::SelectInlineAsmMemoryOperand(
return false;
}
+X86ISelDAGToDAGPass::X86ISelDAGToDAGPass(X86TargetMachine &TM)
+ : SelectionDAGISelPass(
+ std::make_unique<X86DAGToDAGISel>(TM, TM.getOptLevel())) {}
+
/// This pass converts a legalized DAG into a X86-specific DAG,
/// ready for instruction scheduling.
FunctionPass *llvm::createX86ISelDag(X86TargetMachine &TM,
CodeGenOptLevel OptLevel) {
- return new X86DAGToDAGISel(TM, OptLevel);
+ return new X86DAGToDAGISelLegacy(TM, OptLevel);
}
diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.h b/llvm/lib/Target/X86/X86ISelDAGToDAG.h
new file mode 100644
index 0000000000000..1f30c25b502fc
--- /dev/null
+++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.h
@@ -0,0 +1,25 @@
+//===-- X86ISelDAGToDAG.h ---------------------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_X86_X86ISELDAGTODAG_H
+#define LLVM_LIB_TARGET_X86_X86ISELDAGTODAG_H
+
+#include "llvm/CodeGen/SelectionDAGISel.h"
+
+namespace llvm {
+
+class X86TargetMachine;
+
+class X86ISelDAGToDAGPass : public SelectionDAGISelPass {
+public:
+ X86ISelDAGToDAGPass(X86TargetMachine &TM);
+};
+
+} // namespace llvm
+
+#endif // LLVM_LIB_TARGET_X86_X86ISELDAGTODAG_H
diff --git a/llvm/lib/Target/X86/X86PassRegistry.def b/llvm/lib/Target/X86/X86PassRegistry.def
new file mode 100644
index 0000000000000..620526ffc1ab6
--- /dev/null
+++ b/llvm/lib/Target/X86/X86PassRegistry.def
@@ -0,0 +1,19 @@
+//===- X86PassRegistry.def - Registry of X86 specific passes ----*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file is used as the registry of passes that are part of the X86 backend.
+//
+//===----------------------------------------------------------------------===//
+
+// NOTE: NO INCLUDE GUARD DESIRED!
+
+#ifndef MACHINE_FUNCTION_PASS
+#define MACHINE_FUNCTION_PASS(NAME, CREATE_PASS)
+#endif
+MACHINE_FUNCTION_PASS("x86-isel", X86ISelDAGToDAGPass(*this))
+#undef MACHINE_FUNCTION_PASS
diff --git a/llvm/lib/Target/X86/X86TargetMachine.cpp b/llvm/lib/Target/X86/X86TargetMachine.cpp
index 86b456019c4e5..f771f610d0e55 100644
--- a/llvm/lib/Target/X86/X86TargetMachine.cpp
+++ b/llvm/lib/Target/X86/X86TargetMachine.cpp
@@ -100,7 +100,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeX86Target() {
initializeX86PartialReductionPass(PR);
initializePseudoProbeInserterPass(PR);
initializeX86ReturnThunksPass(PR);
- initializeX86DAGToDAGISelPass(PR);
+ initializeX86DAGToDAGISelLegacyPass(PR);
initializeX86ArgumentStackSlotPassPass(PR);
initializeX86FixupInstTuningPassPass(PR);
initializeX86FixupVectorConstantsPassPass(PR);
diff --git a/llvm/lib/Target/X86/X86TargetMachine.h b/llvm/lib/Target/X86/X86TargetMachine.h
index 4e7ded16729d0..4a5f20fcc0172 100644
--- a/llvm/lib/Target/X86/X86TargetMachine.h
+++ b/llvm/lib/Target/X86/X86TargetMachine.h
@@ -58,6 +58,9 @@ class X86TargetMachine final : public LLVMTargetMachine {
createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F,
const TargetSubtargetInfo *STI) const override;
+ void registerPassBuilderCallbacks(PassBuilder &PB,
+ bool PopulateClassToPassNames) override;
+
Error buildCodeGenPipeline(ModulePassManager &, raw_pwrite_stream &,
raw_pwrite_stream *, CodeGenFileType,
const CGPassBuilderOption &,
diff --git a/llvm/test/CodeGen/X86/apx/no-rex2-general.ll b/llvm/test/CodeGen/X86/apx/no-rex2-general.ll
index 1f92883f41708..805fc7ccaab76 100644
--- a/llvm/test/CodeGen/X86/apx/no-rex2-general.ll
+++ b/llvm/test/CodeGen/X86/apx/no-rex2-general.ll
@@ -1,6 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown -stop-after=x86-isel -mattr=+sse2,+ssse3,+egpr | FileCheck %s --check-prefix=SSE
; RUN: llc < %s -mtriple=x86_64-unknown -stop-after=x86-isel -mattr=+sse2,+ssse3,+egpr,+avx | FileCheck %s --check-prefix=AVX
+; RUN: llc < %s -enable-new-pm -mtriple=x86_64-unknown -stop-after=x86-isel -mattr=+sse2,+ssse3,+egpr | FileCheck %s --check-prefix=SSE
+; RUN: llc < %s -enable-new-pm -mtriple=x86_64-unknown -stop-after=x86-isel -mattr=+sse2,+ssse3,+egpr,+avx | FileCheck %s --check-prefix=AVX
define i32 @map0(ptr nocapture noundef readonly %a, i64 noundef %b) {
; SSE-LABEL: name: map0
diff --git a/llvm/test/CodeGen/X86/apx/no-rex2-pseudo-amx.ll b/llvm/test/CodeGen/X86/apx/no-rex2-pseudo-amx.ll
index e082becbc441d..5fa4cb4c8826b 100644
--- a/llvm/test/CodeGen/X86/apx/no-rex2-pseudo-amx.ll
+++ b/llvm/test/CodeGen/X86/apx/no-rex2-pseudo-amx.ll
@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown -stop-after=x86-isel -mattr=+amx-tile,+egpr | FileCheck %s
+; RUN: llc < %s -enable-new-pm -mtriple=x86_64-unknown -stop-after=x86-isel -mattr=+amx-tile,+egpr | FileCheck %s
define dso_local void @amx(ptr noundef %data) {
; CHECK-LABEL: name: amx
diff --git a/llvm/test/CodeGen/X86/apx/no-rex2-pseudo-x87.ll b/llvm/test/CodeGen/X86/apx/no-rex2-pseudo-x87.ll
index 10ec184516e7e..a9ca591a156c2 100644
--- a/llvm/test/CodeGen/X86/apx/no-rex2-pseudo-x87.ll
+++ b/llvm/test/CodeGen/X86/apx/no-rex2-pseudo-x87.ll
@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown -stop-after=x86-isel -mattr=-sse,+egpr | FileCheck %s
+; RUN: llc < %s -enable-new-pm -mtriple=x86_64-unknown -stop-after=x86-isel -mattr=-sse,+egpr | FileCheck %s
define void @x87(ptr %0, ptr %1) {
; CHECK-LABEL: name: x87
diff --git a/llvm/test/CodeGen/X86/apx/no-rex2-special.ll b/llvm/test/CodeGen/X86/apx/no-rex2-special.ll
index b277949697417..86534427a9eae 100644
--- a/llvm/test/CodeGen/X86/apx/no-rex2-special.ll
+++ b/llvm/test/CodeGen/X86/apx/no-rex2-special.ll
@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown -stop-after=x86-isel -mattr=+xsave,+egpr | FileCheck %s
+; RUN: llc < %s -enable-new-pm -mtriple=x86_64-unknown -stop-after=x86-isel -mattr=+xsave,+egpr | FileCheck %s
define void @test_xsave(ptr %ptr, i32 %hi, i32 %lo) {
; CHECK-LABEL: name: test_xsave
>From 42b4d9494f5a670f3563606b56041c5ef06a36f2 Mon Sep 17 00:00:00 2001
From: PaperChalice <liujunchang97 at outlook.com>
Date: Thu, 11 Apr 2024 19:57:41 +0800
Subject: [PATCH 23/26] XCore part
---
llvm/lib/Target/XCore/XCore.h | 2 +-
llvm/lib/Target/XCore/XCoreISelDAGToDAG.cpp | 19 +++++++++++++------
llvm/lib/Target/XCore/XCoreTargetMachine.cpp | 2 +-
3 files changed, 15 insertions(+), 8 deletions(-)
diff --git a/llvm/lib/Target/XCore/XCore.h b/llvm/lib/Target/XCore/XCore.h
index f019fa49f185e..ad50f05a89d86 100644
--- a/llvm/lib/Target/XCore/XCore.h
+++ b/llvm/lib/Target/XCore/XCore.h
@@ -31,7 +31,7 @@ namespace llvm {
FunctionPass *createXCoreISelDag(XCoreTargetMachine &TM,
CodeGenOptLevel OptLevel);
ModulePass *createXCoreLowerThreadLocalPass();
- void initializeXCoreDAGToDAGISelPass(PassRegistry &);
+ void initializeXCoreDAGToDAGISelLegacyPass(PassRegistry &);
} // end namespace llvm;
diff --git a/llvm/lib/Target/XCore/XCoreISelDAGToDAG.cpp b/llvm/lib/Target/XCore/XCoreISelDAGToDAG.cpp
index 1535eb622da68..dcbf1145a5cc2 100644
--- a/llvm/lib/Target/XCore/XCoreISelDAGToDAG.cpp
+++ b/llvm/lib/Target/XCore/XCoreISelDAGToDAG.cpp
@@ -41,12 +41,10 @@ namespace {
class XCoreDAGToDAGISel : public SelectionDAGISel {
public:
- static char ID;
-
XCoreDAGToDAGISel() = delete;
XCoreDAGToDAGISel(XCoreTargetMachine &TM, CodeGenOptLevel OptLevel)
- : SelectionDAGISel(ID, TM, OptLevel) {}
+ : SelectionDAGISel(TM, OptLevel) {}
void Select(SDNode *N) override;
bool tryBRIND(SDNode *N);
@@ -78,18 +76,27 @@ namespace {
// Include the pieces autogenerated from the target description.
#include "XCoreGenDAGISel.inc"
};
+
+ class XCoreDAGToDAGISelLegacy : public SelectionDAGISelLegacy {
+ public:
+ static char ID;
+ explicit XCoreDAGToDAGISelLegacy(XCoreTargetMachine &TM,
+ CodeGenOptLevel OptLevel)
+ : SelectionDAGISelLegacy(
+ ID, std::make_unique<XCoreDAGToDAGISel>(TM, OptLevel)) {}
+ };
} // end anonymous namespace
-char XCoreDAGToDAGISel::ID = 0;
+char XCoreDAGToDAGISelLegacy::ID = 0;
-INITIALIZE_PASS(XCoreDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false)
+INITIALIZE_PASS(XCoreDAGToDAGISelLegacy, DEBUG_TYPE, PASS_NAME, false, false)
/// createXCoreISelDag - This pass converts a legalized DAG into a
/// XCore-specific DAG, ready for instruction scheduling.
///
FunctionPass *llvm::createXCoreISelDag(XCoreTargetMachine &TM,
CodeGenOptLevel OptLevel) {
- return new XCoreDAGToDAGISel(TM, OptLevel);
+ return new XCoreDAGToDAGISelLegacy(TM, OptLevel);
}
bool XCoreDAGToDAGISel::SelectADDRspii(SDValue Addr, SDValue &Base,
diff --git a/llvm/lib/Target/XCore/XCoreTargetMachine.cpp b/llvm/lib/Target/XCore/XCoreTargetMachine.cpp
index 374e91d01bdac..bb5beefbb65e1 100644
--- a/llvm/lib/Target/XCore/XCoreTargetMachine.cpp
+++ b/llvm/lib/Target/XCore/XCoreTargetMachine.cpp
@@ -107,7 +107,7 @@ void XCorePassConfig::addPreEmitPass() {
extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeXCoreTarget() {
RegisterTargetMachine<XCoreTargetMachine> X(getTheXCoreTarget());
PassRegistry &PR = *PassRegistry::getPassRegistry();
- initializeXCoreDAGToDAGISelPass(PR);
+ initializeXCoreDAGToDAGISelLegacyPass(PR);
}
TargetTransformInfo
>From b03cffa184ba446ff1ea9ff3a0bbcca37f6e6145 Mon Sep 17 00:00:00 2001
From: PaperChalice <liujunchang97 at outlook.com>
Date: Thu, 11 Apr 2024 20:00:10 +0800
Subject: [PATCH 24/26] Xtensa part
---
llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp | 25 ++++++++++++-------
1 file changed, 16 insertions(+), 9 deletions(-)
diff --git a/llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp b/llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp
index 5ebedefafc165..145f285036358 100644
--- a/llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp
+++ b/llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp
@@ -28,14 +28,8 @@ namespace {
class XtensaDAGToDAGISel : public SelectionDAGISel {
public:
- static char ID;
-
XtensaDAGToDAGISel(XtensaTargetMachine &TM, CodeGenOptLevel OptLevel)
- : SelectionDAGISel(ID, TM, OptLevel) {}
-
- StringRef getPassName() const override {
- return "Xtensa DAG->DAG Pattern Instruction Selection";
- }
+ : SelectionDAGISel(TM, OptLevel) {}
void Select(SDNode *Node) override;
@@ -107,13 +101,26 @@ class XtensaDAGToDAGISel : public SelectionDAGISel {
// Include the pieces autogenerated from the target description.
#include "XtensaGenDAGISel.inc"
}; // namespace
+
+class XtensaDAGToDAGISelLegacy : public SelectionDAGISelLegacy {
+public:
+ static char ID;
+
+ XtensaDAGToDAGISelLegacy(XtensaTargetMachine &TM, CodeGenOptLevel OptLevel)
+ : SelectionDAGISelLegacy(
+ ID, std::make_unique<XtensaDAGToDAGISel>(TM, OptLevel)) {}
+
+ StringRef getPassName() const override {
+ return "Xtensa DAG->DAG Pattern Instruction Selection";
+ }
+};
} // end anonymous namespace
-char XtensaDAGToDAGISel::ID = 0;
+char XtensaDAGToDAGISelLegacy::ID = 0;
FunctionPass *llvm::createXtensaISelDag(XtensaTargetMachine &TM,
CodeGenOptLevel OptLevel) {
- return new XtensaDAGToDAGISel(TM, OptLevel);
+ return new XtensaDAGToDAGISelLegacy(TM, OptLevel);
}
void XtensaDAGToDAGISel::Select(SDNode *Node) {
>From f6ceec46808843796babbf5b03513f3df8a8a597 Mon Sep 17 00:00:00 2001
From: PaperChalice <liujunchang97 at outlook.com>
Date: Sun, 19 May 2024 12:25:38 +0800
Subject: [PATCH 25/26] [CodeGenPassBuilder] Don't skip required passes
---
llvm/include/llvm/Passes/CodeGenPassBuilder.h | 9 +++++++--
llvm/test/tools/llc/new-pm/start-stop.ll | 4 ++--
2 files changed, 9 insertions(+), 4 deletions(-)
diff --git a/llvm/include/llvm/Passes/CodeGenPassBuilder.h b/llvm/include/llvm/Passes/CodeGenPassBuilder.h
index 17bea5da48ce1..afe066101c753 100644
--- a/llvm/include/llvm/Passes/CodeGenPassBuilder.h
+++ b/llvm/include/llvm/Passes/CodeGenPassBuilder.h
@@ -140,6 +140,9 @@ template <typename DerivedT, typename TargetMachineT> class CodeGenPassBuilder {
}
protected:
+ template <typename PassT>
+ using has_required_t = decltype(std::declval<PassT &>().isRequired());
+
template <typename PassT>
using is_module_pass_t = decltype(std::declval<PassT &>().run(
std::declval<Module &>(), std::declval<ModuleAnalysisManager &>()));
@@ -170,8 +173,10 @@ template <typename DerivedT, typename TargetMachineT> class CodeGenPassBuilder {
static_assert((is_detected<is_function_pass_t, PassT>::value ||
is_detected<is_module_pass_t, PassT>::value) &&
"Only module pass and function pass are supported.");
-
- if (!PB.runBeforeAdding(Name))
+ bool Required = false;
+ if constexpr (is_detected<has_required_t, PassT>::value)
+ Required = PassT::isRequired();
+ if (!PB.runBeforeAdding(Name) && !Required)
return;
// Add Function Pass
diff --git a/llvm/test/tools/llc/new-pm/start-stop.ll b/llvm/test/tools/llc/new-pm/start-stop.ll
index ba225d227d4ca..9c3b9f009178f 100644
--- a/llvm/test/tools/llc/new-pm/start-stop.ll
+++ b/llvm/test/tools/llc/new-pm/start-stop.ll
@@ -1,5 +1,5 @@
; RUN: llc -mtriple=x86_64-pc-linux-gnu -enable-new-pm -print-pipeline-passes -start-before=mergeicmps -stop-after=gc-lowering -filetype=null %s | FileCheck --match-full-lines %s --check-prefix=NULL
; RUN: llc -mtriple=x86_64-pc-linux-gnu -enable-new-pm -print-pipeline-passes -start-before=mergeicmps -stop-after=gc-lowering -o /dev/null %s | FileCheck --match-full-lines %s --check-prefix=OBJ
-; NULL: function(mergeicmps,expand-memcmp,gc-lowering)
-; OBJ: function(mergeicmps,expand-memcmp,gc-lowering),PrintMIRPreparePass,function(machine-function(print),invalidate<machine-function-info>)
+; NULL: require<MachineModuleAnalysis>,require<profile-summary>,require<collector-metadata>,function(verify,loop-mssa(loop-reduce),mergeicmps,expand-memcmp,gc-lowering,ee-instrument<post-inline>,verify)
+; OBJ: require<MachineModuleAnalysis>,require<profile-summary>,require<collector-metadata>,function(verify,loop-mssa(loop-reduce),mergeicmps,expand-memcmp,gc-lowering,ee-instrument<post-inline>,verify),PrintMIRPreparePass,function(machine-function(print),invalidate<machine-function-info>)
>From 1fd885bd7cc7e12142f110b56e0eaefeb13909ab Mon Sep 17 00:00:00 2001
From: PaperChalice <liujunchang97 at outlook.com>
Date: Sun, 19 May 2024 13:03:12 +0800
Subject: [PATCH 26/26] [AMDGPU] Port amdgpu-isel to new pass manager
---
.../Target/AMDGPU/AMDGPUCodeGenPassBuilder.cpp | 8 ++++++--
llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp | 4 ++++
llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h | 5 +++++
llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def | 6 ++++++
llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 1 +
llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 15 +++++++++------
.../AMDGPU/buffer-atomic-fadd.f32-no-rtn.ll | 4 ++++
.../CodeGen/AMDGPU/buffer-atomic-fadd.f32-rtn.ll | 5 ++++-
.../test/CodeGen/AMDGPU/buffer-atomic-fadd.f64.ll | 2 ++
.../AMDGPU/buffer-atomic-fadd.v2f16-no-rtn.ll | 3 +++
.../AMDGPU/buffer-atomic-fadd.v2f16-rtn.ll | 2 ++
.../AMDGPU/buffer-intrinsics-mmo-offsets.ll | 1 +
llvm/test/CodeGen/AMDGPU/bug-v4f64-subvector.ll | 1 +
llvm/test/CodeGen/AMDGPU/carryout-selection.ll | 1 +
llvm/test/CodeGen/AMDGPU/dagcombine-fma-crash.ll | 1 +
llvm/test/CodeGen/AMDGPU/divergence-driven-abs.ll | 2 ++
.../AMDGPU/divergence-driven-bitreverse.ll | 1 +
.../CodeGen/AMDGPU/divergence-driven-ctlz-cttz.ll | 1 +
.../CodeGen/AMDGPU/divergence-driven-ctpop.ll | 1 +
.../CodeGen/AMDGPU/divergence-driven-min-max.ll | 1 +
.../AMDGPU/divergence-driven-negsubinlineconst.ll | 2 ++
.../CodeGen/AMDGPU/divergence-driven-not-isel.ll | 1 +
.../test/CodeGen/AMDGPU/divergence-driven-xnor.ll | 2 ++
.../CodeGen/AMDGPU/extract_subvector_vec4_vec3.ll | 1 +
llvm/test/CodeGen/AMDGPU/flat-atomic-fadd.f32.ll | 2 ++
llvm/test/CodeGen/AMDGPU/flat-atomic-fadd.f64.ll | 2 ++
.../AMDGPU/fneg-fabs-divergence-driven-isel.ll | 2 ++
.../AMDGPU/global-atomic-fadd.v2f16-no-rtn.ll | 3 +++
.../AMDGPU/global-atomic-fadd.v2f16-rtn.ll | 2 ++
llvm/test/CodeGen/AMDGPU/img-nouse-adjust.ll | 1 +
llvm/test/CodeGen/AMDGPU/implicit-def-muse.ll | 1 +
.../CodeGen/AMDGPU/legalize-fp-load-invariant.ll | 1 +
.../AMDGPU/llvm.amdgcn.make.buffer.rsrc.ll | 1 +
33 files changed, 77 insertions(+), 9 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPassBuilder.cpp b/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPassBuilder.cpp
index 01ab61a0e4070..7c353fd102848 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPassBuilder.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPassBuilder.cpp
@@ -7,7 +7,9 @@
//===----------------------------------------------------------------------===//
#include "AMDGPUCodeGenPassBuilder.h"
+#include "AMDGPUISelDAGToDAG.h"
#include "AMDGPUTargetMachine.h"
+#include "llvm/Analysis/UniformityAnalysis.h"
using namespace llvm;
@@ -25,6 +27,8 @@ AMDGPUCodeGenPassBuilder::AMDGPUCodeGenPassBuilder(
void AMDGPUCodeGenPassBuilder::addPreISel(AddIRPass &addPass) const {
// TODO: Add passes pre instruction selection.
+ // Test only, convert to real IR passes in future.
+ addPass(RequireAnalysisPass<UniformityInfoAnalysis, Function>());
}
void AMDGPUCodeGenPassBuilder::addAsmPrinter(AddMachinePass &addPass,
@@ -32,7 +36,7 @@ void AMDGPUCodeGenPassBuilder::addAsmPrinter(AddMachinePass &addPass,
// TODO: Add AsmPrinter.
}
-Error AMDGPUCodeGenPassBuilder::addInstSelector(AddMachinePass &) const {
- // TODO: Add instruction selector.
+Error AMDGPUCodeGenPassBuilder::addInstSelector(AddMachinePass &addPass) const {
+ addPass(AMDGPUISelDAGToDAGPass(TM));
return Error::success();
}
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
index 5bdd0815c925f..db60ffe798de6 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
@@ -777,6 +777,10 @@ StringRef AMDGPUDAGToDAGISelLegacy::getPassName() const {
return "AMDGPU DAG->DAG Pattern Instruction Selection";
}
+AMDGPUISelDAGToDAGPass::AMDGPUISelDAGToDAGPass(TargetMachine &TM)
+ : SelectionDAGISelPass(
+ std::make_unique<AMDGPUDAGToDAGISel>(TM, TM.getOptLevel())) {}
+
//===----------------------------------------------------------------------===//
// Complex Patterns
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
index 7d13bf6fda5e3..e5fe12ed331d4 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
@@ -280,6 +280,11 @@ class AMDGPUDAGToDAGISel : public SelectionDAGISel {
#include "AMDGPUGenDAGISel.inc"
};
+class AMDGPUISelDAGToDAGPass : public SelectionDAGISelPass {
+public:
+ AMDGPUISelDAGToDAGPass(TargetMachine &TM);
+};
+
class AMDGPUDAGToDAGISelLegacy : public SelectionDAGISelLegacy {
public:
static char ID;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def b/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
index 90f36fadf3590..57fc3314dd970 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
+++ b/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
@@ -71,3 +71,9 @@ FUNCTION_PASS_WITH_PARAMS(
},
parseAMDGPUAtomicOptimizerStrategy, "strategy=dpp|iterative|none")
#undef FUNCTION_PASS_WITH_PARAMS
+
+#ifndef MACHINE_FUNCTION_PASS
+#define MACHINE_FUNCTION_PASS(NAME, CREATE_PASS)
+#endif
+MACHINE_FUNCTION_PASS("amdgpu-isel", AMDGPUISelDAGToDAGPass(*this))
+#undef MACHINE_FUNCTION_PASS
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index d5117ff0481c7..ee16467faa08b 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -19,6 +19,7 @@
#include "AMDGPUCtorDtorLowering.h"
#include "AMDGPUExportClustering.h"
#include "AMDGPUIGroupLP.h"
+#include "AMDGPUISelDAGToDAG.h"
#include "AMDGPUMacroFusion.h"
#include "AMDGPURegBankSelect.h"
#include "AMDGPUTargetObjectFile.h"
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 89e83babcfef4..0633445397b85 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -3074,9 +3074,10 @@ SDValue SITargetLowering::LowerFormalArguments(
if (IsEntryFunc)
allocateSystemSGPRs(CCInfo, MF, *Info, CallConv, IsGraphics);
- auto &ArgUsageInfo =
- DAG.getPass()->getAnalysis<AMDGPUArgumentUsageInfo>();
- ArgUsageInfo.setFuncArgInfo(Fn, Info->getArgInfo());
+ if (DAG.getPass()) {
+ auto &ArgUsageInfo = DAG.getPass()->getAnalysis<AMDGPUArgumentUsageInfo>();
+ ArgUsageInfo.setFuncArgInfo(Fn, Info->getArgInfo());
+ }
unsigned StackArgSize = CCInfo.getStackSize();
Info->setBytesInStackArgArea(StackArgSize);
@@ -3288,9 +3289,11 @@ void SITargetLowering::passSpecialInputs(
const AMDGPUFunctionArgInfo *CalleeArgInfo
= &AMDGPUArgumentUsageInfo::FixedABIFunctionInfo;
if (const Function *CalleeFunc = CLI.CB->getCalledFunction()) {
- auto &ArgUsageInfo =
- DAG.getPass()->getAnalysis<AMDGPUArgumentUsageInfo>();
- CalleeArgInfo = &ArgUsageInfo.lookupFuncArgInfo(*CalleeFunc);
+ if (DAG.getPass()) {
+ auto &ArgUsageInfo =
+ DAG.getPass()->getAnalysis<AMDGPUArgumentUsageInfo>();
+ CalleeArgInfo = &ArgUsageInfo.lookupFuncArgInfo(*CalleeFunc);
+ }
}
// TODO: Unify with private memory register handling. This is complicated by
diff --git a/llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.f32-no-rtn.ll b/llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.f32-no-rtn.ll
index 41eb2b7bb2748..85a701b23a6cf 100644
--- a/llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.f32-no-rtn.ll
+++ b/llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.f32-no-rtn.ll
@@ -3,6 +3,10 @@
; RUN: llc -mtriple=amdgcn -mcpu=gfx90a -verify-machineinstrs -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GFX90A_GFX940 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx940 -verify-machineinstrs -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GFX90A_GFX940 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GFX908_GFX11 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx908 -enable-new-pm -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GFX908_GFX11 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx90a -enable-new-pm -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GFX90A_GFX940 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx940 -enable-new-pm -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GFX90A_GFX940 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -enable-new-pm -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GFX908_GFX11 %s
define amdgpu_ps void @buffer_atomic_fadd_f32_offset_no_rtn(float %val, <4 x i32> inreg %rsrc, i32 inreg %soffset) {
; GFX908_GFX11-LABEL: name: buffer_atomic_fadd_f32_offset_no_rtn
diff --git a/llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.f32-rtn.ll b/llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.f32-rtn.ll
index f964da2ddf402..417dee573c5da 100644
--- a/llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.f32-rtn.ll
+++ b/llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.f32-rtn.ll
@@ -1,7 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; RUN: llc -mtriple=amdgcn -mcpu=gfx90a -verify-machineinstrs -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GFX90A_GFX940 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx940 -verify-machineinstrs -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GFX90A_GFX940 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GFX11 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -enable-new-pm -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GFX11 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx90a -enable-new-pm -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GFX90A_GFX940 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx940 -enable-new-pm -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GFX90A_GFX940 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -enable-new-pm -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GFX11 %s
define amdgpu_ps float @buffer_atomic_fadd_f32_offset_rtn(float %val, <4 x i32> inreg %rsrc, i32 inreg %soffset) {
; GFX90A_GFX940-LABEL: name: buffer_atomic_fadd_f32_offset_rtn
diff --git a/llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.f64.ll b/llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.f64.ll
index 89a29526320c1..ff087715e0fc0 100644
--- a/llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.f64.ll
+++ b/llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.f64.ll
@@ -1,6 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; RUN: llc -mtriple=amdgcn -mcpu=gfx90a -verify-machineinstrs -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GFX90A_GFX940 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx940 -verify-machineinstrs -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GFX90A_GFX940 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx90a -enable-new-pm -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GFX90A_GFX940 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx940 -enable-new-pm -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GFX90A_GFX940 %s
define amdgpu_ps void @buffer_atomic_fadd_f64_offset_no_rtn(double %val, <4 x i32> inreg %rsrc, i32 inreg %soffset) {
; GFX90A_GFX940-LABEL: name: buffer_atomic_fadd_f64_offset_no_rtn
diff --git a/llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.v2f16-no-rtn.ll b/llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.v2f16-no-rtn.ll
index 0b62977613f1d..44fddc372293f 100644
--- a/llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.v2f16-no-rtn.ll
+++ b/llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.v2f16-no-rtn.ll
@@ -2,6 +2,9 @@
; RUN: llc -mtriple=amdgcn -mcpu=gfx908 -verify-machineinstrs -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GFX908 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx90a -verify-machineinstrs -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GFX90A_GFX940 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx940 -verify-machineinstrs -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GFX90A_GFX940 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx908 -enable-new-pm -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GFX908 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx90a -enable-new-pm -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GFX90A_GFX940 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx940 -enable-new-pm -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GFX90A_GFX940 %s
define amdgpu_ps void @buffer_atomic_fadd_v2f16_offset_no_rtn(<2 x half> %val, <4 x i32> inreg %rsrc, i32 inreg %soffset) {
; GFX908-LABEL: name: buffer_atomic_fadd_v2f16_offset_no_rtn
diff --git a/llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.v2f16-rtn.ll b/llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.v2f16-rtn.ll
index 8c33683c0f5e0..c4ef1390a288f 100644
--- a/llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.v2f16-rtn.ll
+++ b/llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.v2f16-rtn.ll
@@ -1,6 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; RUN: llc -mtriple=amdgcn -mcpu=gfx90a -verify-machineinstrs -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GFX90A_GFX940 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx940 -verify-machineinstrs -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GFX90A_GFX940 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx90a -enable-new-pm -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GFX90A_GFX940 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx940 -enable-new-pm -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GFX90A_GFX940 %s
define amdgpu_ps <2 x half> @buffer_atomic_fadd_v2f16_offset_rtn(<2 x half> %val, <4 x i32> inreg %rsrc, i32 inreg %soffset) {
; GFX90A_GFX940-LABEL: name: buffer_atomic_fadd_v2f16_offset_rtn
diff --git a/llvm/test/CodeGen/AMDGPU/buffer-intrinsics-mmo-offsets.ll b/llvm/test/CodeGen/AMDGPU/buffer-intrinsics-mmo-offsets.ll
index f4cd19a2ffa80..a62ea8fe4606a 100644
--- a/llvm/test/CodeGen/AMDGPU/buffer-intrinsics-mmo-offsets.ll
+++ b/llvm/test/CodeGen/AMDGPU/buffer-intrinsics-mmo-offsets.ll
@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; RUN: llc -mtriple=amdgcn -mcpu=gfx908 -verify-machineinstrs -amdgpu-atomic-optimizer-strategy=None -stop-after=amdgpu-isel -o - %s | FileCheck -check-prefix=GCN %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx908 -enable-new-pm -amdgpu-atomic-optimizer-strategy=None -stop-after=amdgpu-isel -o - %s | FileCheck -check-prefix=GCN %s
define amdgpu_cs void @mmo_offsets0(ptr addrspace(6) inreg noalias align(16) dereferenceable(18446744073709551615) %arg0, i32 %arg1) {
; GCN-LABEL: name: mmo_offsets0
diff --git a/llvm/test/CodeGen/AMDGPU/bug-v4f64-subvector.ll b/llvm/test/CodeGen/AMDGPU/bug-v4f64-subvector.ll
index 459913eb4f6e7..2c7072b8c93b1 100644
--- a/llvm/test/CodeGen/AMDGPU/bug-v4f64-subvector.ll
+++ b/llvm/test/CodeGen/AMDGPU/bug-v4f64-subvector.ll
@@ -1,4 +1,5 @@
; RUN: llc < %s -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -start-before=amdgpu-isel -stop-after=amdgpu-isel -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
+; RUN: llc < %s -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -stop-after=amdgpu-isel -enable-new-pm | FileCheck %s --check-prefixes=CHECK
; This caused failure in infinite cycle in Selection DAG (combine) due to missing insert_subvector.
;
diff --git a/llvm/test/CodeGen/AMDGPU/carryout-selection.ll b/llvm/test/CodeGen/AMDGPU/carryout-selection.ll
index 9a22635e880f1..a0499ef6d0f6a 100644
--- a/llvm/test/CodeGen/AMDGPU/carryout-selection.ll
+++ b/llvm/test/CodeGen/AMDGPU/carryout-selection.ll
@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=amdgcn -stop-after=amdgpu-isel < %s | FileCheck -enable-var-scope -check-prefixes=GCN-ISEL %s
+; RUN: llc -mtriple=amdgcn -stop-after=amdgpu-isel -enable-new-pm < %s | FileCheck -enable-var-scope -check-prefixes=GCN-ISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=CISI %s
; RUN: llc -mtriple=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=VI %s
diff --git a/llvm/test/CodeGen/AMDGPU/dagcombine-fma-crash.ll b/llvm/test/CodeGen/AMDGPU/dagcombine-fma-crash.ll
index 09a1f45557608..8b1a6878136a9 100644
--- a/llvm/test/CodeGen/AMDGPU/dagcombine-fma-crash.ll
+++ b/llvm/test/CodeGen/AMDGPU/dagcombine-fma-crash.ll
@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; RUN: llc -mtriple=amdgcn -mcpu=gfx1030 -start-before=amdgpu-isel -stop-after=amdgpu-isel < %s | FileCheck %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1030 -enable-new-pm -start-before=amdgpu-isel -stop-after=amdgpu-isel < %s | FileCheck %s
define void @main(float %arg) {
; CHECK-LABEL: name: main
diff --git a/llvm/test/CodeGen/AMDGPU/divergence-driven-abs.ll b/llvm/test/CodeGen/AMDGPU/divergence-driven-abs.ll
index c135acaaf4744..4ea553b8aaad0 100644
--- a/llvm/test/CodeGen/AMDGPU/divergence-driven-abs.ll
+++ b/llvm/test/CodeGen/AMDGPU/divergence-driven-abs.ll
@@ -1,5 +1,7 @@
; RUN: llc -mtriple=amdgcn -stop-after=amdgpu-isel < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -stop-after=amdgpu-isel < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX900 %s
+; RUN: llc -mtriple=amdgcn -enable-new-pm -stop-after=amdgpu-isel < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -enable-new-pm -stop-after=amdgpu-isel < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX900 %s
; GCN-LABEL: name: s_abs_i32
; GCN: S_ABS_I32
diff --git a/llvm/test/CodeGen/AMDGPU/divergence-driven-bitreverse.ll b/llvm/test/CodeGen/AMDGPU/divergence-driven-bitreverse.ll
index d5597df08aa26..85ae5f13e7319 100644
--- a/llvm/test/CodeGen/AMDGPU/divergence-driven-bitreverse.ll
+++ b/llvm/test/CodeGen/AMDGPU/divergence-driven-bitreverse.ll
@@ -1,4 +1,5 @@
; RUN: llc -mtriple=amdgcn -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GCN %s
+; RUN: llc -mtriple=amdgcn -enable-new-pm -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GCN %s
; GCN-LABEL: name: uniform_bitreverse_i32
; GCN: S_BREV_B32
diff --git a/llvm/test/CodeGen/AMDGPU/divergence-driven-ctlz-cttz.ll b/llvm/test/CodeGen/AMDGPU/divergence-driven-ctlz-cttz.ll
index 45cb4c623a4b2..030de51abb906 100644
--- a/llvm/test/CodeGen/AMDGPU/divergence-driven-ctlz-cttz.ll
+++ b/llvm/test/CodeGen/AMDGPU/divergence-driven-ctlz-cttz.ll
@@ -1,4 +1,5 @@
; RUN: llc -mtriple=amdgcn -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GCN %s
+; RUN: llc -mtriple=amdgcn -enable-new-pm -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GCN %s
; GCN-LABEL: name: s_ctlz_i32
; GCN: S_FLBIT_I32_B32
diff --git a/llvm/test/CodeGen/AMDGPU/divergence-driven-ctpop.ll b/llvm/test/CodeGen/AMDGPU/divergence-driven-ctpop.ll
index 5c5b7b3e5b9a6..4a3a44d09210e 100644
--- a/llvm/test/CodeGen/AMDGPU/divergence-driven-ctpop.ll
+++ b/llvm/test/CodeGen/AMDGPU/divergence-driven-ctpop.ll
@@ -1,4 +1,5 @@
; RUN: llc -mtriple=amdgcn -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GCN %s
+; RUN: llc -mtriple=amdgcn -enable-new-pm -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GCN %s
; GCN-LABEL: name: s_ctpop_i32
; GCN: S_BCNT1_I32_B32
diff --git a/llvm/test/CodeGen/AMDGPU/divergence-driven-min-max.ll b/llvm/test/CodeGen/AMDGPU/divergence-driven-min-max.ll
index 2711e532fc164..45c805aa1b80c 100644
--- a/llvm/test/CodeGen/AMDGPU/divergence-driven-min-max.ll
+++ b/llvm/test/CodeGen/AMDGPU/divergence-driven-min-max.ll
@@ -1,4 +1,5 @@
; RUN: llc -mtriple=amdgcn -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GCN %s
+; RUN: llc -mtriple=amdgcn -enable-new-pm -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GCN %s
; GCN-LABEL: name: uniform_imin
; GCN: S_MIN_I32
diff --git a/llvm/test/CodeGen/AMDGPU/divergence-driven-negsubinlineconst.ll b/llvm/test/CodeGen/AMDGPU/divergence-driven-negsubinlineconst.ll
index a7f3c18accc93..e740bb3d5eef1 100644
--- a/llvm/test/CodeGen/AMDGPU/divergence-driven-negsubinlineconst.ll
+++ b/llvm/test/CodeGen/AMDGPU/divergence-driven-negsubinlineconst.ll
@@ -1,5 +1,7 @@
; RUN: llc -mtriple=amdgcn -stop-after=amdgpu-isel < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -stop-after=amdgpu-isel < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX900 %s
+; RUN: llc -mtriple=amdgcn -enable-new-pm -stop-after=amdgpu-isel < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -enable-new-pm -stop-after=amdgpu-isel < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX900 %s
; GCN-LABEL: name: uniform_add_SIC
; GCN: S_SUB_I32 killed %{{[0-9]+}}, 32
diff --git a/llvm/test/CodeGen/AMDGPU/divergence-driven-not-isel.ll b/llvm/test/CodeGen/AMDGPU/divergence-driven-not-isel.ll
index f673f2f43d7f3..5f0d17d086605 100644
--- a/llvm/test/CodeGen/AMDGPU/divergence-driven-not-isel.ll
+++ b/llvm/test/CodeGen/AMDGPU/divergence-driven-not-isel.ll
@@ -1,4 +1,5 @@
; RUN: llc -mtriple=amdgcn -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GCN %s
+; RUN: llc -mtriple=amdgcn -enable-new-pm -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GCN %s
; GCN-LABEL: name: scalar_not_i32
; GCN: S_NOT_B32
diff --git a/llvm/test/CodeGen/AMDGPU/divergence-driven-xnor.ll b/llvm/test/CodeGen/AMDGPU/divergence-driven-xnor.ll
index ccfc908b40052..e8d8b1eb1abcb 100644
--- a/llvm/test/CodeGen/AMDGPU/divergence-driven-xnor.ll
+++ b/llvm/test/CodeGen/AMDGPU/divergence-driven-xnor.ll
@@ -1,5 +1,7 @@
; RUN: llc -mtriple=amdgcn -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx906 -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GCN_DL %s
+; RUN: llc -mtriple=amdgcn -enable-new-pm -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GCN %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx906 -enable-new-pm -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GCN_DL %s
; GCN-LABEL: name: uniform_xnor_i64
; GCN: S_XNOR_B64
diff --git a/llvm/test/CodeGen/AMDGPU/extract_subvector_vec4_vec3.ll b/llvm/test/CodeGen/AMDGPU/extract_subvector_vec4_vec3.ll
index d0c0d3acf2717..1319c526868c3 100644
--- a/llvm/test/CodeGen/AMDGPU/extract_subvector_vec4_vec3.ll
+++ b/llvm/test/CodeGen/AMDGPU/extract_subvector_vec4_vec3.ll
@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 < %s -stop-after=amdgpu-isel | FileCheck -check-prefix=GCN %s
+; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 < %s -enable-new-pm -stop-after=amdgpu-isel | FileCheck -check-prefix=GCN %s
; We want to see a BUFFER_LOAD, some register shuffling, and a BUFFER_STORE.
; Specifically, we do not want to see a BUFFER_STORE that says "store into
diff --git a/llvm/test/CodeGen/AMDGPU/flat-atomic-fadd.f32.ll b/llvm/test/CodeGen/AMDGPU/flat-atomic-fadd.f32.ll
index ce4beb8789dc3..5eb8620f1ff2d 100644
--- a/llvm/test/CodeGen/AMDGPU/flat-atomic-fadd.f32.ll
+++ b/llvm/test/CodeGen/AMDGPU/flat-atomic-fadd.f32.ll
@@ -1,6 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; RUN: llc -mtriple=amdgcn -mcpu=gfx940 -verify-machineinstrs -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GFX940 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GFX11 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx940 -enable-new-pm -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GFX940 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -enable-new-pm -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GFX11 %s
define amdgpu_ps void @flat_atomic_fadd_f32_no_rtn_intrinsic(ptr %ptr, float %data) {
; GFX940-LABEL: name: flat_atomic_fadd_f32_no_rtn_intrinsic
diff --git a/llvm/test/CodeGen/AMDGPU/flat-atomic-fadd.f64.ll b/llvm/test/CodeGen/AMDGPU/flat-atomic-fadd.f64.ll
index afd38136870b8..df803ad8470d6 100644
--- a/llvm/test/CodeGen/AMDGPU/flat-atomic-fadd.f64.ll
+++ b/llvm/test/CodeGen/AMDGPU/flat-atomic-fadd.f64.ll
@@ -1,6 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; RUN: llc -mtriple=amdgcn -mcpu=gfx90a -verify-machineinstrs -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GFX90A_GFX940 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx940 -verify-machineinstrs -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GFX90A_GFX940 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx90a -enable-new-pm -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GFX90A_GFX940 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx940 -enable-new-pm -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GFX90A_GFX940 %s
define amdgpu_ps void @flat_atomic_fadd_f64_no_rtn_intrinsic(ptr %ptr, double %data) {
; GFX90A_GFX940-LABEL: name: flat_atomic_fadd_f64_no_rtn_intrinsic
diff --git a/llvm/test/CodeGen/AMDGPU/fneg-fabs-divergence-driven-isel.ll b/llvm/test/CodeGen/AMDGPU/fneg-fabs-divergence-driven-isel.ll
index 07f315ea6cb48..d431503643d63 100644
--- a/llvm/test/CodeGen/AMDGPU/fneg-fabs-divergence-driven-isel.ll
+++ b/llvm/test/CodeGen/AMDGPU/fneg-fabs-divergence-driven-isel.ll
@@ -1,5 +1,7 @@
; RUN: llc -mtriple=amdgcn -stop-after=amdgpu-isel < %s | FileCheck -check-prefixes=GCN,SI %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -stop-after=amdgpu-isel < %s | FileCheck -check-prefixes=GCN,FP16 %s
+; RUN: llc -mtriple=amdgcn -enable-new-pm -stop-after=amdgpu-isel < %s | FileCheck -check-prefixes=GCN,SI %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -enable-new-pm -stop-after=amdgpu-isel < %s | FileCheck -check-prefixes=GCN,FP16 %s
define amdgpu_kernel void @divergent_fneg_f32(ptr addrspace(1) %out, ptr addrspace(1) %in) {
diff --git a/llvm/test/CodeGen/AMDGPU/global-atomic-fadd.v2f16-no-rtn.ll b/llvm/test/CodeGen/AMDGPU/global-atomic-fadd.v2f16-no-rtn.ll
index 666971618a5c2..60345c0b44339 100644
--- a/llvm/test/CodeGen/AMDGPU/global-atomic-fadd.v2f16-no-rtn.ll
+++ b/llvm/test/CodeGen/AMDGPU/global-atomic-fadd.v2f16-no-rtn.ll
@@ -2,6 +2,9 @@
; RUN: llc -mtriple=amdgcn -mcpu=gfx908 -verify-machineinstrs -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GFX908 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx90a -verify-machineinstrs -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GFX90A_GFX940 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx940 -verify-machineinstrs -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GFX90A_GFX940 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx908 -enable-new-pm -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GFX908 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx90a -enable-new-pm -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GFX90A_GFX940 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx940 -enable-new-pm -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GFX90A_GFX940 %s
define amdgpu_ps void @global_atomic_fadd_v2f16_no_rtn_intrinsic(ptr addrspace(1) %ptr, <2 x half> %data) {
; GFX908-LABEL: name: global_atomic_fadd_v2f16_no_rtn_intrinsic
diff --git a/llvm/test/CodeGen/AMDGPU/global-atomic-fadd.v2f16-rtn.ll b/llvm/test/CodeGen/AMDGPU/global-atomic-fadd.v2f16-rtn.ll
index ae81e97ca39e2..c8caf1fe365b1 100644
--- a/llvm/test/CodeGen/AMDGPU/global-atomic-fadd.v2f16-rtn.ll
+++ b/llvm/test/CodeGen/AMDGPU/global-atomic-fadd.v2f16-rtn.ll
@@ -1,6 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; RUN: llc -mtriple=amdgcn -mcpu=gfx90a -verify-machineinstrs -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GFX90A_GFX940 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx940 -verify-machineinstrs -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GFX90A_GFX940 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx90a -enable-new-pm -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GFX90A_GFX940 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx940 -enable-new-pm -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GFX90A_GFX940 %s
define amdgpu_ps <2 x half> @global_atomic_fadd_v2f16_rtn_intrinsic(ptr addrspace(1) %ptr, <2 x half> %data) {
; GFX90A_GFX940-LABEL: name: global_atomic_fadd_v2f16_rtn_intrinsic
diff --git a/llvm/test/CodeGen/AMDGPU/img-nouse-adjust.ll b/llvm/test/CodeGen/AMDGPU/img-nouse-adjust.ll
index 9927f4d166bad..6d1adb9c1f87d 100644
--- a/llvm/test/CodeGen/AMDGPU/img-nouse-adjust.ll
+++ b/llvm/test/CodeGen/AMDGPU/img-nouse-adjust.ll
@@ -1,4 +1,5 @@
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -start-before=amdgpu-isel -stop-after=amdgpu-isel -verify-machineinstrs < %s | FileCheck %s --check-prefix=GCN
+; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -start-before=amdgpu-isel -stop-after=amdgpu-isel -enable-new-pm < %s | FileCheck %s --check-prefix=GCN
; We're really just checking for no crashes
; The feature we're testing for in AdjustWriteMask leaves the image_load as an instruction just post amdgpu-isel
diff --git a/llvm/test/CodeGen/AMDGPU/implicit-def-muse.ll b/llvm/test/CodeGen/AMDGPU/implicit-def-muse.ll
index 88605785f8141..f2858e4ff79c9 100644
--- a/llvm/test/CodeGen/AMDGPU/implicit-def-muse.ll
+++ b/llvm/test/CodeGen/AMDGPU/implicit-def-muse.ll
@@ -1,4 +1,5 @@
; RUN: llc -mtriple=amdgcn -stop-after=amdgpu-isel -verify-machineinstrs -o - %s | FileCheck %s
+; RUN: llc -mtriple=amdgcn -stop-after=amdgpu-isel -enable-new-pm -o - %s | FileCheck %s
; CHECK-LABEL: vcopy_i1_undef
; CHECK: [[IMPDEF0:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
diff --git a/llvm/test/CodeGen/AMDGPU/legalize-fp-load-invariant.ll b/llvm/test/CodeGen/AMDGPU/legalize-fp-load-invariant.ll
index 55fd8336e967b..599488822b644 100644
--- a/llvm/test/CodeGen/AMDGPU/legalize-fp-load-invariant.ll
+++ b/llvm/test/CodeGen/AMDGPU/legalize-fp-load-invariant.ll
@@ -1,4 +1,5 @@
; RUN: llc -mtriple=amdgcn -mcpu=tahiti -verify-machineinstrs -stop-after=amdgpu-isel -o - %s | FileCheck -check-prefix=GCN %s
+; RUN: llc -mtriple=amdgcn -mcpu=tahiti -enable-new-pm -stop-after=amdgpu-isel -o - %s | FileCheck -check-prefix=GCN %s
; Type legalization for illegal FP type results was dropping invariant
; and dereferenceable flags.
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.make.buffer.rsrc.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.make.buffer.rsrc.ll
index 18c977bf5100d..b4840bce53d2c 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.make.buffer.rsrc.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.make.buffer.rsrc.ll
@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs -stop-after=amdgpu-isel < %s | FileCheck %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -enable-new-pm -stop-after=amdgpu-isel < %s | FileCheck %s
define amdgpu_ps ptr addrspace(8) @basic_raw_buffer(ptr inreg %p) {
; CHECK-LABEL: name: basic_raw_buffer
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