[llvm] 0bced10 - [SDAG][X86] Extend SplitVecOp_VSETCC for STRICT_FSETCC. (#92509)
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Sun May 19 17:53:25 PDT 2024
Author: Freddy Ye
Date: 2024-05-20T08:53:21+08:00
New Revision: 0bced10f290bb96d675874a89f1b6789a2384e30
URL: https://github.com/llvm/llvm-project/commit/0bced10f290bb96d675874a89f1b6789a2384e30
DIFF: https://github.com/llvm/llvm-project/commit/0bced10f290bb96d675874a89f1b6789a2384e30.diff
LOG: [SDAG][X86] Extend SplitVecOp_VSETCC for STRICT_FSETCC. (#92509)
Added:
llvm/test/CodeGen/X86/vec-strict-cmp-512-skx.ll
Modified:
llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
index cd858003cf03b..dca5a481fbd0e 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -3033,6 +3033,7 @@ bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) {
"operand!\n");
case ISD::VP_SETCC:
+ case ISD::STRICT_FSETCC:
case ISD::SETCC: Res = SplitVecOp_VSETCC(N); break;
case ISD::BITCAST: Res = SplitVecOp_BITCAST(N); break;
case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break;
@@ -3997,14 +3998,16 @@ SDValue DAGTypeLegalizer::SplitVecOp_TruncateHelper(SDNode *N) {
}
SDValue DAGTypeLegalizer::SplitVecOp_VSETCC(SDNode *N) {
+ bool isStrict = N->getOpcode() == ISD::STRICT_FSETCC;
assert(N->getValueType(0).isVector() &&
- N->getOperand(0).getValueType().isVector() &&
+ N->getOperand(isStrict ? 1 : 0).getValueType().isVector() &&
"Operand types must be vectors");
// The result has a legal vector type, but the input needs splitting.
SDValue Lo0, Hi0, Lo1, Hi1, LoRes, HiRes;
SDLoc DL(N);
- GetSplitVector(N->getOperand(0), Lo0, Hi0);
- GetSplitVector(N->getOperand(1), Lo1, Hi1);
+ GetSplitVector(N->getOperand(isStrict ? 1 : 0), Lo0, Hi0);
+ GetSplitVector(N->getOperand(isStrict ? 2 : 1), Lo1, Hi1);
+
auto PartEltCnt = Lo0.getValueType().getVectorElementCount();
LLVMContext &Context = *DAG.getContext();
@@ -4014,6 +4017,16 @@ SDValue DAGTypeLegalizer::SplitVecOp_VSETCC(SDNode *N) {
if (N->getOpcode() == ISD::SETCC) {
LoRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Lo0, Lo1, N->getOperand(2));
HiRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Hi0, Hi1, N->getOperand(2));
+ } else if (N->getOpcode() == ISD::STRICT_FSETCC) {
+ LoRes = DAG.getNode(ISD::STRICT_FSETCC, DL,
+ DAG.getVTList(PartResVT, N->getValueType(1)),
+ N->getOperand(0), Lo0, Lo1, N->getOperand(3));
+ HiRes = DAG.getNode(ISD::STRICT_FSETCC, DL,
+ DAG.getVTList(PartResVT, N->getValueType(1)),
+ N->getOperand(0), Hi0, Hi1, N->getOperand(3));
+ SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
+ LoRes.getValue(1), HiRes.getValue(1));
+ ReplaceValueWith(SDValue(N, 1), NewChain);
} else {
assert(N->getOpcode() == ISD::VP_SETCC && "Expected VP_SETCC opcode");
SDValue MaskLo, MaskHi, EVLLo, EVLHi;
diff --git a/llvm/test/CodeGen/X86/vec-strict-cmp-512-skx.ll b/llvm/test/CodeGen/X86/vec-strict-cmp-512-skx.ll
new file mode 100644
index 0000000000000..3028b74967378
--- /dev/null
+++ b/llvm/test/CodeGen/X86/vec-strict-cmp-512-skx.ll
@@ -0,0 +1,40 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64 -mcpu=skx | FileCheck %s --check-prefixes=SKX
+
+;; Test no crash for AVX512 targets without prefer-vector-width=512.
+
+define <16 x i32> @test_v16f32_oeq_q(<16 x i32> %a, <16 x i32> %b, <16 x float> %f1, <16 x float> %f2) #0 {
+; SKX-LABEL: test_v16f32_oeq_q:
+; SKX: # %bb.0:
+; SKX-NEXT: vcmpeqps %ymm7, %ymm5, %k1
+; SKX-NEXT: vcmpeqps %ymm6, %ymm4, %k2
+; SKX-NEXT: vpblendmd %ymm0, %ymm2, %ymm0 {%k2}
+; SKX-NEXT: vpblendmd %ymm1, %ymm3, %ymm1 {%k1}
+; SKX-NEXT: retq
+ %cond = call <16 x i1> @llvm.experimental.constrained.fcmp.v16f32(
+ <16 x float> %f1, <16 x float> %f2, metadata !"oeq",
+ metadata !"fpexcept.strict") #0
+ %res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b
+ ret <16 x i32> %res
+}
+
+define <8 x i32> @test_v8f64_oeq_q(<8 x i32> %a, <8 x i32> %b, <8 x double> %f1, <8 x double> %f2) #0 {
+; SKX-LABEL: test_v8f64_oeq_q:
+; SKX: # %bb.0:
+; SKX-NEXT: vcmpeqpd %ymm4, %ymm2, %k0
+; SKX-NEXT: vcmpeqpd %ymm5, %ymm3, %k1
+; SKX-NEXT: kshiftlb $4, %k1, %k1
+; SKX-NEXT: korb %k1, %k0, %k1
+; SKX-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+; SKX-NEXT: retq
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f64(
+ <8 x double> %f1, <8 x double> %f2, metadata !"oeq",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i32> %a, <8 x i32> %b
+ ret <8 x i32> %res
+}
+
+declare <16 x i1> @llvm.experimental.constrained.fcmp.v16f32(<16 x float>, <16 x float>, metadata, metadata)
+declare <8 x i1> @llvm.experimental.constrained.fcmp.v8f64(<8 x double>, <8 x double>, metadata, metadata)
+
+attributes #0 = { nounwind strictfp "min-legal-vector-width"="0" }
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