[llvm] [RISCV] Split WriteVISlideX into WriteVISlideUpX and WriteVISlideDownX (PR #92605)
Min-Yih Hsu via llvm-commits
llvm-commits at lists.llvm.org
Fri May 17 15:54:46 PDT 2024
https://github.com/mshockwave updated https://github.com/llvm/llvm-project/pull/92605
>From 53ae53007e0964d24022a0b4e149462cf021833b Mon Sep 17 00:00:00 2001
From: Min Hsu <min.hsu at sifive.com>
Date: Fri, 17 May 2024 13:55:33 -0700
Subject: [PATCH 1/2] [RISCV] Split WriteVISlideX into WriteVISlideUpX and
WriteVISlideDownX
Some processors might have different latencies and/or rthroughput for
slide up and down operations on integer vectors, yet there is only a
single SchedWrite for both of them at this moment. This patch splits
this SchedWrite into two.
Note that we only tackle the X variant (i.e. using a register value for
index offset) for now.
This is effectively NFC.
---
llvm/lib/Target/RISCV/RISCVInstrInfoV.td | 6 +++++-
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td | 4 +++-
llvm/lib/Target/RISCV/RISCVSchedSiFive7.td | 3 ++-
llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td | 6 ++++--
llvm/lib/Target/RISCV/RISCVScheduleV.td | 6 ++++--
5 files changed, 18 insertions(+), 7 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
index e68fb42ece9f0..10cb15bbcd16d 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
@@ -976,8 +976,12 @@ multiclass VNCLP_IV_V_X_I<string opcodestr, bits<6> funct6> {
}
multiclass VSLD_IV_X_I<string opcodestr, bits<6> funct6> {
+ // Note: In the future, if VISlideI is also splitted into VISlideUpI and
+ // VISlideDownI, it'll probably better to use two separate multiclasses.
+ defvar WriteSlideX = !if(!ge(!find(NAME, "SLIDEUP"), 0),
+ "WriteVISlideUpX", "WriteVISlideDownX");
def X : VALUVX<funct6, OPIVX, opcodestr # ".vx">,
- SchedBinaryMC<"WriteVISlideX", "ReadVISlideV", "ReadVISlideX">;
+ SchedBinaryMC<WriteSlideX, "ReadVISlideV", "ReadVISlideX">;
def I : VALUVI<funct6, opcodestr # ".vi", uimm5>,
SchedUnaryMC<"WriteVISlideI", "ReadVISlideV">;
}
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index 317a6d7d4c52f..9291efaf3aace 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -3381,10 +3381,12 @@ multiclass VPseudoVMAC_VV_VF_AAXA_RM<string Constraint = ""> {
}
multiclass VPseudoVSLD_VX_VI<Operand ImmType = simm5, string Constraint = ""> {
+ defvar WriteSlideX = !if(!ge(!find(NAME, "SLIDEUP"), 0),
+ "WriteVISlideUpX", "WriteVISlideDownX");
foreach m = MxList in {
defvar mx = m.MX;
defm "" : VPseudoVSLDV_VX<m, Constraint>,
- SchedTernary<"WriteVISlideX", "ReadVISlideV", "ReadVISlideV",
+ SchedTernary<WriteSlideX, "ReadVISlideV", "ReadVISlideV",
"ReadVISlideX", mx>;
defm "" : VPseudoVSLDV_VI<ImmType, m, Constraint>,
SchedBinary<"WriteVISlideI", "ReadVISlideV", "ReadVISlideV", mx>;
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
index e67da839bdb87..ae4a2b65a88a4 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
@@ -937,7 +937,8 @@ foreach mx = SchedMxList in {
defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
let Latency = 4, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in {
- defm "" : LMULWriteResMX<"WriteVISlideX", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVISlideUpX", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVISlideDownX", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVISlideI", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVISlide1X", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVFSlide1F", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
index 6ba299385f07e..bcd1f464bc066 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
@@ -679,7 +679,8 @@ foreach mx = SchedMxList in {
foreach mx = ["MF8", "MF4", "MF2", "M1"] in {
defvar IsWorstCase = SiFiveP600IsWorstCaseMX<mx, SchedMxList>.c;
let Latency = 2, ReleaseAtCycles = [1] in {
- defm "" : LMULWriteResMX<"WriteVISlideX", [SiFiveP600VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVISlideUpX", [SiFiveP600VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVISlideDownX", [SiFiveP600VEXQ0], mx, IsWorstCase>;
}
}
@@ -688,7 +689,8 @@ foreach mx = ["M8", "M4", "M2"] in {
defvar LMulLat = SiFiveP600GetLMulCycles<mx>.c;
defvar IsWorstCase = SiFiveP600IsWorstCaseMX<mx, SchedMxList>.c;
let Latency = !add(4, LMulLat), ReleaseAtCycles = [LMulLat] in {
- defm "" : LMULWriteResMX<"WriteVISlideX", [SiFiveP600VEXQ1], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVISlideUpX", [SiFiveP600VEXQ1], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVISlideDownX", [SiFiveP600VEXQ1], mx, IsWorstCase>;
}
}
diff --git a/llvm/lib/Target/RISCV/RISCVScheduleV.td b/llvm/lib/Target/RISCV/RISCVScheduleV.td
index 5be06d4c3f7e7..7cae1a11840aa 100644
--- a/llvm/lib/Target/RISCV/RISCVScheduleV.td
+++ b/llvm/lib/Target/RISCV/RISCVScheduleV.td
@@ -514,7 +514,8 @@ def WriteVMovXS : SchedWrite;
def WriteVMovSF : SchedWrite;
def WriteVMovFS : SchedWrite;
// 16.3. Vector Slide Instructions
-defm "" : LMULSchedWrites<"WriteVISlideX">;
+defm "" : LMULSchedWrites<"WriteVISlideUpX">;
+defm "" : LMULSchedWrites<"WriteVISlideDownX">;
defm "" : LMULSchedWrites<"WriteVISlideI">;
defm "" : LMULSchedWrites<"WriteVISlide1X">;
defm "" : LMULSchedWrites<"WriteVFSlide1F">;
@@ -949,7 +950,8 @@ def : WriteRes<WriteVMovSX, []>;
def : WriteRes<WriteVMovXS, []>;
def : WriteRes<WriteVMovSF, []>;
def : WriteRes<WriteVMovFS, []>;
-defm "" : LMULWriteRes<"WriteVISlideX", []>;
+defm "" : LMULWriteRes<"WriteVISlideUpX", []>;
+defm "" : LMULWriteRes<"WriteVISlideDownX", []>;
defm "" : LMULWriteRes<"WriteVISlideI", []>;
defm "" : LMULWriteRes<"WriteVISlide1X", []>;
defm "" : LMULWriteRes<"WriteVFSlide1F", []>;
>From b03df6e44d7652f518c59a6ce1b13871e7c58b20 Mon Sep 17 00:00:00 2001
From: Min Hsu <min.hsu at sifive.com>
Date: Fri, 17 May 2024 15:53:40 -0700
Subject: [PATCH 2/2] Rename VISlideUp/DownX and VISlideI to VSlideUp/Down and
VSlideI
---
llvm/lib/Target/RISCV/RISCVInstrInfoV.td | 8 ++++----
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td | 4 ++--
llvm/lib/Target/RISCV/RISCVSchedSiFive7.td | 6 +++---
llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td | 10 +++++-----
llvm/lib/Target/RISCV/RISCVScheduleV.td | 12 ++++++------
5 files changed, 20 insertions(+), 20 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
index 10cb15bbcd16d..cfe127e9a8cda 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
@@ -976,14 +976,14 @@ multiclass VNCLP_IV_V_X_I<string opcodestr, bits<6> funct6> {
}
multiclass VSLD_IV_X_I<string opcodestr, bits<6> funct6> {
- // Note: In the future, if VISlideI is also splitted into VISlideUpI and
- // VISlideDownI, it'll probably better to use two separate multiclasses.
+ // Note: In the future, if VISlideI is also split into VSlideUpI and
+ // VSlideDownI, it'll probably better to use two separate multiclasses.
defvar WriteSlideX = !if(!ge(!find(NAME, "SLIDEUP"), 0),
- "WriteVISlideUpX", "WriteVISlideDownX");
+ "WriteVSlideUpX", "WriteVSlideDownX");
def X : VALUVX<funct6, OPIVX, opcodestr # ".vx">,
SchedBinaryMC<WriteSlideX, "ReadVISlideV", "ReadVISlideX">;
def I : VALUVI<funct6, opcodestr # ".vi", uimm5>,
- SchedUnaryMC<"WriteVISlideI", "ReadVISlideV">;
+ SchedUnaryMC<"WriteVSlideI", "ReadVISlideV">;
}
multiclass VSLD1_MV_X<string opcodestr, bits<6> funct6> {
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index 9291efaf3aace..8ba8410a7fb5b 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -3382,14 +3382,14 @@ multiclass VPseudoVMAC_VV_VF_AAXA_RM<string Constraint = ""> {
multiclass VPseudoVSLD_VX_VI<Operand ImmType = simm5, string Constraint = ""> {
defvar WriteSlideX = !if(!ge(!find(NAME, "SLIDEUP"), 0),
- "WriteVISlideUpX", "WriteVISlideDownX");
+ "WriteVSlideUpX", "WriteVSlideDownX");
foreach m = MxList in {
defvar mx = m.MX;
defm "" : VPseudoVSLDV_VX<m, Constraint>,
SchedTernary<WriteSlideX, "ReadVISlideV", "ReadVISlideV",
"ReadVISlideX", mx>;
defm "" : VPseudoVSLDV_VI<ImmType, m, Constraint>,
- SchedBinary<"WriteVISlideI", "ReadVISlideV", "ReadVISlideV", mx>;
+ SchedBinary<"WriteVSlideI", "ReadVISlideV", "ReadVISlideV", mx>;
}
}
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
index ae4a2b65a88a4..966941bdd0faf 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
@@ -937,9 +937,9 @@ foreach mx = SchedMxList in {
defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
let Latency = 4, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in {
- defm "" : LMULWriteResMX<"WriteVISlideUpX", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVISlideDownX", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVISlideI", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSlideUpX", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSlideDownX", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSlideI", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVISlide1X", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVFSlide1F", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
}
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
index bcd1f464bc066..07d72b61862dd 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
@@ -669,7 +669,7 @@ foreach mx = SchedMxList in {
defvar LMulLat = SiFiveP600GetLMulCycles<mx>.c;
defvar IsWorstCase = SiFiveP600IsWorstCaseMX<mx, SchedMxList>.c;
let Latency = 2, ReleaseAtCycles = [LMulLat] in {
- defm "" : LMULWriteResMX<"WriteVISlideI", [SiFiveP600VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSlideI", [SiFiveP600VEXQ0], mx, IsWorstCase>;
}
let Latency = 1, ReleaseAtCycles = [LMulLat] in {
defm "" : LMULWriteResMX<"WriteVISlide1X", [SiFiveP600VEXQ0], mx, IsWorstCase>;
@@ -679,8 +679,8 @@ foreach mx = SchedMxList in {
foreach mx = ["MF8", "MF4", "MF2", "M1"] in {
defvar IsWorstCase = SiFiveP600IsWorstCaseMX<mx, SchedMxList>.c;
let Latency = 2, ReleaseAtCycles = [1] in {
- defm "" : LMULWriteResMX<"WriteVISlideUpX", [SiFiveP600VEXQ0], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVISlideDownX", [SiFiveP600VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSlideUpX", [SiFiveP600VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSlideDownX", [SiFiveP600VEXQ0], mx, IsWorstCase>;
}
}
@@ -689,8 +689,8 @@ foreach mx = ["M8", "M4", "M2"] in {
defvar LMulLat = SiFiveP600GetLMulCycles<mx>.c;
defvar IsWorstCase = SiFiveP600IsWorstCaseMX<mx, SchedMxList>.c;
let Latency = !add(4, LMulLat), ReleaseAtCycles = [LMulLat] in {
- defm "" : LMULWriteResMX<"WriteVISlideUpX", [SiFiveP600VEXQ1], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVISlideDownX", [SiFiveP600VEXQ1], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSlideUpX", [SiFiveP600VEXQ1], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSlideDownX", [SiFiveP600VEXQ1], mx, IsWorstCase>;
}
}
diff --git a/llvm/lib/Target/RISCV/RISCVScheduleV.td b/llvm/lib/Target/RISCV/RISCVScheduleV.td
index 7cae1a11840aa..e4524185991e5 100644
--- a/llvm/lib/Target/RISCV/RISCVScheduleV.td
+++ b/llvm/lib/Target/RISCV/RISCVScheduleV.td
@@ -514,9 +514,9 @@ def WriteVMovXS : SchedWrite;
def WriteVMovSF : SchedWrite;
def WriteVMovFS : SchedWrite;
// 16.3. Vector Slide Instructions
-defm "" : LMULSchedWrites<"WriteVISlideUpX">;
-defm "" : LMULSchedWrites<"WriteVISlideDownX">;
-defm "" : LMULSchedWrites<"WriteVISlideI">;
+defm "" : LMULSchedWrites<"WriteVSlideUpX">;
+defm "" : LMULSchedWrites<"WriteVSlideDownX">;
+defm "" : LMULSchedWrites<"WriteVSlideI">;
defm "" : LMULSchedWrites<"WriteVISlide1X">;
defm "" : LMULSchedWrites<"WriteVFSlide1F">;
// 16.4. Vector Register Gather Instructions
@@ -950,9 +950,9 @@ def : WriteRes<WriteVMovSX, []>;
def : WriteRes<WriteVMovXS, []>;
def : WriteRes<WriteVMovSF, []>;
def : WriteRes<WriteVMovFS, []>;
-defm "" : LMULWriteRes<"WriteVISlideUpX", []>;
-defm "" : LMULWriteRes<"WriteVISlideDownX", []>;
-defm "" : LMULWriteRes<"WriteVISlideI", []>;
+defm "" : LMULWriteRes<"WriteVSlideUpX", []>;
+defm "" : LMULWriteRes<"WriteVSlideDownX", []>;
+defm "" : LMULWriteRes<"WriteVSlideI", []>;
defm "" : LMULWriteRes<"WriteVISlide1X", []>;
defm "" : LMULWriteRes<"WriteVFSlide1F", []>;
defm "" : LMULSEWWriteRes<"WriteVRGatherVV", []>;
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