[llvm] [AArch64] Optimization of repeated constant loads (#51483) (PR #86249)

[via llvm-commits]

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@@ -518,6 +518,14 @@ static inline void expandMOVImmSimple(uint64_t Imm, unsigned BitSize,
     Insn.push_back({ Opc, Imm16,
                      AArch64_AM::getShifterImm(AArch64_AM::LSL, Shift) });
   }
+
+  // Now, we get 16-bit divided Imm. If high and low bits are same in
+  // 32-bit, there is an opportunity to reduce instruction.
+  if (Insn.size() > 2 && (Imm >> 32) == (Imm & UINT_MAX)) {
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ParkHanbum wrote:

got it!

https://github.com/llvm/llvm-project/pull/86249