[llvm] 98deeda - [X86][CodeGen] Use switch-case for transform in X86DAGToDAGISel::PostprocessISelDAG, NFCI
Shengchen Kan via llvm-commits
llvm-commits at lists.llvm.org
Fri May 17 04:47:42 PDT 2024
Author: Shengchen Kan
Date: 2024-05-17T19:47:20+08:00
New Revision: 98deedae929fce01f0c40d5a55d00e93fb121981
URL: https://github.com/llvm/llvm-project/commit/98deedae929fce01f0c40d5a55d00e93fb121981
DIFF: https://github.com/llvm/llvm-project/commit/98deedae929fce01f0c40d5a55d00e93fb121981.diff
LOG: [X86][CodeGen] Use switch-case for transform in X86DAGToDAGISel::PostprocessISelDAG, NFCI
This is to simplify code for #91747
Added:
Modified:
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
index ea3b84d0ca9eb..7f76324fa5705 100644
--- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -1549,136 +1549,147 @@ void X86DAGToDAGISel::PostprocessISelDAG() {
continue;
}
- // Look for a TESTrr+ANDrr pattern where both operands of the test are
- // the same. Rewrite to remove the AND.
unsigned Opc = N->getMachineOpcode();
- if ((Opc == X86::TEST8rr || Opc == X86::TEST16rr ||
- Opc == X86::TEST32rr || Opc == X86::TEST64rr) &&
- N->getOperand(0) == N->getOperand(1) &&
- N->getOperand(0)->hasNUsesOfValue(2, N->getOperand(0).getResNo()) &&
- N->getOperand(0).isMachineOpcode()) {
- SDValue And = N->getOperand(0);
- unsigned N0Opc = And.getMachineOpcode();
- if ((N0Opc == X86::AND8rr || N0Opc == X86::AND16rr ||
- N0Opc == X86::AND32rr || N0Opc == X86::AND64rr ||
- N0Opc == X86::AND8rr_ND || N0Opc == X86::AND16rr_ND ||
- N0Opc == X86::AND32rr_ND || N0Opc == X86::AND64rr_ND) &&
- !And->hasAnyUseOfValue(1)) {
- MachineSDNode *Test = CurDAG->getMachineNode(Opc, SDLoc(N),
- MVT::i32,
- And.getOperand(0),
- And.getOperand(1));
- ReplaceUses(N, Test);
- MadeChange = true;
+ switch (Opc) {
+ default:
+ continue;
+ // TESTrr+ANDrr/rm -> TESTrr/TESTmr
+ case X86::TEST8rr:
+ case X86::TEST16rr:
+ case X86::TEST32rr:
+ case X86::TEST64rr: {
+ auto &Op0 = N->getOperand(0);
+ if (Op0 != N->getOperand(1) || !Op0->hasNUsesOfValue(2, Op0.getResNo()) ||
+ !Op0.isMachineOpcode())
continue;
- }
- if ((N0Opc == X86::AND8rm || N0Opc == X86::AND16rm ||
- N0Opc == X86::AND32rm || N0Opc == X86::AND64rm ||
- N0Opc == X86::AND8rm_ND || N0Opc == X86::AND16rm_ND ||
- N0Opc == X86::AND32rm_ND || N0Opc == X86::AND64rm_ND) &&
- !And->hasAnyUseOfValue(1)) {
- unsigned NewOpc;
+ SDValue And = N->getOperand(0);
#define CASE_ND(OP) \
case X86::OP: \
case X86::OP##_ND:
+ switch (And.getMachineOpcode()) {
+ default:
+ continue;
+ CASE_ND(AND8rr)
+ CASE_ND(AND16rr)
+ CASE_ND(AND32rr)
+ CASE_ND(AND64rr) {
+ if (And->hasAnyUseOfValue(1))
+ continue;
+ MachineSDNode *Test = CurDAG->getMachineNode(
+ Opc, SDLoc(N), MVT::i32, And.getOperand(0), And.getOperand(1));
+ ReplaceUses(N, Test);
+ MadeChange = true;
+ continue;
+ }
+ CASE_ND(AND8rm)
+ CASE_ND(AND16rm)
+ CASE_ND(AND32rm)
+ CASE_ND(AND64rm) {
+ if (And->hasAnyUseOfValue(1))
+ continue;
+ unsigned NewOpc;
#define FROM_TO(A, B) \
CASE_ND(A) NewOpc = X86::B; \
break;
- switch (N0Opc) {
- FROM_TO(AND8rm, TEST8mr);
- FROM_TO(AND16rm, TEST16mr);
- FROM_TO(AND32rm, TEST32mr);
- FROM_TO(AND64rm, TEST64mr);
- }
+ switch (And.getMachineOpcode()) {
+ FROM_TO(AND8rm, TEST8mr);
+ FROM_TO(AND16rm, TEST16mr);
+ FROM_TO(AND32rm, TEST32mr);
+ FROM_TO(AND64rm, TEST64mr);
+ }
#undef FROM_TO
#undef CASE_ND
-
- // Need to swap the memory and register operand.
- SDValue Ops[] = { And.getOperand(1),
- And.getOperand(2),
- And.getOperand(3),
- And.getOperand(4),
- And.getOperand(5),
- And.getOperand(0),
- And.getOperand(6) /* Chain */ };
- MachineSDNode *Test = CurDAG->getMachineNode(NewOpc, SDLoc(N),
- MVT::i32, MVT::Other, Ops);
- CurDAG->setNodeMemRefs(
- Test, cast<MachineSDNode>(And.getNode())->memoperands());
- ReplaceUses(And.getValue(2), SDValue(Test, 1));
- ReplaceUses(SDValue(N, 0), SDValue(Test, 0));
- MadeChange = true;
- continue;
+ // Need to swap the memory and register operand.
+ SDValue Ops[] = {And.getOperand(1), And.getOperand(2),
+ And.getOperand(3), And.getOperand(4),
+ And.getOperand(5), And.getOperand(0),
+ And.getOperand(6) /* Chain */};
+ MachineSDNode *Test = CurDAG->getMachineNode(
+ NewOpc, SDLoc(N), MVT::i32, MVT::Other, Ops);
+ CurDAG->setNodeMemRefs(
+ Test, cast<MachineSDNode>(And.getNode())->memoperands());
+ ReplaceUses(And.getValue(2), SDValue(Test, 1));
+ ReplaceUses(SDValue(N, 0), SDValue(Test, 0));
+ MadeChange = true;
+ continue;
+ }
}
}
-
// Look for a KAND+KORTEST and turn it into KTEST if only the zero flag is
// used. We're doing this late so we can prefer to fold the AND into masked
// comparisons. Doing that can be better for the live range of the mask
// register.
- if ((Opc == X86::KORTESTBrr || Opc == X86::KORTESTWrr ||
- Opc == X86::KORTESTDrr || Opc == X86::KORTESTQrr) &&
- N->getOperand(0) == N->getOperand(1) &&
- N->isOnlyUserOf(N->getOperand(0).getNode()) &&
- N->getOperand(0).isMachineOpcode() &&
- onlyUsesZeroFlag(SDValue(N, 0))) {
- SDValue And = N->getOperand(0);
- unsigned N0Opc = And.getMachineOpcode();
+ case X86::KORTESTBrr:
+ case X86::KORTESTWrr:
+ case X86::KORTESTDrr:
+ case X86::KORTESTQrr: {
+ SDValue Op0 = N->getOperand(0);
+ if (Op0 != N->getOperand(1) || !N->isOnlyUserOf(Op0.getNode()) ||
+ !Op0.isMachineOpcode() || !onlyUsesZeroFlag(SDValue(N, 0)))
+ continue;
+#define CASE(A) \
+ case X86::A: \
+ break;
+ switch (Op0.getMachineOpcode()) {
+ default:
+ continue;
+ CASE(KANDBrr)
+ CASE(KANDWrr)
+ CASE(KANDDrr)
+ CASE(KANDQrr)
+ }
+ unsigned NewOpc;
+#define FROM_TO(A, B) \
+ case X86::A: \
+ NewOpc = X86::B; \
+ break;
+ switch (Opc) {
+ FROM_TO(KORTESTBrr, KTESTBrr)
+ FROM_TO(KORTESTWrr, KTESTWrr)
+ FROM_TO(KORTESTDrr, KTESTDrr)
+ FROM_TO(KORTESTQrr, KTESTQrr)
+ }
// KANDW is legal with AVX512F, but KTESTW requires AVX512DQ. The other
// KAND instructions and KTEST use the same ISA feature.
- if (N0Opc == X86::KANDBrr ||
- (N0Opc == X86::KANDWrr && Subtarget->hasDQI()) ||
- N0Opc == X86::KANDDrr || N0Opc == X86::KANDQrr) {
- unsigned NewOpc;
- switch (Opc) {
- default: llvm_unreachable("Unexpected opcode!");
- case X86::KORTESTBrr: NewOpc = X86::KTESTBrr; break;
- case X86::KORTESTWrr: NewOpc = X86::KTESTWrr; break;
- case X86::KORTESTDrr: NewOpc = X86::KTESTDrr; break;
- case X86::KORTESTQrr: NewOpc = X86::KTESTQrr; break;
- }
- MachineSDNode *KTest = CurDAG->getMachineNode(NewOpc, SDLoc(N),
- MVT::i32,
- And.getOperand(0),
- And.getOperand(1));
- ReplaceUses(N, KTest);
- MadeChange = true;
+ if (NewOpc == X86::KTESTWrr && !Subtarget->hasDQI())
continue;
- }
+#undef FROM_TO
+ MachineSDNode *KTest = CurDAG->getMachineNode(
+ NewOpc, SDLoc(N), MVT::i32, Op0.getOperand(0), Op0.getOperand(1));
+ ReplaceUses(N, KTest);
+ MadeChange = true;
+ continue;
}
-
// Attempt to remove vectors moves that were inserted to zero upper bits.
- if (Opc != TargetOpcode::SUBREG_TO_REG)
- continue;
-
- unsigned SubRegIdx = N->getConstantOperandVal(2);
- if (SubRegIdx != X86::sub_xmm && SubRegIdx != X86::sub_ymm)
- continue;
+ case TargetOpcode::SUBREG_TO_REG: {
+ unsigned SubRegIdx = N->getConstantOperandVal(2);
+ if (SubRegIdx != X86::sub_xmm && SubRegIdx != X86::sub_ymm)
+ continue;
- SDValue Move = N->getOperand(1);
- if (!Move.isMachineOpcode())
- continue;
+ SDValue Move = N->getOperand(1);
+ if (!Move.isMachineOpcode())
+ continue;
- // Make sure its one of the move opcodes we recognize.
- switch (Move.getMachineOpcode()) {
- default:
- continue;
- case X86::VMOVAPDrr: case X86::VMOVUPDrr:
- case X86::VMOVAPSrr: case X86::VMOVUPSrr:
- case X86::VMOVDQArr: case X86::VMOVDQUrr:
- case X86::VMOVAPDYrr: case X86::VMOVUPDYrr:
- case X86::VMOVAPSYrr: case X86::VMOVUPSYrr:
- case X86::VMOVDQAYrr: case X86::VMOVDQUYrr:
- case X86::VMOVAPDZ128rr: case X86::VMOVUPDZ128rr:
- case X86::VMOVAPSZ128rr: case X86::VMOVUPSZ128rr:
- case X86::VMOVDQA32Z128rr: case X86::VMOVDQU32Z128rr:
- case X86::VMOVDQA64Z128rr: case X86::VMOVDQU64Z128rr:
- case X86::VMOVAPDZ256rr: case X86::VMOVUPDZ256rr:
- case X86::VMOVAPSZ256rr: case X86::VMOVUPSZ256rr:
- case X86::VMOVDQA32Z256rr: case X86::VMOVDQU32Z256rr:
- case X86::VMOVDQA64Z256rr: case X86::VMOVDQU64Z256rr:
- break;
- }
+ // Make sure its one of the move opcodes we recognize.
+ switch (Move.getMachineOpcode()) {
+ default:
+ continue;
+ CASE(VMOVAPDrr) CASE(VMOVUPDrr)
+ CASE(VMOVAPSrr) CASE(VMOVUPSrr)
+ CASE(VMOVDQArr) CASE(VMOVDQUrr)
+ CASE(VMOVAPDYrr) CASE(VMOVUPDYrr)
+ CASE(VMOVAPSYrr) CASE(VMOVUPSYrr)
+ CASE(VMOVDQAYrr) CASE(VMOVDQUYrr)
+ CASE(VMOVAPDZ128rr) CASE(VMOVUPDZ128rr)
+ CASE(VMOVAPSZ128rr) CASE(VMOVUPSZ128rr)
+ CASE(VMOVDQA32Z128rr) CASE(VMOVDQU32Z128rr)
+ CASE(VMOVDQA64Z128rr) CASE(VMOVDQU64Z128rr)
+ CASE(VMOVAPDZ256rr) CASE(VMOVUPDZ256rr)
+ CASE(VMOVAPSZ256rr) CASE(VMOVUPSZ256rr)
+ CASE(VMOVDQA32Z256rr) CASE(VMOVDQU32Z256rr)
+ CASE(VMOVDQA64Z256rr) CASE(VMOVDQU64Z256rr)
+ }
+#undef CASE
SDValue In = Move.getOperand(0);
if (!In.isMachineOpcode() ||
@@ -1697,6 +1708,8 @@ void X86DAGToDAGISel::PostprocessISelDAG() {
// move.
CurDAG->UpdateNodeOperands(N, N->getOperand(0), In, N->getOperand(2));
MadeChange = true;
+ }
+ }
}
if (MadeChange)
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