[llvm] [DAG] SimplifyDemandedBits - use ComputeKnownBits instead of getValidShiftAmountConstant to check for constant shift amounts. (PR #92412)

[Simon Pilgrim via llvm-commits]

================
@@ -3176,7 +3176,8 @@ define <2 x i64> @test_128_i64_x_2_18446744065119617024_mask_ashr_32(<2 x i64> %
 ;
 ; X86-AVX2-LABEL: test_128_i64_x_2_18446744065119617024_mask_ashr_32:
 ; X86-AVX2:       # %bb.0:
-; X86-AVX2-NEXT:    vpand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; X86-AVX2-NEXT:    vpbroadcastd {{.*#+}} xmm1 = [4294967294,4294967294,4294967294,4294967294]
+; X86-AVX2-NEXT:    vpand %xmm1, %xmm0, %xmm0
----------------
RKSimon wrote:

On 32-bit we end up with a 4i32 legalised constant, which SimplifyDemandedBits has removed the even elements as they are undemanded by the v2i64 SRA by 32, allowing us to match as 32-bit broadcasts
```
SelectionDAG has 17 nodes:
  t0: ch,glue = EntryToken
        t2: v2i64,ch = CopyFromReg t0, Register:v2i64 %0
          t21: v4i32 = BUILD_VECTOR undef:i32, Constant:i32<-2>, undef:i32, Constant:i32<-2>
        t19: v2i64 = bitcast t21
      t5: v2i64 = and t2, t19
        t15: v4i32 = BUILD_VECTOR Constant:i32<32>, Constant:i32<0>, Constant:i32<32>, Constant:i32<0>
      t16: v2i64 = bitcast t15
    t8: v2i64 = sra t5, t16
  t11: ch,glue = CopyToReg t0, Register:v2i64 $xmm0, t8
  t12: ch = X86ISD::RET_GLUE t11, TargetConstant:i32<0>, Register:v2i64 $xmm0, t11:1
```
on 64-bit we keep the 2i64 constants which aren't simplified (and AVX2-only targets don't broadcast load v2i64, just v4i64)
```
SelectionDAG has 13 nodes:
  t0: ch,glue = EntryToken
        t2: v2i64,ch = CopyFromReg t0, Register:v2i64 %0
        t4: v2i64 = BUILD_VECTOR Constant:i64<-8589934592>, Constant:i64<-8589934592>
      t5: v2i64 = and t2, t4
      t7: v2i64 = BUILD_VECTOR Constant:i64<32>, Constant:i64<32>
    t8: v2i64 = sra t5, t7
  t11: ch,glue = CopyToReg t0, Register:v2i64 $xmm0, t8
  t12: ch = X86ISD::RET_GLUE t11, TargetConstant:i32<0>, Register:v2i64 $xmm0, t11:1
```
It might be feasible to get X86 targetShrinkDemandedConstant to recognise broadcastable patterns so the <i64 -8589934592> value gets converted into something that matches <i32 -2, i32-2>?

https://github.com/llvm/llvm-project/pull/92412