[llvm] [AMDGPU] Support tfe operand in image_atomic instructions (PR #92469)

[Matt Arsenault via llvm-commits]

arsenm wrote:

> I'm not opposed, but I doubt that some runtimes can properly handle TFE=1. Do we know, e.g. that it is valid for amdgcn-amd-amdhsa?

It's not the job of the assembler to know or care about whether it works, it just needs to emit the encoded instruction 

https://github.com/llvm/llvm-project/pull/92469