[llvm] [WIP][SelectionDAG] Add support for the 3-way comparison intrinsics [US]CMP (PR #91871)
via llvm-commits
llvm-commits at lists.llvm.org
Thu May 16 14:23:35 PDT 2024
https://github.com/Poseydon42 updated https://github.com/llvm/llvm-project/pull/91871
>From 81dfa5432dd76f27fe2a7993f57aa653b530918b Mon Sep 17 00:00:00 2001
From: Poseydon42 <vvmposeydon at gmail.com>
Date: Sat, 11 May 2024 23:33:14 +0100
Subject: [PATCH 1/2] [SelectionDAG] Add support for the 3-way comparison
intrinsics [US]CMP
---
llvm/include/llvm/CodeGen/ISDOpcodes.h | 6 +
llvm/include/llvm/CodeGen/TargetLowering.h | 4 +
.../include/llvm/Target/TargetSelectionDAG.td | 5 +
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 6 +
.../SelectionDAG/LegalizeIntegerTypes.cpp | 41 ++++++
llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h | 5 +
.../SelectionDAG/SelectionDAGBuilder.cpp | 16 +++
.../SelectionDAG/SelectionDAGDumper.cpp | 2 +
.../CodeGen/SelectionDAG/TargetLowering.cpp | 21 +++
llvm/lib/CodeGen/TargetLoweringBase.cpp | 3 +
llvm/test/CodeGen/X86/uscmp.ll | 129 ++++++++++++++++++
11 files changed, 238 insertions(+)
create mode 100644 llvm/test/CodeGen/X86/uscmp.ll
diff --git a/llvm/include/llvm/CodeGen/ISDOpcodes.h b/llvm/include/llvm/CodeGen/ISDOpcodes.h
index 6429947958ee9..7d36f582244b0 100644
--- a/llvm/include/llvm/CodeGen/ISDOpcodes.h
+++ b/llvm/include/llvm/CodeGen/ISDOpcodes.h
@@ -677,6 +677,12 @@ enum NodeType {
UMIN,
UMAX,
+ /// [US]CMP - 3-way comparison of signed or unsigned integers. Returns -1, 0,
+ /// or 1 depending on whether Op0 <, ==, or > Op1. The operands can have type
+ /// different to the result.
+ SCMP,
+ UCMP,
+
/// Bitwise operators - logical and, logical or, logical xor.
AND,
OR,
diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h
index 7ed08cfa8a202..82c450afcbcf6 100644
--- a/llvm/include/llvm/CodeGen/TargetLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetLowering.h
@@ -5402,6 +5402,10 @@ class TargetLowering : public TargetLoweringBase {
/// method accepts integers as its arguments.
SDValue expandAddSubSat(SDNode *Node, SelectionDAG &DAG) const;
+ /// Method for building the DAG expansion of ISD::[US]CMP. This
+ /// method accepts integers as its arguments
+ SDValue expandCMP(SDNode *Node, SelectionDAG &DAG) const;
+
/// Method for building the DAG expansion of ISD::[US]SHLSAT. This
/// method accepts integers as its arguments.
SDValue expandShlSat(SDNode *Node, SelectionDAG &DAG) const;
diff --git a/llvm/include/llvm/Target/TargetSelectionDAG.td b/llvm/include/llvm/Target/TargetSelectionDAG.td
index 1684b424e3b44..6d771521aa739 100644
--- a/llvm/include/llvm/Target/TargetSelectionDAG.td
+++ b/llvm/include/llvm/Target/TargetSelectionDAG.td
@@ -434,6 +434,11 @@ def umin : SDNode<"ISD::UMIN" , SDTIntBinOp,
def umax : SDNode<"ISD::UMAX" , SDTIntBinOp,
[SDNPCommutative, SDNPAssociative]>;
+def scmp : SDNode<"ISD::SCMP" , SDTIntBinOp,
+ []>;
+def ucmp : SDNode<"ISD::UCMP" , SDTIntBinOp,
+ []>;
+
def saddsat : SDNode<"ISD::SADDSAT" , SDTIntBinOp, [SDNPCommutative]>;
def uaddsat : SDNode<"ISD::UADDSAT" , SDTIntBinOp, [SDNPCommutative]>;
def ssubsat : SDNode<"ISD::SSUBSAT" , SDTIntBinOp>;
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index bfc3e08c1632d..f7da195e03bd1 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -1148,6 +1148,8 @@ void SelectionDAGLegalize::LegalizeOp(SDNode *Node) {
case ISD::USUBSAT:
case ISD::SSHLSAT:
case ISD::USHLSAT:
+ case ISD::SCMP:
+ case ISD::UCMP:
case ISD::FP_TO_SINT_SAT:
case ISD::FP_TO_UINT_SAT:
Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
@@ -3864,6 +3866,10 @@ bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
case ISD::USUBSAT:
Results.push_back(TLI.expandAddSubSat(Node, DAG));
break;
+ case ISD::SCMP:
+ case ISD::UCMP:
+ Results.push_back(TLI.expandCMP(Node, DAG));
+ break;
case ISD::SSHLSAT:
case ISD::USHLSAT:
Results.push_back(TLI.expandShlSat(Node, DAG));
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
index 0aa36deda79dc..e82ab9db4c090 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -232,6 +232,11 @@ void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
Res = PromoteIntRes_ADDSUBSHLSAT<VPMatchContext>(N);
break;
+ case ISD::SCMP:
+ case ISD::UCMP:
+ Res = PromoteIntRes_CMP(N);
+ break;
+
case ISD::SMULFIX:
case ISD::SMULFIXSAT:
case ISD::UMULFIX:
@@ -1246,6 +1251,13 @@ SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo) {
return Res;
}
+SDValue DAGTypeLegalizer::PromoteIntRes_CMP(SDNode *N) {
+ EVT PromotedResultTy =
+ TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
+ return DAG.getNode(N->getOpcode(), SDLoc(N), PromotedResultTy,
+ N->getOperand(0), N->getOperand(1));
+}
+
SDValue DAGTypeLegalizer::PromoteIntRes_Select(SDNode *N) {
SDValue Mask = N->getOperand(0);
@@ -1874,6 +1886,9 @@ bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
case ISD::ROTL:
case ISD::ROTR: Res = PromoteIntOp_Shift(N); break;
+ case ISD::SCMP:
+ case ISD::UCMP: Res = PromoteIntOp_CMP(N); break;
+
case ISD::FSHL:
case ISD::FSHR: Res = PromoteIntOp_FunnelShift(N); break;
@@ -2184,6 +2199,17 @@ SDValue DAGTypeLegalizer::PromoteIntOp_Shift(SDNode *N) {
ZExtPromotedInteger(N->getOperand(1))), 0);
}
+SDValue DAGTypeLegalizer::PromoteIntOp_CMP(SDNode *N) {
+ SDValue LHS = N->getOpcode() == ISD::UCMP
+ ? ZExtPromotedInteger(N->getOperand(0))
+ : SExtPromotedInteger(N->getOperand(0));
+ SDValue RHS = N->getOpcode() == ISD::UCMP
+ ? ZExtPromotedInteger(N->getOperand(1))
+ : SExtPromotedInteger(N->getOperand(1));
+
+ return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS), 0);
+}
+
SDValue DAGTypeLegalizer::PromoteIntOp_FunnelShift(SDNode *N) {
return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), N->getOperand(1),
ZExtPromotedInteger(N->getOperand(2))), 0);
@@ -2741,6 +2767,9 @@ void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) {
case ISD::UMIN:
case ISD::SMIN: ExpandIntRes_MINMAX(N, Lo, Hi); break;
+ case ISD::SCMP:
+ case ISD::UCMP: ExpandIntRes_CMP(N, Lo, Hi); break;
+
case ISD::ADD:
case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break;
@@ -3233,6 +3262,11 @@ void DAGTypeLegalizer::ExpandIntRes_MINMAX(SDNode *N,
SplitInteger(Result, Lo, Hi);
}
+void DAGTypeLegalizer::ExpandIntRes_CMP(SDNode *N, SDValue &Lo, SDValue &Hi) {
+ SDValue ExpandedCMP = TLI.expandCMP(N, DAG);
+ SplitInteger(ExpandedCMP, Lo, Hi);
+}
+
void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
SDValue &Lo, SDValue &Hi) {
SDLoc dl(N);
@@ -5137,6 +5171,9 @@ bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) {
case ISD::RETURNADDR:
case ISD::FRAMEADDR: Res = ExpandIntOp_RETURNADDR(N); break;
+ case ISD::SCMP:
+ case ISD::UCMP: Res = ExpandIntOp_CMP(N); break;
+
case ISD::ATOMIC_STORE: Res = ExpandIntOp_ATOMIC_STORE(N); break;
case ISD::STACKMAP:
Res = ExpandIntOp_STACKMAP(N, OpNo);
@@ -5398,6 +5435,10 @@ SDValue DAGTypeLegalizer::ExpandIntOp_Shift(SDNode *N) {
return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Lo), 0);
}
+SDValue DAGTypeLegalizer::ExpandIntOp_CMP(SDNode *N) {
+ return TLI.expandCMP(N, DAG);
+}
+
SDValue DAGTypeLegalizer::ExpandIntOp_RETURNADDR(SDNode *N) {
// The argument of RETURNADDR / FRAMEADDR builtin is 32 bit contant. This
// surely makes pretty nice problems on 8/16 bit targets. Just truncate this
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
index 4b06e19656ce6..035f16720c3f6 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
@@ -324,6 +324,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
SDValue PromoteIntRes_Overflow(SDNode *N);
SDValue PromoteIntRes_FFREXP(SDNode *N);
SDValue PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo);
+ SDValue PromoteIntRes_CMP(SDNode *N);
SDValue PromoteIntRes_Select(SDNode *N);
SDValue PromoteIntRes_SELECT_CC(SDNode *N);
SDValue PromoteIntRes_SETCC(SDNode *N);
@@ -375,6 +376,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
SDValue PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo);
SDValue PromoteIntOp_SETCC(SDNode *N, unsigned OpNo);
SDValue PromoteIntOp_Shift(SDNode *N);
+ SDValue PromoteIntOp_CMP(SDNode *N);
SDValue PromoteIntOp_FunnelShift(SDNode *N);
SDValue PromoteIntOp_SIGN_EXTEND(SDNode *N);
SDValue PromoteIntOp_VP_SIGN_EXTEND(SDNode *N);
@@ -457,6 +459,8 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
void ExpandIntRes_MINMAX (SDNode *N, SDValue &Lo, SDValue &Hi);
+ void ExpandIntRes_CMP (SDNode *N, SDValue &Lo, SDValue &Hi);
+
void ExpandIntRes_SADDSUBO (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandIntRes_UADDSUBO (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandIntRes_XMULO (SDNode *N, SDValue &Lo, SDValue &Hi);
@@ -485,6 +489,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
SDValue ExpandIntOp_SETCC(SDNode *N);
SDValue ExpandIntOp_SETCCCARRY(SDNode *N);
SDValue ExpandIntOp_Shift(SDNode *N);
+ SDValue ExpandIntOp_CMP(SDNode *N);
SDValue ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo);
SDValue ExpandIntOp_TRUNCATE(SDNode *N);
SDValue ExpandIntOp_XINT_TO_FP(SDNode *N);
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index cfd82a342433f..16d8a9816b013 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -7143,6 +7143,22 @@ void SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I,
setValue(&I, DAG.getNode(ISD::ABS, sdl, Op1.getValueType(), Op1));
return;
}
+ case Intrinsic::scmp: {
+ SDValue Op1 = getValue(I.getArgOperand(0));
+ SDValue Op2 = getValue(I.getArgOperand(1));
+ EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
+ I.getType());
+ setValue(&I, DAG.getNode(ISD::SCMP, sdl, DestVT, Op1, Op2));
+ break;
+ }
+ case Intrinsic::ucmp: {
+ SDValue Op1 = getValue(I.getArgOperand(0));
+ SDValue Op2 = getValue(I.getArgOperand(1));
+ EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
+ I.getType());
+ setValue(&I, DAG.getNode(ISD::UCMP, sdl, DestVT, Op1, Op2));
+ break;
+ }
case Intrinsic::stacksave: {
SDValue Op = getRoot();
EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
index 4ad4a938ca97f..d5e8256aa4085 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
@@ -289,6 +289,8 @@ std::string SDNode::getOperationName(const SelectionDAG *G) const {
case ISD::SMAX: return "smax";
case ISD::UMIN: return "umin";
case ISD::UMAX: return "umax";
+ case ISD::SCMP: return "scmp";
+ case ISD::UCMP: return "ucmp";
case ISD::FLDEXP: return "fldexp";
case ISD::STRICT_FLDEXP: return "strict_fldexp";
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 336d89fbcf638..3de57001135e9 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -10274,6 +10274,27 @@ SDValue TargetLowering::expandAddSubSat(SDNode *Node, SelectionDAG &DAG) const {
return DAG.getSelect(dl, VT, Overflow, Result, SumDiff);
}
+SDValue TargetLowering::expandCMP(SDNode *Node, SelectionDAG &DAG) const {
+ unsigned Opcode = Node->getOpcode();
+ SDValue LHS = Node->getOperand(0);
+ SDValue RHS = Node->getOperand(1);
+ EVT VT = LHS.getValueType();
+ EVT ResVT = Node->getValueType(0);
+ EVT BoolVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
+ SDLoc dl(Node);
+
+ auto LTPredicate = (Opcode == ISD::UCMP ? ISD::SETULT : ISD::SETLT);
+ auto GTPredicate = (Opcode == ISD::UCMP ? ISD::SETUGT : ISD::SETGT);
+
+ SDValue IsLT = DAG.getSetCC(dl, BoolVT, LHS, RHS, LTPredicate);
+ SDValue IsGT = DAG.getSetCC(dl, BoolVT, LHS, RHS, GTPredicate);
+ SDValue SelectZeroOrOne =
+ DAG.getSelect(dl, ResVT, IsGT, DAG.getConstant(1, dl, ResVT),
+ DAG.getConstant(0, dl, ResVT));
+ return DAG.getSelect(dl, ResVT, IsLT, DAG.getConstant(-1, dl, ResVT),
+ SelectZeroOrOne);
+}
+
SDValue TargetLowering::expandShlSat(SDNode *Node, SelectionDAG &DAG) const {
unsigned Opcode = Node->getOpcode();
bool IsSigned = Opcode == ISD::SSHLSAT;
diff --git a/llvm/lib/CodeGen/TargetLoweringBase.cpp b/llvm/lib/CodeGen/TargetLoweringBase.cpp
index 6e7b67ded23c8..311ba68b96ec9 100644
--- a/llvm/lib/CodeGen/TargetLoweringBase.cpp
+++ b/llvm/lib/CodeGen/TargetLoweringBase.cpp
@@ -909,6 +909,9 @@ void TargetLoweringBase::initActions() {
setOperationAction({ISD::ADDC, ISD::ADDE, ISD::SUBC, ISD::SUBE}, VT,
Expand);
+ // [US]CMP default to expand
+ setOperationAction({ISD::UCMP, ISD::SCMP}, VT, Expand);
+
// Halving adds
setOperationAction(
{ISD::AVGFLOORS, ISD::AVGFLOORU, ISD::AVGCEILS, ISD::AVGCEILU}, VT,
diff --git a/llvm/test/CodeGen/X86/uscmp.ll b/llvm/test/CodeGen/X86/uscmp.ll
new file mode 100644
index 0000000000000..3d1765b94f72a
--- /dev/null
+++ b/llvm/test/CodeGen/X86/uscmp.ll
@@ -0,0 +1,129 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
+
+define i8 @ucmp(i32 %x, i32 %y) {
+; CHECK-LABEL: ucmp:
+; CHECK: # %bb.0:
+; CHECK-NEXT: xorl %ecx, %ecx
+; CHECK-NEXT: cmpl %esi, %edi
+; CHECK-NEXT: seta %cl
+; CHECK-NEXT: movl $255, %eax
+; CHECK-NEXT: cmovael %ecx, %eax
+; CHECK-NEXT: # kill: def $al killed $al killed $eax
+; CHECK-NEXT: retq
+ %1 = call i8 @llvm.ucmp(i32 %x, i32 %y)
+ ret i8 %1
+}
+
+define i8 @scmp(i32 %x, i32 %y) {
+; CHECK-LABEL: scmp:
+; CHECK: # %bb.0:
+; CHECK-NEXT: xorl %ecx, %ecx
+; CHECK-NEXT: cmpl %esi, %edi
+; CHECK-NEXT: seta %cl
+; CHECK-NEXT: movl $255, %eax
+; CHECK-NEXT: cmovael %ecx, %eax
+; CHECK-NEXT: # kill: def $al killed $al killed $eax
+; CHECK-NEXT: retq
+ %1 = call i8 @llvm.ucmp(i32 %x, i32 %y)
+ ret i8 %1
+}
+
+define i4 @ucmp_narrow_result(i32 %x, i32 %y) {
+; CHECK-LABEL: ucmp_narrow_result:
+; CHECK: # %bb.0:
+; CHECK-NEXT: xorl %ecx, %ecx
+; CHECK-NEXT: cmpl %esi, %edi
+; CHECK-NEXT: seta %cl
+; CHECK-NEXT: movl $255, %eax
+; CHECK-NEXT: cmovael %ecx, %eax
+; CHECK-NEXT: # kill: def $al killed $al killed $eax
+; CHECK-NEXT: retq
+ %1 = call i4 @llvm.ucmp(i32 %x, i32 %y)
+ ret i4 %1
+}
+
+define i8 @scmp_narrow_op(i5 %x, i5 %y) {
+; CHECK-LABEL: scmp_narrow_op:
+; CHECK: # %bb.0:
+; CHECK-NEXT: andb $31, %sil
+; CHECK-NEXT: andb $31, %dil
+; CHECK-NEXT: xorl %ecx, %ecx
+; CHECK-NEXT: cmpb %sil, %dil
+; CHECK-NEXT: seta %cl
+; CHECK-NEXT: movl $255, %eax
+; CHECK-NEXT: cmovael %ecx, %eax
+; CHECK-NEXT: # kill: def $al killed $al killed $eax
+; CHECK-NEXT: retq
+ %1 = call i8 @llvm.ucmp(i5 %x, i5 %y)
+ ret i8 %1
+}
+
+define i128 @ucmp_wide_result(i32 %x, i32 %y) {
+; CHECK-LABEL: ucmp_wide_result:
+; CHECK: # %bb.0:
+; CHECK-NEXT: xorl %ecx, %ecx
+; CHECK-NEXT: cmpl %esi, %edi
+; CHECK-NEXT: seta %cl
+; CHECK-NEXT: movq $-1, %rax
+; CHECK-NEXT: cmovaeq %rcx, %rax
+; CHECK-NEXT: xorl %edx, %edx
+; CHECK-NEXT: retq
+ %1 = call i128 @llvm.ucmp(i32 %x, i32 %y)
+ ret i128 %1
+}
+
+define i8 @scmp_wide_op(i128 %x, i128 %y) {
+; CHECK-LABEL: scmp_wide_op:
+; CHECK: # %bb.0:
+; CHECK-NEXT: cmpq %rdi, %rdx
+; CHECK-NEXT: movq %rcx, %rax
+; CHECK-NEXT: sbbq %rsi, %rax
+; CHECK-NEXT: setl %al
+; CHECK-NEXT: movzbl %al, %r8d
+; CHECK-NEXT: cmpq %rdx, %rdi
+; CHECK-NEXT: sbbq %rcx, %rsi
+; CHECK-NEXT: movl $255, %eax
+; CHECK-NEXT: cmovgel %r8d, %eax
+; CHECK-NEXT: # kill: def $al killed $al killed $eax
+; CHECK-NEXT: retq
+ %1 = call i8 @llvm.scmp(i128 %x, i128 %y)
+ ret i8 %1
+}
+
+define i41 @ucmp_uncommon_types(i7 %x, i7 %y) {
+; CHECK-LABEL: ucmp_uncommon_types:
+; CHECK: # %bb.0:
+; CHECK-NEXT: andb $127, %sil
+; CHECK-NEXT: andb $127, %dil
+; CHECK-NEXT: xorl %ecx, %ecx
+; CHECK-NEXT: cmpb %sil, %dil
+; CHECK-NEXT: seta %cl
+; CHECK-NEXT: movq $-1, %rax
+; CHECK-NEXT: cmovaeq %rcx, %rax
+; CHECK-NEXT: retq
+ %1 = call i41 @llvm.ucmp(i7 %x, i7 %y)
+ ret i41 %1
+}
+
+define i125 @scmp_uncommon_types(i99 %x, i99 %y) {
+; CHECK-LABEL: scmp_uncommon_types:
+; CHECK: # %bb.0:
+; CHECK-NEXT: shlq $29, %rsi
+; CHECK-NEXT: sarq $29, %rsi
+; CHECK-NEXT: shlq $29, %rcx
+; CHECK-NEXT: sarq $29, %rcx
+; CHECK-NEXT: cmpq %rdi, %rdx
+; CHECK-NEXT: movq %rcx, %rax
+; CHECK-NEXT: sbbq %rsi, %rax
+; CHECK-NEXT: setl %al
+; CHECK-NEXT: movzbl %al, %r8d
+; CHECK-NEXT: cmpq %rdx, %rdi
+; CHECK-NEXT: sbbq %rcx, %rsi
+; CHECK-NEXT: movq $-1, %rax
+; CHECK-NEXT: cmovgeq %r8, %rax
+; CHECK-NEXT: xorl %edx, %edx
+; CHECK-NEXT: retq
+ %1 = call i125 @llvm.scmp(i99 %x, i99 %y)
+ ret i125 %1
+}
>From 5c5e9ccf461059c5bc78e07433a504ef8bcac518 Mon Sep 17 00:00:00 2001
From: Poseydon42 <vvmposeydon at gmail.com>
Date: Thu, 16 May 2024 22:22:44 +0100
Subject: [PATCH 2/2] [SelectionDAG] Properly handle legalization of vector
types for [US]CMP nodes
---
llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h | 5 +
.../SelectionDAG/LegalizeVectorTypes.cpp | 135 +++++++
llvm/test/CodeGen/X86/uscmp.ll | 369 ++++++++++++++++++
3 files changed, 509 insertions(+)
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
index 035f16720c3f6..74ab2f44149fa 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
@@ -784,6 +784,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
void ScalarizeVectorResult(SDNode *N, unsigned ResNo);
SDValue ScalarizeVecRes_MERGE_VALUES(SDNode *N, unsigned ResNo);
SDValue ScalarizeVecRes_BinOp(SDNode *N);
+ SDValue ScalarizeVecRes_CMP(SDNode *N);
SDValue ScalarizeVecRes_TernaryOp(SDNode *N);
SDValue ScalarizeVecRes_UnaryOp(SDNode *N);
SDValue ScalarizeVecRes_StrictFPOp(SDNode *N);
@@ -857,6 +858,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
void SplitVectorResult(SDNode *N, unsigned ResNo);
void SplitVecRes_BinOp(SDNode *N, SDValue &Lo, SDValue &Hi);
void SplitVecRes_TernaryOp(SDNode *N, SDValue &Lo, SDValue &Hi);
+ void SplitVecRes_CMP(SDNode *N, SDValue &Lo, SDValue &Hi);
void SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo, SDValue &Hi);
void SplitVecRes_FFREXP(SDNode *N, unsigned ResNo, SDValue &Lo, SDValue &Hi);
void SplitVecRes_ExtendOp(SDNode *N, SDValue &Lo, SDValue &Hi);
@@ -920,6 +922,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
SDValue SplitVecOp_VSETCC(SDNode *N);
SDValue SplitVecOp_FP_ROUND(SDNode *N);
SDValue SplitVecOp_FPOpDifferentTypes(SDNode *N);
+ SDValue SplitVecOp_CMP(SDNode *N);
SDValue SplitVecOp_FP_TO_XINT_SAT(SDNode *N);
SDValue SplitVecOp_VP_CttzElements(SDNode *N);
@@ -987,6 +990,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
SDValue WidenVecRes_Ternary(SDNode *N);
SDValue WidenVecRes_Binary(SDNode *N);
+ SDValue WidenVecRes_CMP(SDNode *N);
SDValue WidenVecRes_BinaryCanTrap(SDNode *N);
SDValue WidenVecRes_BinaryWithExtraScalarOp(SDNode *N);
SDValue WidenVecRes_StrictFP(SDNode *N);
@@ -1006,6 +1010,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
SDValue WidenVecOp_BITCAST(SDNode *N);
SDValue WidenVecOp_CONCAT_VECTORS(SDNode *N);
SDValue WidenVecOp_EXTEND(SDNode *N);
+ SDValue WidenVecOp_CMP(SDNode *N);
SDValue WidenVecOp_EXTRACT_VECTOR_ELT(SDNode *N);
SDValue WidenVecOp_INSERT_SUBVECTOR(SDNode *N);
SDValue WidenVecOp_EXTRACT_SUBVECTOR(SDNode *N);
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
index cab4dc5f3c156..114b3e8ee6de4 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -164,6 +164,12 @@ void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
case ISD::ROTR:
R = ScalarizeVecRes_BinOp(N);
break;
+
+ case ISD::SCMP:
+ case ISD::UCMP:
+ R = ScalarizeVecRes_CMP(N);
+ break;
+
case ISD::FMA:
case ISD::FSHL:
case ISD::FSHR:
@@ -213,6 +219,13 @@ SDValue DAGTypeLegalizer::ScalarizeVecRes_BinOp(SDNode *N) {
LHS.getValueType(), LHS, RHS, N->getFlags());
}
+SDValue DAGTypeLegalizer::ScalarizeVecRes_CMP(SDNode *N) {
+ SDValue LHS = GetScalarizedVector(N->getOperand(0));
+ SDValue RHS = GetScalarizedVector(N->getOperand(1));
+ return DAG.getNode(N->getOpcode(), SDLoc(N),
+ N->getValueType(0).getVectorElementType(), LHS, RHS);
+}
+
SDValue DAGTypeLegalizer::ScalarizeVecRes_TernaryOp(SDNode *N) {
SDValue Op0 = GetScalarizedVector(N->getOperand(0));
SDValue Op1 = GetScalarizedVector(N->getOperand(1));
@@ -1184,6 +1197,10 @@ void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
SplitVecRes_TernaryOp(N, Lo, Hi);
break;
+ case ISD::SCMP: case ISD::UCMP:
+ SplitVecRes_CMP(N, Lo, Hi);
+ break;
+
#define DAG_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) \
case ISD::STRICT_##DAGN:
#include "llvm/IR/ConstrainedOps.def"
@@ -1327,6 +1344,31 @@ void DAGTypeLegalizer::SplitVecRes_TernaryOp(SDNode *N, SDValue &Lo,
{Op0Hi, Op1Hi, Op2Hi, MaskHi, EVLHi}, Flags);
}
+void DAGTypeLegalizer::SplitVecRes_CMP(SDNode *N, SDValue &Lo, SDValue &Hi) {
+ LLVMContext &Ctxt = *DAG.getContext();
+ SDLoc dl(N);
+
+ SDValue LHS = N->getOperand(0);
+ SDValue RHS = N->getOperand(1);
+ EVT SplitOpVT = LHS.getValueType().getHalfNumVectorElementsVT(Ctxt);
+ EVT SplitResVT = N->getValueType(0).getHalfNumVectorElementsVT(Ctxt);
+
+ SDValue LHSLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SplitOpVT, LHS,
+ DAG.getVectorIdxConstant(0, dl));
+ SDValue LHSHi = DAG.getNode(
+ ISD::EXTRACT_SUBVECTOR, dl, SplitOpVT, LHS,
+ DAG.getVectorIdxConstant(SplitOpVT.getVectorNumElements(), dl));
+
+ SDValue RHSLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SplitOpVT, RHS,
+ DAG.getVectorIdxConstant(0, dl));
+ SDValue RHSHi = DAG.getNode(
+ ISD::EXTRACT_SUBVECTOR, dl, SplitOpVT, RHS,
+ DAG.getVectorIdxConstant(SplitOpVT.getVectorNumElements(), dl));
+
+ Lo = DAG.getNode(N->getOpcode(), dl, SplitResVT, LHSLo, RHSLo);
+ Hi = DAG.getNode(N->getOpcode(), dl, SplitResVT, LHSHi, RHSHi);
+}
+
void DAGTypeLegalizer::SplitVecRes_FIX(SDNode *N, SDValue &Lo, SDValue &Hi) {
SDValue LHSLo, LHSHi;
GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
@@ -3054,6 +3096,11 @@ bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) {
Res = SplitVecOp_FPOpDifferentTypes(N);
break;
+ case ISD::SCMP:
+ case ISD::UCMP:
+ Res = SplitVecOp_CMP(N);
+ break;
+
case ISD::ANY_EXTEND_VECTOR_INREG:
case ISD::SIGN_EXTEND_VECTOR_INREG:
case ISD::ZERO_EXTEND_VECTOR_INREG:
@@ -4043,6 +4090,25 @@ SDValue DAGTypeLegalizer::SplitVecOp_FPOpDifferentTypes(SDNode *N) {
return DAG.getNode(ISD::CONCAT_VECTORS, DL, N->getValueType(0), Lo, Hi);
}
+SDValue DAGTypeLegalizer::SplitVecOp_CMP(SDNode *N) {
+ LLVMContext &Ctxt = *DAG.getContext();
+ SDLoc dl(N);
+
+ SDValue LHSLo, LHSHi, RHSLo, RHSHi;
+ GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
+ GetSplitVector(N->getOperand(1), RHSLo, RHSHi);
+
+ EVT ResVT = N->getValueType(0);
+ ElementCount SplitOpEC = LHSLo.getValueType().getVectorElementCount();
+ EVT NewResVT =
+ EVT::getVectorVT(Ctxt, ResVT.getVectorElementType(), SplitOpEC);
+
+ SDValue Lo = DAG.getNode(N->getOpcode(), dl, NewResVT, LHSLo, RHSLo);
+ SDValue Hi = DAG.getNode(N->getOpcode(), dl, NewResVT, LHSHi, RHSHi);
+
+ return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
+}
+
SDValue DAGTypeLegalizer::SplitVecOp_FP_TO_XINT_SAT(SDNode *N) {
EVT ResVT = N->getValueType(0);
SDValue Lo, Hi;
@@ -4220,6 +4286,11 @@ void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {
Res = WidenVecRes_Binary(N);
break;
+ case ISD::SCMP:
+ case ISD::UCMP:
+ Res = WidenVecRes_CMP(N);
+ break;
+
case ISD::FPOW:
case ISD::FREM:
if (unrollExpandedOp())
@@ -4426,6 +4497,39 @@ SDValue DAGTypeLegalizer::WidenVecRes_Binary(SDNode *N) {
{InOp1, InOp2, Mask, N->getOperand(3)}, N->getFlags());
}
+SDValue DAGTypeLegalizer::WidenVecRes_CMP(SDNode *N) {
+ LLVMContext &Ctxt = *DAG.getContext();
+ SDLoc dl(N);
+
+ SDValue LHS = N->getOperand(0);
+ SDValue RHS = N->getOperand(1);
+ EVT OpVT = LHS.getValueType();
+ EVT OpElementVT = OpVT.getVectorElementType();
+ EVT TransformedOpVT = TLI.getTypeToTransformTo(Ctxt, OpVT);
+ if (TransformedOpVT.getVectorNumElements() > OpVT.getVectorNumElements()) {
+ LHS = GetWidenedVector(LHS);
+ RHS = GetWidenedVector(RHS);
+ }
+
+ EVT WidenResVT = TLI.getTypeToTransformTo(Ctxt, N->getValueType(0));
+ ElementCount WidenResEC = WidenResVT.getVectorElementCount();
+ EVT WidenResElementVT = WidenResVT.getVectorElementType();
+
+ assert(OpElementVT.getSizeInBits() >= WidenResElementVT.getSizeInBits() &&
+ "Element size of operands should be at least as wide as of the output "
+ "if widening is needed");
+
+ SDValue CMP = DAG.getNode(N->getOpcode(), dl, LHS.getValueType(), LHS, RHS);
+
+ EVT WideUndefVectorVT = EVT::getVectorVT(Ctxt, OpElementVT, WidenResEC);
+ SDValue WideUndefValue = DAG.getUNDEF(WideUndefVectorVT);
+
+ SDValue WideResult =
+ DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideUndefVectorVT, WideUndefValue,
+ CMP, DAG.getVectorIdxConstant(0, dl));
+ return DAG.getNode(ISD::TRUNCATE, dl, WidenResVT, WideResult);
+}
+
SDValue DAGTypeLegalizer::WidenVecRes_BinaryWithExtraScalarOp(SDNode *N) {
// Binary op widening, but with an extra operand that shouldn't be widened.
SDLoc dl(N);
@@ -6129,6 +6233,11 @@ bool DAGTypeLegalizer::WidenVectorOperand(SDNode *N, unsigned OpNo) {
Res = WidenVecOp_EXTEND(N);
break;
+ case ISD::SCMP:
+ case ISD::UCMP:
+ Res = WidenVecOp_CMP(N);
+ break;
+
case ISD::FP_EXTEND:
case ISD::STRICT_FP_EXTEND:
case ISD::FP_ROUND:
@@ -6273,6 +6382,32 @@ SDValue DAGTypeLegalizer::WidenVecOp_EXTEND(SDNode *N) {
}
}
+SDValue DAGTypeLegalizer::WidenVecOp_CMP(SDNode *N) {
+ SDLoc dl(N);
+
+ EVT OpVT = N->getOperand(0).getValueType();
+ EVT ResVT = N->getValueType(0);
+ SDValue LHS = GetWidenedVector(N->getOperand(0));
+ SDValue RHS = GetWidenedVector(N->getOperand(1));
+
+ // 1. EXTRACT_SUBVECTOR
+ // 2. SIGN_EXTEND/ZERO_EXTEND
+ // 3. CMP
+ LHS = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OpVT, LHS,
+ DAG.getVectorIdxConstant(0, dl));
+ RHS = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OpVT, RHS,
+ DAG.getVectorIdxConstant(0, dl));
+
+ // At this point the result type is guaranteed to be valid, so we can use it
+ // as the operand type by extending it appropriately
+ ISD::NodeType ExtendOpcode =
+ N->getOpcode() == ISD::SCMP ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
+ LHS = DAG.getNode(ExtendOpcode, dl, ResVT, LHS);
+ RHS = DAG.getNode(ExtendOpcode, dl, ResVT, RHS);
+
+ return DAG.getNode(N->getOpcode(), dl, ResVT, LHS, RHS);
+}
+
SDValue DAGTypeLegalizer::WidenVecOp_UnrollVectorOp(SDNode *N) {
// The result (and first input) is legal, but the second input is illegal.
// We can't do much to fix that, so just unroll and let the extracts off of
diff --git a/llvm/test/CodeGen/X86/uscmp.ll b/llvm/test/CodeGen/X86/uscmp.ll
index 3d1765b94f72a..016073ed6b6bd 100644
--- a/llvm/test/CodeGen/X86/uscmp.ll
+++ b/llvm/test/CodeGen/X86/uscmp.ll
@@ -127,3 +127,372 @@ define i125 @scmp_uncommon_types(i99 %x, i99 %y) {
%1 = call i125 @llvm.scmp(i99 %x, i99 %y)
ret i125 %1
}
+
+define <4 x i32> @ucmp_normal_vectors(<4 x i32> %x, <4 x i32> %y) {
+; CHECK-LABEL: ucmp_normal_vectors:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648]
+; CHECK-NEXT: pxor %xmm2, %xmm0
+; CHECK-NEXT: pxor %xmm2, %xmm1
+; CHECK-NEXT: movdqa %xmm1, %xmm2
+; CHECK-NEXT: pcmpgtd %xmm0, %xmm2
+; CHECK-NEXT: pcmpgtd %xmm1, %xmm0
+; CHECK-NEXT: psrld $31, %xmm0
+; CHECK-NEXT: por %xmm2, %xmm0
+; CHECK-NEXT: retq
+ %1 = call <4 x i32> @llvm.ucmp(<4 x i32> %x, <4 x i32> %y)
+ ret <4 x i32> %1
+}
+
+define <4 x i8> @scmp_narrow_result(<4 x i32> %x, <4 x i32> %y) {
+; CHECK-LABEL: scmp_narrow_result:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movdqa %xmm1, %xmm2
+; CHECK-NEXT: pcmpgtd %xmm0, %xmm2
+; CHECK-NEXT: pcmpgtd %xmm1, %xmm0
+; CHECK-NEXT: psrld $31, %xmm0
+; CHECK-NEXT: por %xmm2, %xmm0
+; CHECK-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: pxor %xmm1, %xmm1
+; CHECK-NEXT: packuswb %xmm1, %xmm0
+; CHECK-NEXT: packuswb %xmm1, %xmm0
+; CHECK-NEXT: retq
+ %1 = call <4 x i8> @llvm.scmp(<4 x i32> %x, <4 x i32> %y)
+ ret <4 x i8> %1
+}
+
+define <4 x i32> @ucmp_narrow_op(<4 x i8> %x, <4 x i8> %y) {
+; CHECK-LABEL: ucmp_narrow_op:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pxor %xmm2, %xmm2
+; CHECK-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3],xmm0[4],xmm2[4],xmm0[5],xmm2[5],xmm0[6],xmm2[6],xmm0[7],xmm2[7]
+; CHECK-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3]
+; CHECK-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3],xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]
+; CHECK-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3]
+; CHECK-NEXT: movdqa %xmm1, %xmm2
+; CHECK-NEXT: pcmpgtd %xmm0, %xmm2
+; CHECK-NEXT: pcmpgtd %xmm1, %xmm0
+; CHECK-NEXT: psrld $31, %xmm0
+; CHECK-NEXT: por %xmm2, %xmm0
+; CHECK-NEXT: retq
+ %1 = call <4 x i32> @llvm.ucmp(<4 x i8> %x, <4 x i8> %y)
+ ret <4 x i32> %1
+}
+
+define <16 x i32> @scmp_wide_res(<16 x i8> %x, <16 x i8> %y) {
+; CHECK-LABEL: scmp_wide_res:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movdqa %xmm1, %xmm4
+; CHECK-NEXT: movdqa %xmm0, %xmm3
+; CHECK-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
+; CHECK-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
+; CHECK-NEXT: psrad $24, %xmm0
+; CHECK-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm4[0],xmm2[1],xmm4[1],xmm2[2],xmm4[2],xmm2[3],xmm4[3],xmm2[4],xmm4[4],xmm2[5],xmm4[5],xmm2[6],xmm4[6],xmm2[7],xmm4[7]
+; CHECK-NEXT: punpcklwd {{.*#+}} xmm5 = xmm5[0],xmm2[0],xmm5[1],xmm2[1],xmm5[2],xmm2[2],xmm5[3],xmm2[3]
+; CHECK-NEXT: psrad $24, %xmm5
+; CHECK-NEXT: movdqa %xmm5, %xmm6
+; CHECK-NEXT: pcmpgtd %xmm0, %xmm6
+; CHECK-NEXT: pcmpgtd %xmm5, %xmm0
+; CHECK-NEXT: psrld $31, %xmm0
+; CHECK-NEXT: por %xmm6, %xmm0
+; CHECK-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4,4,5,5,6,6,7,7]
+; CHECK-NEXT: psrad $24, %xmm1
+; CHECK-NEXT: punpckhwd {{.*#+}} xmm2 = xmm2[4,4,5,5,6,6,7,7]
+; CHECK-NEXT: psrad $24, %xmm2
+; CHECK-NEXT: movdqa %xmm2, %xmm5
+; CHECK-NEXT: pcmpgtd %xmm1, %xmm5
+; CHECK-NEXT: pcmpgtd %xmm2, %xmm1
+; CHECK-NEXT: psrld $31, %xmm1
+; CHECK-NEXT: por %xmm5, %xmm1
+; CHECK-NEXT: punpckhbw {{.*#+}} xmm3 = xmm3[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
+; CHECK-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1],xmm2[2],xmm3[2],xmm2[3],xmm3[3]
+; CHECK-NEXT: psrad $24, %xmm2
+; CHECK-NEXT: punpckhbw {{.*#+}} xmm4 = xmm4[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
+; CHECK-NEXT: punpcklwd {{.*#+}} xmm5 = xmm5[0],xmm4[0],xmm5[1],xmm4[1],xmm5[2],xmm4[2],xmm5[3],xmm4[3]
+; CHECK-NEXT: psrad $24, %xmm5
+; CHECK-NEXT: movdqa %xmm5, %xmm6
+; CHECK-NEXT: pcmpgtd %xmm2, %xmm6
+; CHECK-NEXT: pcmpgtd %xmm5, %xmm2
+; CHECK-NEXT: psrld $31, %xmm2
+; CHECK-NEXT: por %xmm6, %xmm2
+; CHECK-NEXT: punpckhwd {{.*#+}} xmm3 = xmm3[4,4,5,5,6,6,7,7]
+; CHECK-NEXT: psrad $24, %xmm3
+; CHECK-NEXT: punpckhwd {{.*#+}} xmm4 = xmm4[4,4,5,5,6,6,7,7]
+; CHECK-NEXT: psrad $24, %xmm4
+; CHECK-NEXT: movdqa %xmm4, %xmm5
+; CHECK-NEXT: pcmpgtd %xmm3, %xmm5
+; CHECK-NEXT: pcmpgtd %xmm4, %xmm3
+; CHECK-NEXT: psrld $31, %xmm3
+; CHECK-NEXT: por %xmm5, %xmm3
+; CHECK-NEXT: retq
+ %1 = call <16 x i32> @llvm.scmp(<16 x i8> %x, <16 x i8> %y)
+ ret <16 x i32> %1
+}
+
+define <16 x i8> @ucmp_wide_op(<16 x i32> %x, <16 x i32> %y) {
+; CHECK-LABEL: ucmp_wide_op:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movdqa {{.*#+}} xmm8 = [2147483648,2147483648,2147483648,2147483648]
+; CHECK-NEXT: pxor %xmm8, %xmm3
+; CHECK-NEXT: pxor %xmm8, %xmm7
+; CHECK-NEXT: movdqa %xmm7, %xmm9
+; CHECK-NEXT: pcmpgtd %xmm3, %xmm9
+; CHECK-NEXT: pcmpgtd %xmm7, %xmm3
+; CHECK-NEXT: psrld $31, %xmm3
+; CHECK-NEXT: por %xmm9, %xmm3
+; CHECK-NEXT: movdqa {{.*#+}} xmm7 = [255,0,0,0,255,0,0,0,255,0,0,0,255,0,0,0]
+; CHECK-NEXT: pand %xmm7, %xmm3
+; CHECK-NEXT: pxor %xmm8, %xmm2
+; CHECK-NEXT: pxor %xmm8, %xmm6
+; CHECK-NEXT: movdqa %xmm6, %xmm9
+; CHECK-NEXT: pcmpgtd %xmm2, %xmm9
+; CHECK-NEXT: pcmpgtd %xmm6, %xmm2
+; CHECK-NEXT: psrld $31, %xmm2
+; CHECK-NEXT: por %xmm9, %xmm2
+; CHECK-NEXT: pand %xmm7, %xmm2
+; CHECK-NEXT: packuswb %xmm3, %xmm2
+; CHECK-NEXT: pxor %xmm8, %xmm1
+; CHECK-NEXT: pxor %xmm8, %xmm5
+; CHECK-NEXT: movdqa %xmm5, %xmm3
+; CHECK-NEXT: pcmpgtd %xmm1, %xmm3
+; CHECK-NEXT: pcmpgtd %xmm5, %xmm1
+; CHECK-NEXT: psrld $31, %xmm1
+; CHECK-NEXT: por %xmm3, %xmm1
+; CHECK-NEXT: pand %xmm7, %xmm1
+; CHECK-NEXT: pxor %xmm8, %xmm0
+; CHECK-NEXT: pxor %xmm8, %xmm4
+; CHECK-NEXT: movdqa %xmm4, %xmm3
+; CHECK-NEXT: pcmpgtd %xmm0, %xmm3
+; CHECK-NEXT: pcmpgtd %xmm4, %xmm0
+; CHECK-NEXT: psrld $31, %xmm0
+; CHECK-NEXT: por %xmm3, %xmm0
+; CHECK-NEXT: pand %xmm7, %xmm0
+; CHECK-NEXT: packuswb %xmm1, %xmm0
+; CHECK-NEXT: packuswb %xmm2, %xmm0
+; CHECK-NEXT: retq
+ %1 = call <16 x i8> @llvm.ucmp(<16 x i32> %x, <16 x i32> %y)
+ ret <16 x i8> %1
+}
+
+define <7 x i25> @scmp_uncommon_vectors(<7 x i109> %x, <7 x i109> %y) {
+; CHECK-LABEL: scmp_uncommon_vectors:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pushq %rbp
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: pushq %r15
+; CHECK-NEXT: .cfi_def_cfa_offset 24
+; CHECK-NEXT: pushq %r14
+; CHECK-NEXT: .cfi_def_cfa_offset 32
+; CHECK-NEXT: pushq %r12
+; CHECK-NEXT: .cfi_def_cfa_offset 40
+; CHECK-NEXT: pushq %rbx
+; CHECK-NEXT: .cfi_def_cfa_offset 48
+; CHECK-NEXT: .cfi_offset %rbx, -48
+; CHECK-NEXT: .cfi_offset %r12, -40
+; CHECK-NEXT: .cfi_offset %r14, -32
+; CHECK-NEXT: .cfi_offset %r15, -24
+; CHECK-NEXT: .cfi_offset %rbp, -16
+; CHECK-NEXT: movq %rdi, %rax
+; CHECK-NEXT: movq %r9, %xmm0
+; CHECK-NEXT: movq {{.*#+}} xmm1 = mem[0],zero
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
+; CHECK-NEXT: movq %xmm0, %r10
+; CHECK-NEXT: shlq $19, %r10
+; CHECK-NEXT: sarq $19, %r10
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %r11
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rbx
+; CHECK-NEXT: shlq $19, %rbx
+; CHECK-NEXT: sarq $19, %rbx
+; CHECK-NEXT: cmpq %r9, %r11
+; CHECK-NEXT: movq %rbx, %rdi
+; CHECK-NEXT: sbbq %r10, %rdi
+; CHECK-NEXT: setl %dil
+; CHECK-NEXT: movzbl %dil, %edi
+; CHECK-NEXT: cmpq %r11, %r9
+; CHECK-NEXT: sbbq %rbx, %r10
+; CHECK-NEXT: movl $-1, %r9d
+; CHECK-NEXT: cmovll %r9d, %edi
+; CHECK-NEXT: movq %r8, %xmm0
+; CHECK-NEXT: movq %rcx, %xmm1
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0]
+; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,3,2,3]
+; CHECK-NEXT: movq %xmm0, %r10
+; CHECK-NEXT: shlq $19, %r10
+; CHECK-NEXT: sarq $19, %r10
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %r11
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rbx
+; CHECK-NEXT: shlq $19, %rbx
+; CHECK-NEXT: sarq $19, %rbx
+; CHECK-NEXT: cmpq %rcx, %r11
+; CHECK-NEXT: movq %rbx, %r8
+; CHECK-NEXT: sbbq %r10, %r8
+; CHECK-NEXT: setl %r8b
+; CHECK-NEXT: movzbl %r8b, %r8d
+; CHECK-NEXT: cmpq %r11, %rcx
+; CHECK-NEXT: sbbq %rbx, %r10
+; CHECK-NEXT: cmovll %r9d, %r8d
+; CHECK-NEXT: movq %rdx, %xmm0
+; CHECK-NEXT: movq %rsi, %xmm1
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0]
+; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,3,2,3]
+; CHECK-NEXT: movq %xmm0, %rcx
+; CHECK-NEXT: shlq $19, %rcx
+; CHECK-NEXT: sarq $19, %rcx
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %r10
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %r11
+; CHECK-NEXT: shlq $19, %r11
+; CHECK-NEXT: sarq $19, %r11
+; CHECK-NEXT: cmpq %rsi, %r10
+; CHECK-NEXT: movq %r11, %rdx
+; CHECK-NEXT: sbbq %rcx, %rdx
+; CHECK-NEXT: setl %dl
+; CHECK-NEXT: movzbl %dl, %edx
+; CHECK-NEXT: cmpq %r10, %rsi
+; CHECK-NEXT: sbbq %r11, %rcx
+; CHECK-NEXT: cmovll %r9d, %edx
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rsi
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %r10
+; CHECK-NEXT: shlq $19, %r10
+; CHECK-NEXT: sarq $19, %r10
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %r11
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rbx
+; CHECK-NEXT: shlq $19, %rbx
+; CHECK-NEXT: sarq $19, %rbx
+; CHECK-NEXT: cmpq %rsi, %r11
+; CHECK-NEXT: movq %rbx, %rcx
+; CHECK-NEXT: sbbq %r10, %rcx
+; CHECK-NEXT: setl %cl
+; CHECK-NEXT: movzbl %cl, %ecx
+; CHECK-NEXT: cmpq %r11, %rsi
+; CHECK-NEXT: sbbq %rbx, %r10
+; CHECK-NEXT: cmovll %r9d, %ecx
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %r10
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %r11
+; CHECK-NEXT: shlq $19, %r11
+; CHECK-NEXT: sarq $19, %r11
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rbx
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %r14
+; CHECK-NEXT: shlq $19, %r14
+; CHECK-NEXT: sarq $19, %r14
+; CHECK-NEXT: cmpq %r10, %rbx
+; CHECK-NEXT: movq %r14, %rsi
+; CHECK-NEXT: sbbq %r11, %rsi
+; CHECK-NEXT: setl %sil
+; CHECK-NEXT: movzbl %sil, %esi
+; CHECK-NEXT: cmpq %rbx, %r10
+; CHECK-NEXT: sbbq %r14, %r11
+; CHECK-NEXT: cmovll %r9d, %esi
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %r10
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %r11
+; CHECK-NEXT: shlq $19, %r11
+; CHECK-NEXT: sarq $19, %r11
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rbx
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %r14
+; CHECK-NEXT: shlq $19, %r14
+; CHECK-NEXT: sarq $19, %r14
+; CHECK-NEXT: cmpq %r10, %rbx
+; CHECK-NEXT: movq %r14, %r9
+; CHECK-NEXT: sbbq %r11, %r9
+; CHECK-NEXT: setl %r9b
+; CHECK-NEXT: movzbl %r9b, %r9d
+; CHECK-NEXT: cmpq %rbx, %r10
+; CHECK-NEXT: sbbq %r14, %r11
+; CHECK-NEXT: movq $-1, %r10
+; CHECK-NEXT: cmovlq %r10, %r9
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %r11
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rbx
+; CHECK-NEXT: shlq $19, %rbx
+; CHECK-NEXT: sarq $19, %rbx
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %r14
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %r15
+; CHECK-NEXT: shlq $19, %r15
+; CHECK-NEXT: sarq $19, %r15
+; CHECK-NEXT: cmpq %r11, %r14
+; CHECK-NEXT: movq %r15, %r12
+; CHECK-NEXT: sbbq %rbx, %r12
+; CHECK-NEXT: setl %bpl
+; CHECK-NEXT: movzbl %bpl, %r12d
+; CHECK-NEXT: cmpq %r14, %r11
+; CHECK-NEXT: sbbq %r15, %rbx
+; CHECK-NEXT: cmovlq %r10, %r12
+; CHECK-NEXT: movq %r12, %r10
+; CHECK-NEXT: shrq $32, %r10
+; CHECK-NEXT: andl $32767, %r10d # imm = 0x7FFF
+; CHECK-NEXT: movw %r10w, 20(%rax)
+; CHECK-NEXT: shlq $22, %r12
+; CHECK-NEXT: movl %r9d, %r10d
+; CHECK-NEXT: andl $33554424, %r10d # imm = 0x1FFFFF8
+; CHECK-NEXT: shrl $3, %r10d
+; CHECK-NEXT: orq %r12, %r10
+; CHECK-NEXT: movl %r10d, 16(%rax)
+; CHECK-NEXT: andl $33554431, %edx # imm = 0x1FFFFFF
+; CHECK-NEXT: andl $33554431, %r8d # imm = 0x1FFFFFF
+; CHECK-NEXT: shlq $25, %r8
+; CHECK-NEXT: orq %rdx, %r8
+; CHECK-NEXT: movq %rdi, %rdx
+; CHECK-NEXT: shlq $50, %rdx
+; CHECK-NEXT: orq %r8, %rdx
+; CHECK-NEXT: movq %rdx, (%rax)
+; CHECK-NEXT: andl $33538048, %edi # imm = 0x1FFC000
+; CHECK-NEXT: shrl $14, %edi
+; CHECK-NEXT: andl $33554431, %esi # imm = 0x1FFFFFF
+; CHECK-NEXT: shlq $11, %rsi
+; CHECK-NEXT: orq %rdi, %rsi
+; CHECK-NEXT: andl $33554431, %ecx # imm = 0x1FFFFFF
+; CHECK-NEXT: shlq $36, %rcx
+; CHECK-NEXT: orq %rsi, %rcx
+; CHECK-NEXT: shlq $61, %r9
+; CHECK-NEXT: orq %rcx, %r9
+; CHECK-NEXT: movq %r9, 8(%rax)
+; CHECK-NEXT: popq %rbx
+; CHECK-NEXT: .cfi_def_cfa_offset 40
+; CHECK-NEXT: popq %r12
+; CHECK-NEXT: .cfi_def_cfa_offset 32
+; CHECK-NEXT: popq %r14
+; CHECK-NEXT: .cfi_def_cfa_offset 24
+; CHECK-NEXT: popq %r15
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: popq %rbp
+; CHECK-NEXT: .cfi_def_cfa_offset 8
+; CHECK-NEXT: retq
+ %1 = call <7 x i25> @llvm.scmp(<7 x i109> %x, <7 x i109> %y)
+ ret <7 x i25> %1
+}
+
+define <2 x i117> @ucmp_uncommon_vectors(<2 x i62> %x, <2 x i62> %y) {
+; CHECK-LABEL: ucmp_uncommon_vectors:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movq %rdi, %rax
+; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm1[2,3,2,3]
+; CHECK-NEXT: movq %xmm2, %rcx
+; CHECK-NEXT: movabsq $4611686018427387903, %rdx # imm = 0x3FFFFFFFFFFFFFFF
+; CHECK-NEXT: andq %rdx, %rcx
+; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm0[2,3,2,3]
+; CHECK-NEXT: movq %xmm2, %rsi
+; CHECK-NEXT: andq %rdx, %rsi
+; CHECK-NEXT: xorl %edi, %edi
+; CHECK-NEXT: cmpq %rcx, %rsi
+; CHECK-NEXT: seta %dil
+; CHECK-NEXT: movq $-1, %rcx
+; CHECK-NEXT: cmovbq %rcx, %rdi
+; CHECK-NEXT: movq %xmm1, %rsi
+; CHECK-NEXT: andq %rdx, %rsi
+; CHECK-NEXT: movq %xmm0, %r8
+; CHECK-NEXT: andq %rdx, %r8
+; CHECK-NEXT: xorl %edx, %edx
+; CHECK-NEXT: cmpq %rsi, %r8
+; CHECK-NEXT: seta %dl
+; CHECK-NEXT: cmovbq %rcx, %rdx
+; CHECK-NEXT: movq %rdx, (%rax)
+; CHECK-NEXT: movq %rdi, %rcx
+; CHECK-NEXT: shrq $11, %rcx
+; CHECK-NEXT: movq %rcx, 16(%rax)
+; CHECK-NEXT: shlq $53, %rdi
+; CHECK-NEXT: movq %rdi, 8(%rax)
+; CHECK-NEXT: movw $0, 28(%rax)
+; CHECK-NEXT: movl $0, 24(%rax)
+; CHECK-NEXT: retq
+ %1 = call <2 x i117> @llvm.ucmp(<2 x i62> %x, <2 x i62> %y)
+ ret <2 x i117> %1
+}
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