[llvm] [AMDGPU] Fix broken MIR generated by gfx11 simulated trap lowering (PR #91652)

[Emma Pilkington via llvm-commits]

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@@ -2065,14 +2065,26 @@ MachineBasicBlock *SIInstrInfo::insertSimulatedTrap(MachineRegisterInfo &MRI,
       .addImm(AMDGPU::SendMsg::ID_INTERRUPT);
   BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), AMDGPU::M0)
       .addUse(AMDGPU::TTMP2);
-  BuildMI(MBB, MI, DL, get(AMDGPU::S_BRANCH)).addMBB(HaltLoop);
+
+  if (MBB.succ_empty()) {
+    BuildMI(MBB, MI, DL, get(AMDGPU::S_BRANCH)).addMBB(HaltLoop);
+  } else {
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epilk wrote:

I think we still need a "fake" branch so we don't disconnect definitions before the trap with their uses after it in the CFG (this was what I was trying to do with the `s_cmp %0,%0; s_cbranch_scc1` thing). I guess we should prefer c_branch_execnz since it seems like a more compact way of representing that. 

Incidentally, I guess [this comment ](https://github.com/llvm/llvm-project/blob/main/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp#L34)is not correct (the s_cbranch_execnz isn't "optional")?

https://github.com/llvm/llvm-project/pull/91652