[llvm] [LoongArch] Select {DIV,MOD}.{W,WU} instruction to eliminate explicit sign extension (PR #92205)

[via llvm-commits]

heiher wrote:

> Seems this case also benefits from this change:
> 
> ```
> define signext i32 @test(i32 signext %a, i32 signext %b) {
> entry:
>   %r = sdiv i32 %a, %b
>   ret i32 %r
> }
> ```
> 
> Before:
> 
> ```
>         div.d   $a0, $a0, $a1
>         addi.w  $a0, $a0, 0
>         ret
> ```
> 
> After:
> 
> ```
>         div.w   $a0, $a0, $a1
>         ret
> ```
> 
> Could you add this test?

Sure. It has been added to a test called `sdiv_si32_si32_si32`:

https://github.com/llvm/llvm-project/pull/92205/files#diff-5c4e077e14446f5a434927f881ccabd5122c2508f6591e1643772ed168aba410L223-L256

Thanks.

https://github.com/llvm/llvm-project/pull/92205