[llvm] [LoongArch] Select {DIV,MOD}.{W,WU} instruction to eliminate explicit sign extension (PR #92205)

[Lu Weining via llvm-commits]

https://github.com/SixWeining commented:

Seems this case also benefits from this change:
```
define signext i32 @sdiv_i32(i32 %a, i32 %b) {
entry:
  %r = sdiv i32 %a, %b
  ret i32 %r
}
```

Before:
```
        addi.w  $a1, $a1, 0
        addi.w  $a0, $a0, 0
        div.d   $a0, $a0, $a1
        addi.w  $a0, $a0, 0
        ret
```

After:
```
        addi.w  $a1, $a1, 0
        addi.w  $a0, $a0, 0
        div.w   $a0, $a0, $a1
        ret
```

Could you add this test?

https://github.com/llvm/llvm-project/pull/92205