[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)

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github-actions[bot] wrote:

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git-clang-format --diff 23b673e5b4b73b42864fcd7d63c1e974317ed4d6 41fbc18c7a4a26b11bc4b772bbe2e384ad9d9dbc -- clang/test/Driver/x86-apx-inline-asm-use-gpr32.cpp clang/lib/Basic/Targets/X86.cpp clang/lib/Basic/Targets/X86.h clang/lib/Driver/ToolChains/Arch/X86.cpp clang/test/Preprocessor/x86_target_features.c llvm/lib/Target/X86/X86ISelLowering.cpp
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View the diff from clang-format here.
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diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 2f381a3fc1..45cc92a904 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -58281,19 +58281,19 @@ X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
     }
   } else if (Constraint.size() == 2 && Constraint[0] == 'j') {
     switch (Constraint[1]) {
-      default:
-        break;
-      case 'R':
-        if (VT == MVT::i8 || VT == MVT::i1)
-          return std::make_pair(0U, &X86::GR8RegClass);
-        if (VT == MVT::i16)
-          return std::make_pair(0U, &X86::GR16RegClass);
-        if (VT == MVT::i32 || VT == MVT::f32 ||
-            (!VT.isVector() && !Subtarget.is64Bit()))
-          return std::make_pair(0U, &X86::GR32RegClass);
-        if (VT != MVT::f80 && !VT.isVector())
-          return std::make_pair(0U, &X86::GR64RegClass);
-        break;
+    default:
+      break;
+    case 'R':
+      if (VT == MVT::i8 || VT == MVT::i1)
+        return std::make_pair(0U, &X86::GR8RegClass);
+      if (VT == MVT::i16)
+        return std::make_pair(0U, &X86::GR16RegClass);
+      if (VT == MVT::i32 || VT == MVT::f32 ||
+          (!VT.isVector() && !Subtarget.is64Bit()))
+        return std::make_pair(0U, &X86::GR32RegClass);
+      if (VT != MVT::f80 && !VT.isVector())
+        return std::make_pair(0U, &X86::GR64RegClass);
+      break;
     }
   }
 

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https://github.com/llvm/llvm-project/pull/92338