[llvm] [RISCV] Move RISCVInsertVSETVLI to after phi elimination (PR #91440)

[Philip Reames via llvm-commits]

preames wrote:

FYI, there appears to be another regression here.  When merging these changes downstream, I see many instances of:
```
       vsetivli        zero, 4, e32, mf2, ta, ma
...
+       vsetivli        zero, 4, e32, mf2, tu, ma
        vmv.s.x v9, a2
+       vsetivli        zero, 4, e32, mf2, ta, ma
```

I see this for both vmv.s.x and vmv.v.x.  It looks like maybe we broke the don't care on tail policy somehow?

https://github.com/llvm/llvm-project/pull/91440