[llvm] [DAGCombiner] Mark vectors as not AllAddOne/AllSubOne on type mismatch (PR #92195)

[Patrick O'Neill via llvm-commits]

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@@ -0,0 +1,42 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; RUN: llc -O1 < %s | FileCheck %s
+
+; Dag-combine used to improperly combine a vector vselect of 0 and 5 into
+; 5 + condition(0/1) because one of the two args was transformed from an i32->i64.
+
+target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
+target triple = "riscv64-unknown-linux-gnu"
+
+ at g.var.0 = global i8 5
+ at g.arr.0 = global i32 0
+
+define i8 @foo() {
+; CHECK-LABEL: foo:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lui a0, %hi(g.arr.0)
+; CHECK-NEXT:    li a1, 4
+; CHECK-NEXT:    sw a1, %lo(g.arr.0)(a0)
+; CHECK-NEXT:    li a0, 0
+; CHECK-NEXT:    ret
+entry:
+  store i32 4, ptr @g.arr.0, align 32
+
+  %g.var.0.val = load i8, ptr @g.var.0, align 1
+  %loaded.arr = insertelement <4 x i8> <i8 1, i8 1, i8 1, i8 1>, i8 %g.var.0.val, i64 0
+
+  %g.arr.elem.0 = load i32, ptr @g.arr.0, align 32
+  %insert.0 = insertelement <4 x i32> zeroinitializer, i32 %g.arr.elem.0, i64 0
+  %cmp.0 = icmp ult <4 x i32> %insert.0, <i32 1, i32 1, i32 1, i32 1>
+
+  %all.g.arr.elem.0 = shufflevector <4 x i32> %insert.0, <4 x i32> zeroinitializer, <4 x i32> zeroinitializer
+  %or.0 = or <4 x i32> %all.g.arr.elem.0, <i32 1, i32 1, i32 1, i32 1>
+
+  %sel.0 = select <4 x i1> %cmp.0, <4 x i32> zeroinitializer, <4 x i32> %or.0
+
+  %trunc.0 = trunc <4 x i32> %sel.0 to <4 x i8>
+
+  %mul.0 = mul <4 x i8> %loaded.arr, %trunc.0
+  %reduced.mul.0 = call i8 @llvm.vector.reduce.mul.v4i8(<4 x i8> %mul.0)
+
+  ret i8 %reduced.mul.0
----------------
patrick-rivos wrote:

Thanks for pointing this out. The original testcase was reduced based on -O1 vs -O0 runtime behavior but I was able to re-reduce it with a debug assertion/modify it to fail on rv32 as well. Updated.

https://github.com/llvm/llvm-project/pull/92195