[llvm] 0647d10 - [RISCV] Remove unneeded casts from int64_t to uint64_t in RISCVMatInt.cpp. NFC

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2024-05-15T10:42:39-07:00
New Revision: 0647d1035cb208195e002b38089b82004b6f7b92

URL: https://github.com/llvm/llvm-project/commit/0647d1035cb208195e002b38089b82004b6f7b92
DIFF: https://github.com/llvm/llvm-project/commit/0647d1035cb208195e002b38089b82004b6f7b92.diff

LOG: [RISCV] Remove unneeded casts from int64_t to uint64_t in RISCVMatInt.cpp. NFC

Most of these were to avoid undefined behavior if a shift left
changed the sign of the result. I don't think its possible to change
the sign of the result here. We're shifting left by 12 after an arithmetic
right shift by more than 12. The bits we are shifting out with the left
shift are guaranteed to be sign bits.

Also use SignExtend64<32> to force upper bits to all 1s instead of an
Or. We know the value isUInt<32> && !isInt<32> which means bit 31 is set.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
index 0a857eb96935e..fca3362f9a8b2 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
@@ -115,30 +115,29 @@ static void generateInstSeqImpl(int64_t Val, const MCSubtargetInfo &STI,
     Val >>= ShiftAmount;
 
     // If the remaining bits don't fit in 12 bits, we might be able to reduce
-    // the // shift amount in order to use LUI which will zero the lower 12
-    // bits.
+    // the shift amount in order to use LUI which will zero the lower 12 bits.
     if (ShiftAmount > 12 && !isInt<12>(Val)) {
-      if (isInt<32>((uint64_t)Val << 12)) {
+      if (isInt<32>(Val << 12)) {
         // Reduce the shift amount and add zeros to the LSBs so it will match
         // LUI.
         ShiftAmount -= 12;
-        Val = (uint64_t)Val << 12;
-      } else if (isUInt<32>((uint64_t)Val << 12) &&
+        Val = Val << 12;
+      } else if (isUInt<32>(Val << 12) &&
                  STI.hasFeature(RISCV::FeatureStdExtZba)) {
         // Reduce the shift amount and add zeros to the LSBs so it will match
         // LUI, then shift left with SLLI.UW to clear the upper 32 set bits.
         ShiftAmount -= 12;
-        Val = ((uint64_t)Val << 12) | (0xffffffffull << 32);
+        Val = SignExtend64<32>(Val << 12);
         Unsigned = true;
       }
     }
 
     // Try to use SLLI_UW for Val when it is uint32 but not int32.
-    if (isUInt<32>((uint64_t)Val) && !isInt<32>((uint64_t)Val) &&
+    if (isUInt<32>(Val) && !isInt<32>(Val) &&
         STI.hasFeature(RISCV::FeatureStdExtZba)) {
-      // Use LUI+ADDI or LUI to compose, then clear the upper 32 bits with
+      // Use LUI+ADDI(W) or LUI to compose, then clear the upper 32 bits with
       // SLLI_UW.
-      Val = ((uint64_t)Val) | (0xffffffffull << 32);
+      Val = SignExtend64<32>(Val);
       Unsigned = true;
     }
   }