[llvm] [TableGen][SubtargetEmitter] Early exit from loop in FindWriteResources and FindReadAdvance (PR #92202)
Michael Maitland via llvm-commits
llvm-commits at lists.llvm.org
Wed May 15 10:21:06 PDT 2024
https://github.com/michaelmaitland updated https://github.com/llvm/llvm-project/pull/92202
>From 9235b8d019c754b1a56a55ec157c10d522f7c2b1 Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Tue, 14 May 2024 18:53:54 -0700
Subject: [PATCH 1/3] [TableGen][SubtargetEmitter] Early exit from loop in
FindWriteResources
This gives us a 26% speed improvement in our downstream.
---
llvm/utils/TableGen/SubtargetEmitter.cpp | 25 ++++++++++++++----------
1 file changed, 15 insertions(+), 10 deletions(-)
diff --git a/llvm/utils/TableGen/SubtargetEmitter.cpp b/llvm/utils/TableGen/SubtargetEmitter.cpp
index 9e32d2de19b2c..737b1bdfd58b6 100644
--- a/llvm/utils/TableGen/SubtargetEmitter.cpp
+++ b/llvm/utils/TableGen/SubtargetEmitter.cpp
@@ -904,14 +904,17 @@ SubtargetEmitter::FindWriteResources(const CodeGenSchedRW &SchedWrite,
continue;
if (AliasDef == WR->getValueAsDef("WriteType") ||
SchedWrite.TheDef == WR->getValueAsDef("WriteType")) {
- if (ResDef) {
- PrintFatalError(WR->getLoc(), "Resources are defined for both "
- "SchedWrite and its alias on processor " +
- ProcModel.ModelName);
- }
ResDef = WR;
+ break;
}
}
+
+ if (ResDef && AliasDef) {
+ PrintFatalError(ResDef->getLoc(), "Resources are defined for both "
+ "SchedWrite and its alias on processor " +
+ ProcModel.ModelName);
+ }
+
// TODO: If ProcModel has a base model (previous generation processor),
// then call FindWriteResources recursively with that model here.
if (!ResDef) {
@@ -958,14 +961,16 @@ Record *SubtargetEmitter::FindReadAdvance(const CodeGenSchedRW &SchedRead,
continue;
if (AliasDef == RA->getValueAsDef("ReadType") ||
SchedRead.TheDef == RA->getValueAsDef("ReadType")) {
- if (ResDef) {
- PrintFatalError(RA->getLoc(), "Resources are defined for both "
- "SchedRead and its alias on processor " +
- ProcModel.ModelName);
- }
ResDef = RA;
+ break;
}
}
+ if (ResDef && AliasDef) {
+ PrintFatalError(ResDef->getLoc(), "Resources are defined for both "
+ "SchedRead and its alias on processor " +
+ ProcModel.ModelName);
+ }
+
// TODO: If ProcModel has a base model (previous generation processor),
// then call FindReadAdvance recursively with that model here.
if (!ResDef && SchedRead.TheDef->getName() != "ReadDefault") {
>From 6b710d0a16602f012377fe469d0992fd64caaf64 Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Wed, 15 May 2024 10:13:07 -0700
Subject: [PATCH 2/3] fixup! make sure we PrintFatalError
---
llvm/utils/TableGen/SubtargetEmitter.cpp | 37 ++++++++++++++----------
1 file changed, 21 insertions(+), 16 deletions(-)
diff --git a/llvm/utils/TableGen/SubtargetEmitter.cpp b/llvm/utils/TableGen/SubtargetEmitter.cpp
index 737b1bdfd58b6..9892f101d0fff 100644
--- a/llvm/utils/TableGen/SubtargetEmitter.cpp
+++ b/llvm/utils/TableGen/SubtargetEmitter.cpp
@@ -902,19 +902,21 @@ SubtargetEmitter::FindWriteResources(const CodeGenSchedRW &SchedWrite,
for (Record *WR : ProcModel.WriteResDefs) {
if (!WR->isSubClassOf("WriteRes"))
continue;
- if (AliasDef == WR->getValueAsDef("WriteType") ||
- SchedWrite.TheDef == WR->getValueAsDef("WriteType")) {
+ // If there is no AliasDef and we find a match, we can early exit since
+ // there is no need to verify whether there are resources defined for both
+ // SchedWrite and its alias.
+ if (!AliasDef && SchedWrite.TheDef == WR->getValueAsDef("WriteType")) {
ResDef = WR;
break;
- }
- }
-
- if (ResDef && AliasDef) {
- PrintFatalError(ResDef->getLoc(), "Resources are defined for both "
+ } else if (AliasDef == WR->getValueAsDef("WriteType")) {
+ if (ResDef) {
+ PrintFatalError(WR->getLoc(), "Resources are defined for both "
"SchedWrite and its alias on processor " +
ProcModel.ModelName);
+ }
+ ResDef = WR;
+ }
}
-
// TODO: If ProcModel has a base model (previous generation processor),
// then call FindWriteResources recursively with that model here.
if (!ResDef) {
@@ -959,18 +961,21 @@ Record *SubtargetEmitter::FindReadAdvance(const CodeGenSchedRW &SchedRead,
for (Record *RA : ProcModel.ReadAdvanceDefs) {
if (!RA->isSubClassOf("ReadAdvance"))
continue;
- if (AliasDef == RA->getValueAsDef("ReadType") ||
- SchedRead.TheDef == RA->getValueAsDef("ReadType")) {
- ResDef = RA;
+ // If there is no AliasDef and we find a match, we can early exit since
+ // there is no need to verify whether there are resources defined for both
+ // SchedWrite and its alias.
+ if (!AliasDef && AliasDef == RA->getValueAsDef("ReadType")) {
+ ResDef = WR;
break;
- }
- }
- if (ResDef && AliasDef) {
- PrintFatalError(ResDef->getLoc(), "Resources are defined for both "
+ } else if (SchedRead.TheDef == RA->getValueAsDef("ReadType")) {
+ if (ResDef) {
+ PrintFatalError(RA->getLoc(), "Resources are defined for both "
"SchedRead and its alias on processor " +
ProcModel.ModelName);
+ }
+ ResDef = RA;
+ }
}
-
// TODO: If ProcModel has a base model (previous generation processor),
// then call FindReadAdvance recursively with that model here.
if (!ResDef && SchedRead.TheDef->getName() != "ReadDefault") {
>From 5212ee108819263c0c56e1e9d2022a5f12e91114 Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Wed, 15 May 2024 10:20:44 -0700
Subject: [PATCH 3/3] fixup! fix typo
---
llvm/utils/TableGen/SubtargetEmitter.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/utils/TableGen/SubtargetEmitter.cpp b/llvm/utils/TableGen/SubtargetEmitter.cpp
index 9892f101d0fff..fb06d05c26f38 100644
--- a/llvm/utils/TableGen/SubtargetEmitter.cpp
+++ b/llvm/utils/TableGen/SubtargetEmitter.cpp
@@ -965,7 +965,7 @@ Record *SubtargetEmitter::FindReadAdvance(const CodeGenSchedRW &SchedRead,
// there is no need to verify whether there are resources defined for both
// SchedWrite and its alias.
if (!AliasDef && AliasDef == RA->getValueAsDef("ReadType")) {
- ResDef = WR;
+ ResDef = RA;
break;
} else if (SchedRead.TheDef == RA->getValueAsDef("ReadType")) {
if (ResDef) {
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