[llvm] [TableGen][SubtargetEmitter] Early exit from loop in FindWriteResources (PR #92202)

[Michael Maitland via llvm-commits]

https://github.com/michaelmaitland updated https://github.com/llvm/llvm-project/pull/92202

>From 9235b8d019c754b1a56a55ec157c10d522f7c2b1 Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Tue, 14 May 2024 18:53:54 -0700
Subject: [PATCH 1/2] [TableGen][SubtargetEmitter] Early exit from loop in
 FindWriteResources

This gives us a 26% speed improvement in our downstream.
---
 llvm/utils/TableGen/SubtargetEmitter.cpp | 25 ++++++++++++++----------
 1 file changed, 15 insertions(+), 10 deletions(-)

diff --git a/llvm/utils/TableGen/SubtargetEmitter.cpp b/llvm/utils/TableGen/SubtargetEmitter.cpp
index 9e32d2de19b2c..737b1bdfd58b6 100644
--- a/llvm/utils/TableGen/SubtargetEmitter.cpp
+++ b/llvm/utils/TableGen/SubtargetEmitter.cpp
@@ -904,14 +904,17 @@ SubtargetEmitter::FindWriteResources(const CodeGenSchedRW &SchedWrite,
       continue;
     if (AliasDef == WR->getValueAsDef("WriteType") ||
         SchedWrite.TheDef == WR->getValueAsDef("WriteType")) {
-      if (ResDef) {
-        PrintFatalError(WR->getLoc(), "Resources are defined for both "
-                                      "SchedWrite and its alias on processor " +
-                                          ProcModel.ModelName);
-      }
       ResDef = WR;
+      break;
     }
   }
+
+  if (ResDef && AliasDef) {
+    PrintFatalError(ResDef->getLoc(), "Resources are defined for both "
+                                      "SchedWrite and its alias on processor " +
+                                          ProcModel.ModelName);
+  }
+
   // TODO: If ProcModel has a base model (previous generation processor),
   // then call FindWriteResources recursively with that model here.
   if (!ResDef) {
@@ -958,14 +961,16 @@ Record *SubtargetEmitter::FindReadAdvance(const CodeGenSchedRW &SchedRead,
       continue;
     if (AliasDef == RA->getValueAsDef("ReadType") ||
         SchedRead.TheDef == RA->getValueAsDef("ReadType")) {
-      if (ResDef) {
-        PrintFatalError(RA->getLoc(), "Resources are defined for both "
-                                      "SchedRead and its alias on processor " +
-                                          ProcModel.ModelName);
-      }
       ResDef = RA;
+      break;
     }
   }
+  if (ResDef && AliasDef) {
+    PrintFatalError(ResDef->getLoc(), "Resources are defined for both "
+                                      "SchedRead and its alias on processor " +
+                                          ProcModel.ModelName);
+  }
+
   // TODO: If ProcModel has a base model (previous generation processor),
   // then call FindReadAdvance recursively with that model here.
   if (!ResDef && SchedRead.TheDef->getName() != "ReadDefault") {

>From 3fc1d3ea847dcd5fcd0dc47f8ba7b597579ad0b5 Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Wed, 15 May 2024 10:13:07 -0700
Subject: [PATCH 2/2] fixup! make sure we PrintFatalError

---
 llvm/utils/TableGen/SubtargetEmitter.cpp | 37 ++++++++++++++----------
 1 file changed, 22 insertions(+), 15 deletions(-)

diff --git a/llvm/utils/TableGen/SubtargetEmitter.cpp b/llvm/utils/TableGen/SubtargetEmitter.cpp
index 737b1bdfd58b6..f8b96b787417a 100644
--- a/llvm/utils/TableGen/SubtargetEmitter.cpp
+++ b/llvm/utils/TableGen/SubtargetEmitter.cpp
@@ -902,17 +902,20 @@ SubtargetEmitter::FindWriteResources(const CodeGenSchedRW &SchedWrite,
   for (Record *WR : ProcModel.WriteResDefs) {
     if (!WR->isSubClassOf("WriteRes"))
       continue;
-    if (AliasDef == WR->getValueAsDef("WriteType") ||
-        SchedWrite.TheDef == WR->getValueAsDef("WriteType")) {
+    // If there is no AliasDef and we find a match, we can early exit since
+    // there is no need to verify whether there are resources defined for both
+    // SchedWrite and its alias.
+    if (!AliasDef && SchedWrite.TheDef == WR->getValueAsDef("WriteType")) {
       ResDef = WR;
       break;
-    }
-  }
-
-  if (ResDef && AliasDef) {
-    PrintFatalError(ResDef->getLoc(), "Resources are defined for both "
+    } else if (AliasDef == WR->getValueAsDef("WriteType")) {
+      if (ResDef) {
+        PrintFatalError(WR->getLoc(), "Resources are defined for both "
                                       "SchedWrite and its alias on processor " +
                                           ProcModel.ModelName);
+      }
+      ResDef = WR;
+    }
   }
 
   // TODO: If ProcModel has a base model (previous generation processor),
@@ -959,16 +962,20 @@ Record *SubtargetEmitter::FindReadAdvance(const CodeGenSchedRW &SchedRead,
   for (Record *RA : ProcModel.ReadAdvanceDefs) {
     if (!RA->isSubClassOf("ReadAdvance"))
       continue;
-    if (AliasDef == RA->getValueAsDef("ReadType") ||
-        SchedRead.TheDef == RA->getValueAsDef("ReadType")) {
-      ResDef = RA;
+    // If there is no AliasDef and we find a match, we can early exit since
+    // there is no need to verify whether there are resources defined for both
+    // SchedWrite and its alias.
+    if (!AliasDef && AliasDef == RA->getValueAsDef("ReadType")) {
+      ResDef = WR;
       break;
-    }
-  }
-  if (ResDef && AliasDef) {
-    PrintFatalError(ResDef->getLoc(), "Resources are defined for both "
-                                      "SchedRead and its alias on processor " +
+    } else if (SchedRead.TheDef == RA->getValueAsDef("ReadType")) {
+      if (ResDef) {
+        PrintFatalError(WR->getLoc(), "Resources are defined for both "
+                                      "SchedWrite and its alias on processor " +
                                           ProcModel.ModelName);
+      }
+      ResDef = RA;
+    }
   }
 
   // TODO: If ProcModel has a base model (previous generation processor),