[llvm] [RISCV] Support postRA vsetvl insertion pass (PR #70549)
Philip Reames via llvm-commits
llvm-commits at lists.llvm.org
Wed May 15 10:11:01 PDT 2024
================
@@ -46,13 +46,12 @@ define <16 x i8> @trn1.v16i8(<16 x i8> %v0, <16 x i8> %v1) {
define <16 x i8> @trn2.v16i8(<16 x i8> %v0, <16 x i8> %v1) {
; CHECK-LABEL: trn2.v16i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vi v8, v8, 1
; CHECK-NEXT: lui a0, 11
; CHECK-NEXT: addi a0, a0, -1366
-; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
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preames wrote:
Again, real (if minor) regression.
https://github.com/llvm/llvm-project/pull/70549
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