[llvm] [RISCV] Support postRA vsetvl insertion pass (PR #70549)

[Philip Reames via llvm-commits]

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@@ -197,28 +197,51 @@ entry:
 define void @test_compresstore_v256i8(ptr %p, <256 x i1> %mask, <256 x i8> %data) {
 ; RV64-LABEL: test_compresstore_v256i8:
 ; RV64:       # %bb.0: # %entry
-; RV64-NEXT:    vmv1r.v v7, v8
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preames wrote:

This change is a bit concerning, we have no actual reordering happening here, but we chose a strictly less optimal register allocation solution.  I don't see any obvious reason for this one, does anyone else?

https://github.com/llvm/llvm-project/pull/70549