[llvm] [RISCV] Support postRA vsetvl insertion pass (PR #70549)

[Philip Reames via llvm-commits]

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@@ -223,16 +223,16 @@ declare <vscale x 32 x half> @llvm.vp.ceil.nxv32f16(<vscale x 32 x half>, <vscal
 define <vscale x 32 x half> @vp_ceil_vv_nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
 ; CHECK-LABEL: vp_ceil_vv_nxv32f16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vmv1r.v v16, v0
 ; CHECK-NEXT:    lui a1, %hi(.LCPI10_0)
 ; CHECK-NEXT:    flh fa5, %lo(.LCPI10_0)(a1)
+; CHECK-NEXT:    vmv1r.v v16, v0
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preames wrote:

This is another (unrelated) missed opportunity.  We're moving v0 into another register, but nothing between this and restore appears to actually write to v0.  Do we have an imprecise clobber specification on some instruction?

https://github.com/llvm/llvm-project/pull/70549