[llvm] [AArch64][GISel] Support SVE with 128-bit min-size for G_LOAD and G_STORE (PR #92130)
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Wed May 15 09:40:51 PDT 2024
================
@@ -1413,7 +1413,7 @@ bool IRTranslator::translateLoad(const User &U, MachineIRBuilder &MIRBuilder) {
bool IRTranslator::translateStore(const User &U, MachineIRBuilder &MIRBuilder) {
const StoreInst &SI = cast<StoreInst>(U);
- if (DL->getTypeStoreSize(SI.getValueOperand()->getType()) == 0)
+ if (DL->getTypeStoreSize(SI.getValueOperand()->getType()).isZero())
----------------
Him188 wrote:
It's needed, otherwise we implicitly cast a ScalableVectorTy into ScalarTy and will fail.
```c++
TypeSize::operator TypeSize::ScalarTy() const {
if (isScalable()) {
reportInvalidSizeRequest(
"Cannot implicitly convert a scalable size to a fixed-width size in "
"`TypeSize::operator ScalarTy()`");
return getKnownMinValue();
}
return getFixedValue();
}
```
https://github.com/llvm/llvm-project/pull/92130
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