[llvm] [DAGCombiner] Mark vectors as not AllAddOne/AllSubOne on type mismatch (PR #92195)

[Craig Topper via llvm-commits]

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@@ -0,0 +1,42 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
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topperc wrote:

Can we just name this pr92193.ll.

https://github.com/llvm/llvm-project/pull/92195