[llvm] [RISCV] Support postRA vsetvl insertion pass (PR #70549)
Luke Lau via llvm-commits
llvm-commits at lists.llvm.org
Wed May 15 04:13:10 PDT 2024
================
@@ -96,6 +96,10 @@ static cl::opt<bool> EnableMISchedLoadClustering(
cl::desc("Enable load clustering in the machine scheduler"),
cl::init(false));
+static cl::opt<bool> EnableVSETVLIAfterRVVRegAlloc(
+ "riscv-vsetvli-after-rvv-regalloc", cl::Hidden,
+ cl::desc("vsetvl insertion after rvv regalloc"), cl::init(true));
----------------
lukel97 wrote:
Nit
```suggestion
cl::desc("Insert vsetvls after vector register allocation"), cl::init(true));
```
https://github.com/llvm/llvm-project/pull/70549
More information about the llvm-commits
mailing list