[llvm] [DAGCombiner] Mark vectors as not AllAddOne/AllSubOne on undef or type mismatch (PR #92195)

[Simon Pilgrim via llvm-commits]

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@@ -0,0 +1,42 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; RUN: llc -O1 < %s | FileCheck %s
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RKSimon wrote:

Do you need -O1?

https://github.com/llvm/llvm-project/pull/92195