[llvm] [DAGCombiner] Mark vectors as not AllAddOne/AllSubOne on undef or type mismatch (PR #92195)

[Simon Pilgrim via llvm-commits]

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@@ -0,0 +1,42 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; RUN: llc -O1 < %s | FileCheck %s
+
+; Dag-combine used to improperly combine a vector vselect of 0 and 5 into
+; 5 + condition(0/1) because one of the two args was transformed from an i32->i64.
+
+target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
+target triple = "riscv64-unknown-linux-gnu"
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RKSimon wrote:

Maybe remove the datalayout and move the triple into RUN command `-mtriple=riscv64-unknown-linux-gnu` - not sure if you should add a riscv32 RUN line as well

https://github.com/llvm/llvm-project/pull/92195