[llvm] [X86] LowerBITREVERSE - use AND+CMPEQ+MOVMSK trick to lower scalar types (PR #92236)
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Wed May 15 02:59:26 PDT 2024
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You can test this locally with the following command:
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git-clang-format --diff ca4a405232cf170f20a2f111bf72beab82095935 dd32f93696571166cad9f170df5a7b83735d7d23 -- llvm/lib/Target/X86/X86ISelLowering.cpp llvm/lib/Target/X86/X86TargetTransformInfo.cpp
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View the diff from clang-format here.
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diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 5d3d290365..9bc5550ab7 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -1294,8 +1294,8 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
setOperationAction(ISD::BITREVERSE, VT, Custom);
setOperationAction(ISD::CTLZ, VT, Custom);
}
- setOperationAction(ISD::BITREVERSE, MVT::i8, Custom);
- setOperationAction(ISD::BITREVERSE, MVT::i16, Custom);
+ setOperationAction(ISD::BITREVERSE, MVT::i8, Custom);
+ setOperationAction(ISD::BITREVERSE, MVT::i16, Custom);
// These might be better off as horizontal vector ops.
setOperationAction(ISD::ADD, MVT::i16, Custom);
@@ -1923,7 +1923,7 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
}
if (HasBWI)
- setOperationAction(ISD::BITREVERSE, MVT::i64, Custom);
+ setOperationAction(ISD::BITREVERSE, MVT::i64, Custom);
setOperationAction(ISD::SETCC, MVT::v8f64, Custom);
setOperationAction(ISD::SETCC, MVT::v16f32, Custom);
diff --git a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
index 252b7a7dcb..545c963d38 100644
--- a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
+++ b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
@@ -3952,31 +3952,30 @@ X86TTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
{ ISD::UMIN, MVT::v8i16, { 1, 1, 1, 1 } },
};
static const CostKindTblEntry SSSE3CostTbl[] = {
- { ISD::ABS, MVT::v4i32, { 1, 2, 1, 1 } },
- { ISD::ABS, MVT::v8i16, { 1, 2, 1, 1 } },
- { ISD::ABS, MVT::v16i8, { 1, 2, 1, 1 } },
- { ISD::BITREVERSE, MVT::v2i64, { 16, 20, 11, 21 } },
- { ISD::BITREVERSE, MVT::v4i32, { 16, 20, 11, 21 } },
- { ISD::BITREVERSE, MVT::v8i16, { 16, 20, 11, 21 } },
- { ISD::BITREVERSE, MVT::v16i8, { 11, 12, 10, 16 } },
- { ISD::BITREVERSE, MVT::i16, { 5, 6, 6, 10 } }, // AND+PCMPEQB+PMOVMSKB
- { ISD::BITREVERSE, MVT::i8, { 4, 4, 7, 8 } }, // AND+PCMPEQB+PMOVMSKB
- { ISD::BSWAP, MVT::v2i64, { 2, 3, 1, 5 } },
- { ISD::BSWAP, MVT::v4i32, { 2, 3, 1, 5 } },
- { ISD::BSWAP, MVT::v8i16, { 2, 3, 1, 5 } },
- { ISD::CTLZ, MVT::v2i64, { 18, 28, 28, 35 } },
- { ISD::CTLZ, MVT::v4i32, { 15, 20, 22, 28 } },
- { ISD::CTLZ, MVT::v8i16, { 13, 17, 16, 22 } },
- { ISD::CTLZ, MVT::v16i8, { 11, 15, 10, 16 } },
- { ISD::CTPOP, MVT::v2i64, { 13, 19, 12, 18 } },
- { ISD::CTPOP, MVT::v4i32, { 18, 24, 16, 22 } },
- { ISD::CTPOP, MVT::v8i16, { 13, 18, 14, 20 } },
- { ISD::CTPOP, MVT::v16i8, { 11, 12, 10, 16 } },
- { ISD::CTTZ, MVT::v2i64, { 13, 25, 15, 22 } },
- { ISD::CTTZ, MVT::v4i32, { 18, 26, 19, 25 } },
- { ISD::CTTZ, MVT::v8i16, { 13, 20, 17, 23 } },
- { ISD::CTTZ, MVT::v16i8, { 11, 16, 13, 19 } }
- };
+ {ISD::ABS, MVT::v4i32, {1, 2, 1, 1}},
+ {ISD::ABS, MVT::v8i16, {1, 2, 1, 1}},
+ {ISD::ABS, MVT::v16i8, {1, 2, 1, 1}},
+ {ISD::BITREVERSE, MVT::v2i64, {16, 20, 11, 21}},
+ {ISD::BITREVERSE, MVT::v4i32, {16, 20, 11, 21}},
+ {ISD::BITREVERSE, MVT::v8i16, {16, 20, 11, 21}},
+ {ISD::BITREVERSE, MVT::v16i8, {11, 12, 10, 16}},
+ {ISD::BITREVERSE, MVT::i16, {5, 6, 6, 10}}, // AND+PCMPEQB+PMOVMSKB
+ {ISD::BITREVERSE, MVT::i8, {4, 4, 7, 8}}, // AND+PCMPEQB+PMOVMSKB
+ {ISD::BSWAP, MVT::v2i64, {2, 3, 1, 5}},
+ {ISD::BSWAP, MVT::v4i32, {2, 3, 1, 5}},
+ {ISD::BSWAP, MVT::v8i16, {2, 3, 1, 5}},
+ {ISD::CTLZ, MVT::v2i64, {18, 28, 28, 35}},
+ {ISD::CTLZ, MVT::v4i32, {15, 20, 22, 28}},
+ {ISD::CTLZ, MVT::v8i16, {13, 17, 16, 22}},
+ {ISD::CTLZ, MVT::v16i8, {11, 15, 10, 16}},
+ {ISD::CTPOP, MVT::v2i64, {13, 19, 12, 18}},
+ {ISD::CTPOP, MVT::v4i32, {18, 24, 16, 22}},
+ {ISD::CTPOP, MVT::v8i16, {13, 18, 14, 20}},
+ {ISD::CTPOP, MVT::v16i8, {11, 12, 10, 16}},
+ {ISD::CTTZ, MVT::v2i64, {13, 25, 15, 22}},
+ {ISD::CTTZ, MVT::v4i32, {18, 26, 19, 25}},
+ {ISD::CTTZ, MVT::v8i16, {13, 20, 17, 23}},
+ {ISD::CTTZ, MVT::v16i8, {11, 16, 13, 19}}};
static const CostKindTblEntry SSE2CostTbl[] = {
{ ISD::ABS, MVT::v2i64, { 3, 6, 5, 5 } },
{ ISD::ABS, MVT::v4i32, { 1, 4, 4, 4 } },
``````````
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https://github.com/llvm/llvm-project/pull/92236
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