[llvm] [DAGCombiner] Mark vectors as not AllAddOne/AllSubOne on undef or type mismatch (PR #92195)

Patrick O'Neill via llvm-commits llvm-commits at lists.llvm.org
Tue May 14 19:30:53 PDT 2024


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@@ -12140,10 +12140,16 @@ SDValue DAGCombiner::foldVSelectOfConstants(SDNode *N) {
   for (unsigned i = 0; i != Elts; ++i) {
     SDValue N1Elt = N1.getOperand(i);
     SDValue N2Elt = N2.getOperand(i);
-    if (N1Elt.isUndef() || N2Elt.isUndef())
+    if (N1Elt.isUndef() || N2Elt.isUndef()) {
+      AllAddOne = false;
----------------
patrick-rivos wrote:

Updated. This invalidates the assertion I added (since a vector of undefs can be both `AllAddOne` and `AllSubOne`) so I removed that as well.

https://github.com/llvm/llvm-project/pull/92195


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