[llvm] [LV] add test for #47665, #88802 (PR #91135)
Ramkumar Ramachandra via llvm-commits
llvm-commits at lists.llvm.org
Tue May 14 11:30:34 PDT 2024
https://github.com/artagnon updated https://github.com/llvm/llvm-project/pull/91135
>From 6232868236fb785f6d0484c7cdd87436dc50ea13 Mon Sep 17 00:00:00 2001
From: Ramkumar Ramachandra <r at artagnon.com>
Date: Sun, 5 May 2024 18:25:08 +0100
Subject: [PATCH 1/3] LoopVectorize: add test for crash #47665
---
.../LoopVectorize/SystemZ/pr47665.ll | 24 +++++++++++++++++++
1 file changed, 24 insertions(+)
create mode 100644 llvm/test/Transforms/LoopVectorize/SystemZ/pr47665.ll
diff --git a/llvm/test/Transforms/LoopVectorize/SystemZ/pr47665.ll b/llvm/test/Transforms/LoopVectorize/SystemZ/pr47665.ll
new file mode 100644
index 0000000000000..586f4bdc65ef0
--- /dev/null
+++ b/llvm/test/Transforms/LoopVectorize/SystemZ/pr47665.ll
@@ -0,0 +1,24 @@
+; REQUIRES: asserts
+; RUN: not --crash opt -passes=loop-vectorize -mtriple=s390x -mcpu=z14 -disable-output %s
+; RUN: not --crash opt -passes=loop-vectorize -force-vector-width=2 -mtriple=s390x -mcpu=z14 -disable-output %s
+
+define void @test(ptr %p) {
+entry:
+ br label %for.body
+
+for.body: ; preds = %for.body, %entry
+ %iv = phi i32 [ 0, %entry ], [ %iv.next, %for.body ]
+ %trunc = trunc i40 0 to i32
+ %icmp.eq = icmp eq i32 %trunc, 0
+ %zext = zext i1 %icmp.eq to i32
+ %icmp.ult = icmp ult i32 0, %zext
+ %or = or i1 %icmp.ult, true
+ %icmp.sgt = icmp sgt i1 %or, false
+ store i1 %icmp.sgt, ptr %p, align 1
+ %iv.next = add i32 %iv, 1
+ %cond = icmp ult i32 %iv.next, 10
+ br i1 %cond, label %for.body, label %exit
+
+exit: ; preds = %for.body
+ ret void
+}
>From bf39d14384e19df5643e8527e1f9af01baca8d06 Mon Sep 17 00:00:00 2001
From: Ramkumar Ramachandra <r at artagnon.com>
Date: Tue, 7 May 2024 14:00:01 +0100
Subject: [PATCH 2/3] LoopVectorize/RISCV: add test for #88802
---
.../Transforms/LoopVectorize/RISCV/pr88802.ll | 32 +++++++++++++++++++
1 file changed, 32 insertions(+)
create mode 100644 llvm/test/Transforms/LoopVectorize/RISCV/pr88802.ll
diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/pr88802.ll b/llvm/test/Transforms/LoopVectorize/RISCV/pr88802.ll
new file mode 100644
index 0000000000000..4b334fec318e6
--- /dev/null
+++ b/llvm/test/Transforms/LoopVectorize/RISCV/pr88802.ll
@@ -0,0 +1,32 @@
+; REQUIRES: asserts
+; RUN: not --crash opt -passes=loop-vectorize -mtriple=riscv64 -mattr=+v -disable-output %s
+
+define void @test(ptr %p) {
+entry:
+ br label %for.cond
+
+for.cond: ; preds = %for.body, %entry
+ %iv = phi i32 [ 0, %entry ], [ %add, %for.body ]
+ %add = add i32 %iv, 1
+ %cmp.slt = icmp slt i32 %iv, 2
+ br i1 %cmp.slt, label %cond.false, label %cond.true
+
+cond.true: ; preds = %for.cond
+ %trunc.i32 = trunc i64 0 to i32
+ br label %for.body
+
+cond.false: ; preds = %for.cond
+ %zext = zext i8 0 to i32
+ br label %for.body
+
+for.body: ; preds = %cond.false, %cond.true
+ %cond = phi i32 [ %trunc.i32, %cond.true ], [ %zext, %cond.false ]
+ %cond.i8 = trunc i32 %cond to i8
+ %and = and i8 %cond.i8, 0
+ store i8 %and, ptr %p, align 1
+ %cmp = icmp slt i32 %iv, 2
+ br i1 %cmp, label %for.cond, label %exit
+
+exit: ; preds = %for.body
+ ret void
+}
>From 40bd3fe96c6aa83c6df3d201801e72685acd7508 Mon Sep 17 00:00:00 2001
From: Ramkumar Ramachandra <r at artagnon.com>
Date: Tue, 14 May 2024 18:29:12 +0100
Subject: [PATCH 3/3] [LV] update tests to be less nonsensical
---
.../Transforms/LoopVectorize/RISCV/pr88802.ll | 23 +++++++++----------
.../LoopVectorize/SystemZ/pr47665.ll | 7 +++---
2 files changed, 15 insertions(+), 15 deletions(-)
diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/pr88802.ll b/llvm/test/Transforms/LoopVectorize/RISCV/pr88802.ll
index 4b334fec318e6..df3680abbf906 100644
--- a/llvm/test/Transforms/LoopVectorize/RISCV/pr88802.ll
+++ b/llvm/test/Transforms/LoopVectorize/RISCV/pr88802.ll
@@ -1,7 +1,7 @@
; REQUIRES: asserts
; RUN: not --crash opt -passes=loop-vectorize -mtriple=riscv64 -mattr=+v -disable-output %s
-define void @test(ptr %p) {
+define void @test(ptr %p, i64 %a, i8 %b) {
entry:
br label %for.cond
@@ -9,21 +9,20 @@ for.cond: ; preds = %for.body, %entry
%iv = phi i32 [ 0, %entry ], [ %add, %for.body ]
%add = add i32 %iv, 1
%cmp.slt = icmp slt i32 %iv, 2
- br i1 %cmp.slt, label %cond.false, label %cond.true
-
-cond.true: ; preds = %for.cond
- %trunc.i32 = trunc i64 0 to i32
- br label %for.body
+ %shl = shl i64 %a, 48
+ %ashr = ashr i64 %shl, 52
+ %trunc.i32 = trunc i64 %ashr to i32
+ br i1 %cmp.slt, label %cond.false, label %for.body
cond.false: ; preds = %for.cond
- %zext = zext i8 0 to i32
+ %zext = zext i8 %b to i32
br label %for.body
-for.body: ; preds = %cond.false, %cond.true
- %cond = phi i32 [ %trunc.i32, %cond.true ], [ %zext, %cond.false ]
- %cond.i8 = trunc i32 %cond to i8
- %and = and i8 %cond.i8, 0
- store i8 %and, ptr %p, align 1
+for.body: ; preds = %cond.false, %for.cond
+ %cond = phi i32 [ %trunc.i32, %for.cond ], [ %zext, %cond.false ]
+ %shl.i32 = shl i32 %cond, 8
+ %trunc = trunc i32 %shl.i32 to i8
+ store i8 %trunc, ptr %p, align 1
%cmp = icmp slt i32 %iv, 2
br i1 %cmp, label %for.cond, label %exit
diff --git a/llvm/test/Transforms/LoopVectorize/SystemZ/pr47665.ll b/llvm/test/Transforms/LoopVectorize/SystemZ/pr47665.ll
index 586f4bdc65ef0..8451d4a4a5433 100644
--- a/llvm/test/Transforms/LoopVectorize/SystemZ/pr47665.ll
+++ b/llvm/test/Transforms/LoopVectorize/SystemZ/pr47665.ll
@@ -1,14 +1,15 @@
; REQUIRES: asserts
; RUN: not --crash opt -passes=loop-vectorize -mtriple=s390x -mcpu=z14 -disable-output %s
-; RUN: not --crash opt -passes=loop-vectorize -force-vector-width=2 -mtriple=s390x -mcpu=z14 -disable-output %s
-define void @test(ptr %p) {
+define void @test(ptr %p, i40 %a) {
entry:
br label %for.body
for.body: ; preds = %for.body, %entry
%iv = phi i32 [ 0, %entry ], [ %iv.next, %for.body ]
- %trunc = trunc i40 0 to i32
+ %shl = shl i40 %a, 24
+ %ashr = ashr i40 %shl, 28
+ %trunc = trunc i40 %ashr to i32
%icmp.eq = icmp eq i32 %trunc, 0
%zext = zext i1 %icmp.eq to i32
%icmp.ult = icmp ult i32 0, %zext
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