[llvm] [AArch64][TargetParser] move CPUInfo into tablegen (PR #92145)
Tomas Matheson via llvm-commits
llvm-commits at lists.llvm.org
Tue May 14 09:30:42 PDT 2024
https://github.com/tmatheson-arm created https://github.com/llvm/llvm-project/pull/92145
This builds on top of https://github.com/llvm/llvm-project/pull/92037, which moves the architecture information. The new changes start at 52b8af6cde23d6ceacbc33f292e0bff1265501b5.
The changes to `AArch64Processors.td` look like a lot, but actually all that is happening for each processor is:
- The class is changed from `ProcessorModel` to `AArch64Processor`
- The base architecture is added, as a reference to the `Architecture64` e.g. `HasV9_0aOps`
- The list of "enabled by default" extensions is added.
>From c650ad9a25f492f3011c6db416171d346d60b759 Mon Sep 17 00:00:00 2001
From: Tomas Matheson <tomas.matheson at arm.com>
Date: Mon, 13 May 2024 17:15:44 +0100
Subject: [PATCH 1/2] [AArch64][TargetParser] move ArchInfo into tablegen
---
.../llvm/TargetParser/AArch64TargetParser.h | 48 +----
llvm/lib/Target/AArch64/AArch64Features.td | 174 ++++++++++--------
llvm/utils/TableGen/ARMTargetDefEmitter.cpp | 65 +++++++
3 files changed, 163 insertions(+), 124 deletions(-)
diff --git a/llvm/include/llvm/TargetParser/AArch64TargetParser.h b/llvm/include/llvm/TargetParser/AArch64TargetParser.h
index 20c3f95173c28..0c89b7859975c 100644
--- a/llvm/include/llvm/TargetParser/AArch64TargetParser.h
+++ b/llvm/include/llvm/TargetParser/AArch64TargetParser.h
@@ -238,8 +238,8 @@ enum ArchProfile { AProfile = 'A', RProfile = 'R', InvalidProfile = '?' };
struct ArchInfo {
VersionTuple Version; // Architecture version, major + minor.
ArchProfile Profile; // Architecuture profile
- StringRef Name; // Human readable name, e.g. "armv8.1-a"
- StringRef ArchFeature; // Command line feature flag, e.g. +v8a
+ StringRef Name; // Name as supplied to -march e.g. "armv8.1-a"
+ StringRef ArchFeature; // Name as supplied to -target-feature, e.g. "+v8a"
AArch64::ExtensionBitset
DefaultExts; // bitfield of default extensions ArchExtKind
@@ -288,48 +288,8 @@ struct ArchInfo {
static std::optional<ArchInfo> findBySubArch(StringRef SubArch);
};
-// clang-format off
-inline constexpr ArchInfo ARMV8A = { VersionTuple{8, 0}, AProfile, "armv8-a", "+v8a", (
- AArch64::ExtensionBitset({AArch64::AEK_FP, AArch64::AEK_SIMD})), };
-inline constexpr ArchInfo ARMV8_1A = { VersionTuple{8, 1}, AProfile, "armv8.1-a", "+v8.1a", (ARMV8A.DefaultExts |
- AArch64::ExtensionBitset({AArch64::AEK_CRC, AArch64::AEK_LSE, AArch64::AEK_RDM}))};
-inline constexpr ArchInfo ARMV8_2A = { VersionTuple{8, 2}, AProfile, "armv8.2-a", "+v8.2a", (ARMV8_1A.DefaultExts |
- AArch64::ExtensionBitset({AArch64::AEK_RAS}))};
-inline constexpr ArchInfo ARMV8_3A = { VersionTuple{8, 3}, AProfile, "armv8.3-a", "+v8.3a", (ARMV8_2A.DefaultExts |
- AArch64::ExtensionBitset({AArch64::AEK_FCMA, AArch64::AEK_JSCVT, AArch64::AEK_PAUTH, AArch64::AEK_RCPC}))};
-inline constexpr ArchInfo ARMV8_4A = { VersionTuple{8, 4}, AProfile, "armv8.4-a", "+v8.4a", (ARMV8_3A.DefaultExts |
- AArch64::ExtensionBitset({AArch64::AEK_DOTPROD}))};
-inline constexpr ArchInfo ARMV8_5A = { VersionTuple{8, 5}, AProfile, "armv8.5-a", "+v8.5a", (ARMV8_4A.DefaultExts)};
-inline constexpr ArchInfo ARMV8_6A = { VersionTuple{8, 6}, AProfile, "armv8.6-a", "+v8.6a", (ARMV8_5A.DefaultExts |
- AArch64::ExtensionBitset({AArch64::AEK_BF16, AArch64::AEK_I8MM}))};
-inline constexpr ArchInfo ARMV8_7A = { VersionTuple{8, 7}, AProfile, "armv8.7-a", "+v8.7a", (ARMV8_6A.DefaultExts)};
-inline constexpr ArchInfo ARMV8_8A = { VersionTuple{8, 8}, AProfile, "armv8.8-a", "+v8.8a", (ARMV8_7A.DefaultExts |
- AArch64::ExtensionBitset({AArch64::AEK_MOPS, AArch64::AEK_HBC}))};
-inline constexpr ArchInfo ARMV8_9A = { VersionTuple{8, 9}, AProfile, "armv8.9-a", "+v8.9a", (ARMV8_8A.DefaultExts |
- AArch64::ExtensionBitset({AArch64::AEK_SPECRES2, AArch64::AEK_CSSC, AArch64::AEK_RASV2}))};
-inline constexpr ArchInfo ARMV9A = { VersionTuple{9, 0}, AProfile, "armv9-a", "+v9a", (ARMV8_5A.DefaultExts |
- AArch64::ExtensionBitset({AArch64::AEK_FP16, AArch64::AEK_SVE, AArch64::AEK_SVE2}))};
-inline constexpr ArchInfo ARMV9_1A = { VersionTuple{9, 1}, AProfile, "armv9.1-a", "+v9.1a", (ARMV9A.DefaultExts |
- AArch64::ExtensionBitset({AArch64::AEK_BF16, AArch64::AEK_I8MM}))};
-inline constexpr ArchInfo ARMV9_2A = { VersionTuple{9, 2}, AProfile, "armv9.2-a", "+v9.2a", (ARMV9_1A.DefaultExts)};
-inline constexpr ArchInfo ARMV9_3A = { VersionTuple{9, 3}, AProfile, "armv9.3-a", "+v9.3a", (ARMV9_2A.DefaultExts |
- AArch64::ExtensionBitset({AArch64::AEK_MOPS, AArch64::AEK_HBC}))};
-inline constexpr ArchInfo ARMV9_4A = { VersionTuple{9, 4}, AProfile, "armv9.4-a", "+v9.4a", (ARMV9_3A.DefaultExts |
- AArch64::ExtensionBitset({AArch64::AEK_SPECRES2, AArch64::AEK_CSSC, AArch64::AEK_RASV2}))};
-inline constexpr ArchInfo ARMV9_5A = { VersionTuple{9, 5}, AProfile, "armv9.5-a", "+v9.5a", (ARMV9_4A.DefaultExts |
- AArch64::ExtensionBitset({AArch64::AEK_CPA}))};
-// For v8-R, we do not enable crypto and align with GCC that enables a more minimal set of optional architecture extensions.
-inline constexpr ArchInfo ARMV8R = { VersionTuple{8, 0}, RProfile, "armv8-r", "+v8r", (ARMV8_5A.DefaultExts |
- AArch64::ExtensionBitset({AArch64::AEK_SSBS,
- AArch64::AEK_FP16, AArch64::AEK_FP16FML, AArch64::AEK_SB}).flip(AArch64::AEK_LSE))};
-// clang-format on
-
-// The set of all architectures
-static constexpr std::array<const ArchInfo *, 17> ArchInfos = {
- &ARMV8A, &ARMV8_1A, &ARMV8_2A, &ARMV8_3A, &ARMV8_4A, &ARMV8_5A,
- &ARMV8_6A, &ARMV8_7A, &ARMV8_8A, &ARMV8_9A, &ARMV9A, &ARMV9_1A,
- &ARMV9_2A, &ARMV9_3A, &ARMV9_4A, &ARMV9_5A, &ARMV8R,
-};
+#define EMIT_ARCHITECTURES
+#include "llvm/TargetParser/AArch64TargetParserDef.inc"
// Details of a specific CPU.
struct CpuInfo {
diff --git a/llvm/lib/Target/AArch64/AArch64Features.td b/llvm/lib/Target/AArch64/AArch64Features.td
index 920ca7f4fbfcb..e615ea9b1cede 100644
--- a/llvm/lib/Target/AArch64/AArch64Features.td
+++ b/llvm/lib/Target/AArch64/AArch64Features.td
@@ -787,90 +787,104 @@ def FeatureTLBIW : Extension<"tlbiw", "TLBIW",
//===----------------------------------------------------------------------===//
// Architectures.
//
-def HasV8_0aOps : SubtargetFeature<"v8a", "HasV8_0aOps", "true",
- "Support ARM v8.0a instructions", [FeatureEL2VMSA, FeatureEL3]>;
-
-def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
- "Support ARM v8.1a instructions", [HasV8_0aOps, FeatureCRC, FeatureLSE,
- FeatureRDM, FeaturePAN, FeatureLOR, FeatureVH]>;
-
-def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true",
- "Support ARM v8.2a instructions", [HasV8_1aOps, FeaturePsUAO,
- FeaturePAN_RWV, FeatureRAS, FeatureCCPP]>;
-
-def HasV8_3aOps : SubtargetFeature<"v8.3a", "HasV8_3aOps", "true",
- "Support ARM v8.3a instructions", [HasV8_2aOps, FeatureRCPC, FeaturePAuth,
- FeatureJS, FeatureCCIDX, FeatureComplxNum]>;
-
-def HasV8_4aOps : SubtargetFeature<"v8.4a", "HasV8_4aOps", "true",
- "Support ARM v8.4a instructions", [HasV8_3aOps, FeatureDotProd,
- FeatureNV, FeatureMPAM, FeatureDIT,
- FeatureTRACEV8_4, FeatureAM, FeatureSEL2, FeatureTLB_RMI,
- FeatureFlagM, FeatureRCPC_IMMO, FeatureLSE2]>;
+class Architecture64<
+ int major, int minor, string profile,
+ string target_feature_name,
+ list<SubtargetFeature> implied_features,
+ list<Extension> default_extensions
+> : SubtargetFeature<target_feature_name,
+ "HasV" # major # "_" # minor # profile # "Ops", "true",
+ "Support ARM " # target_feature_name # " architecture",
+ implied_features
+> {
+ int Major = major;
+ int Minor = minor;
+ string Profile = profile;
+
+ // Extensions enabled by default. Not the same as implied SubtargetFeatures.
+ list<Extension> DefaultExts = default_extensions;
+}
-def HasV8_5aOps : SubtargetFeature<
- "v8.5a", "HasV8_5aOps", "true", "Support ARM v8.5a instructions",
+def HasV8_0aOps : Architecture64<8, 0, "a", "v8a",
+ [FeatureEL2VMSA, FeatureEL3],
+ [FeatureFPARMv8, FeatureNEON]>;
+def HasV8_1aOps : Architecture64<8, 1, "a", "v8.1a",
+ [HasV8_0aOps, FeatureCRC, FeatureLSE, FeatureRDM, FeaturePAN, FeatureLOR,
+ FeatureVH],
+ !listconcat(HasV8_0aOps.DefaultExts, [FeatureCRC, FeatureLSE, FeatureRDM])>;
+def HasV8_2aOps : Architecture64<8, 2, "a", "v8.2a",
+ [HasV8_1aOps, FeaturePsUAO, FeaturePAN_RWV, FeatureRAS, FeatureCCPP],
+ !listconcat(HasV8_1aOps.DefaultExts, [FeatureRAS])>;
+def HasV8_3aOps : Architecture64<8, 3, "a", "v8.3a",
+ [HasV8_2aOps, FeatureRCPC, FeaturePAuth, FeatureJS, FeatureCCIDX,
+ FeatureComplxNum],
+ !listconcat(HasV8_2aOps.DefaultExts, [FeatureComplxNum, FeatureJS,
+ FeaturePAuth, FeatureRCPC])>;
+def HasV8_4aOps : Architecture64<8, 4, "a", "v8.4a",
+ [HasV8_3aOps, FeatureDotProd, FeatureNV, FeatureMPAM, FeatureDIT,
+ FeatureTRACEV8_4, FeatureAM, FeatureSEL2, FeatureTLB_RMI, FeatureFlagM,
+ FeatureRCPC_IMMO, FeatureLSE2],
+ !listconcat(HasV8_3aOps.DefaultExts, [FeatureDotProd])>;
+def HasV8_5aOps : Architecture64<8, 5, "a", "v8.5a",
[HasV8_4aOps, FeatureAltFPCmp, FeatureFRInt3264, FeatureSpecRestrict,
- FeatureSSBS, FeatureSB, FeaturePredRes, FeatureCacheDeepPersist,
- FeatureBranchTargetId]>;
-
-def HasV8_6aOps : SubtargetFeature<
- "v8.6a", "HasV8_6aOps", "true", "Support ARM v8.6a instructions",
+ FeatureSSBS, FeatureSB, FeaturePredRes, FeatureCacheDeepPersist,
+ FeatureBranchTargetId],
+ !listconcat(HasV8_4aOps.DefaultExts, [])>;
+def HasV8_6aOps : Architecture64<8, 6, "a", "v8.6a",
[HasV8_5aOps, FeatureAMVS, FeatureBF16, FeatureFineGrainedTraps,
- FeatureEnhancedCounterVirtualization, FeatureMatMulInt8]>;
-
-def HasV8_7aOps : SubtargetFeature<
- "v8.7a", "HasV8_7aOps", "true", "Support ARM v8.7a instructions",
- [HasV8_6aOps, FeatureXS, FeatureWFxT, FeatureHCX]>;
-
-def HasV8_8aOps : SubtargetFeature<
- "v8.8a", "HasV8_8aOps", "true", "Support ARM v8.8a instructions",
- [HasV8_7aOps, FeatureHBC, FeatureMOPS, FeatureNMI]>;
-
-def HasV8_9aOps : SubtargetFeature<
- "v8.9a", "HasV8_9aOps", "true", "Support ARM v8.9a instructions",
+ FeatureEnhancedCounterVirtualization, FeatureMatMulInt8],
+ !listconcat(HasV8_5aOps.DefaultExts, [FeatureBF16, FeatureMatMulInt8])>;
+def HasV8_7aOps : Architecture64<8, 7, "a", "v8.7a",
+ [HasV8_6aOps, FeatureXS, FeatureWFxT, FeatureHCX],
+ !listconcat(HasV8_6aOps.DefaultExts, [])>;
+def HasV8_8aOps : Architecture64<8, 8, "a", "v8.8a",
+ [HasV8_7aOps, FeatureHBC, FeatureMOPS, FeatureNMI],
+ !listconcat(HasV8_7aOps.DefaultExts, [FeatureMOPS, FeatureHBC])>;
+def HasV8_9aOps : Architecture64<8, 9, "a", "v8.9a",
[HasV8_8aOps, FeatureCLRBHB, FeaturePRFM_SLC, FeatureSPECRES2,
- FeatureCSSC, FeatureRASv2, FeatureCHK]>;
-
-def HasV9_0aOps : SubtargetFeature<
- "v9a", "HasV9_0aOps", "true", "Support ARM v9a instructions",
- [HasV8_5aOps, FeatureMEC, FeatureSVE2]>;
-
-def HasV9_1aOps : SubtargetFeature<
- "v9.1a", "HasV9_1aOps", "true", "Support ARM v9.1a instructions",
- [HasV8_6aOps, HasV9_0aOps]>;
-
-def HasV9_2aOps : SubtargetFeature<
- "v9.2a", "HasV9_2aOps", "true", "Support ARM v9.2a instructions",
- [HasV8_7aOps, HasV9_1aOps]>;
-
-def HasV9_3aOps : SubtargetFeature<
- "v9.3a", "HasV9_3aOps", "true", "Support ARM v9.3a instructions",
- [HasV8_8aOps, HasV9_2aOps]>;
-
-def HasV9_4aOps : SubtargetFeature<
- "v9.4a", "HasV9_4aOps", "true", "Support ARM v9.4a instructions",
- [HasV8_9aOps, HasV9_3aOps]>;
-
-def HasV9_5aOps : SubtargetFeature<
- "v9.5a", "HasV9_5aOps", "true", "Support ARM v9.5a instructions",
- [HasV9_4aOps, FeatureCPA]>;
-
-def HasV8_0rOps : SubtargetFeature<
- "v8r", "HasV8_0rOps", "true", "Support ARM v8r instructions",
- [//v8.1
- FeatureCRC, FeaturePAN, FeatureLSE, FeatureCONTEXTIDREL2,
- //v8.2
- FeatureRAS, FeaturePsUAO, FeatureCCPP, FeaturePAN_RWV,
- //v8.3
- FeatureCCIDX, FeaturePAuth, FeatureRCPC,
- //v8.4
- FeatureTRACEV8_4, FeatureTLB_RMI, FeatureFlagM, FeatureDIT, FeatureSEL2,
- FeatureRCPC_IMMO,
- // Not mandatory in v8.0-R, but included here on the grounds that it
- // only enables names of system registers
- FeatureSpecRestrict
- ]>;
+ FeatureCSSC, FeatureRASv2, FeatureCHK],
+ !listconcat(HasV8_8aOps.DefaultExts, [FeatureSPECRES2, FeatureCSSC,
+ FeatureRASv2])>;
+def HasV9_0aOps : Architecture64<9, 0, "a", "v9a",
+ [HasV8_5aOps, FeatureMEC, FeatureSVE2],
+ !listconcat(HasV8_5aOps.DefaultExts, [FeatureFullFP16, FeatureSVE,
+ FeatureSVE2])>;
+def HasV9_1aOps : Architecture64<9, 1, "a", "v9.1a",
+ [HasV8_6aOps, HasV9_0aOps],
+ !listconcat(HasV9_0aOps.DefaultExts, [FeatureBF16, FeatureMatMulInt8])>;
+def HasV9_2aOps : Architecture64<9, 2, "a", "v9.2a",
+ [HasV8_7aOps, HasV9_1aOps],
+ !listconcat(HasV9_1aOps.DefaultExts, [])>;
+def HasV9_3aOps : Architecture64<9, 3, "a", "v9.3a",
+ [HasV8_8aOps, HasV9_2aOps],
+ !listconcat(HasV9_2aOps.DefaultExts, [FeatureMOPS, FeatureHBC])>;
+def HasV9_4aOps : Architecture64<9, 4, "a", "v9.4a",
+ [HasV8_9aOps, HasV9_3aOps],
+ !listconcat(HasV9_3aOps.DefaultExts, [FeatureSPECRES2, FeatureCSSC,
+ FeatureRASv2])>;
+def HasV9_5aOps : Architecture64<9, 5, "a", "v9.5a",
+ [HasV9_4aOps, FeatureCPA],
+ !listconcat(HasV9_4aOps.DefaultExts, [FeatureCPA])>;
+def HasV8_0rOps : Architecture64<8, 0, "r", "v8r",
+ [ //v8.1
+ FeatureCRC, FeaturePAN, FeatureLSE, FeatureCONTEXTIDREL2,
+ //v8.2
+ FeatureRAS, FeaturePsUAO, FeatureCCPP, FeaturePAN_RWV,
+ //v8.3
+ FeatureCCIDX, FeaturePAuth, FeatureRCPC,
+ //v8.4
+ FeatureTRACEV8_4, FeatureTLB_RMI, FeatureFlagM, FeatureDIT, FeatureSEL2,
+ FeatureRCPC_IMMO,
+ // Not mandatory in v8.0-R, but included here on the grounds that it
+ // only enables names of system registers
+ FeatureSpecRestrict
+ ],
+ // For v8-R, we do not enable crypto and align with GCC that enables a more
+ // minimal set of optional architecture extensions.
+ !listconcat(
+ !listremove(HasV8_5aOps.DefaultExts, [FeatureLSE]),
+ [FeatureSSBS, FeatureFullFP16, FeatureFP16FML, FeatureSB]
+ )>;
//===----------------------------------------------------------------------===//
// Access to privileged registers
diff --git a/llvm/utils/TableGen/ARMTargetDefEmitter.cpp b/llvm/utils/TableGen/ARMTargetDefEmitter.cpp
index 4a46f2ea95869..70050020865e0 100644
--- a/llvm/utils/TableGen/ARMTargetDefEmitter.cpp
+++ b/llvm/utils/TableGen/ARMTargetDefEmitter.cpp
@@ -13,9 +13,12 @@
//===----------------------------------------------------------------------===//
#include "llvm/ADT/StringSet.h"
+#include "llvm/Support/Format.h"
+#include "llvm/TableGen/Error.h"
#include "llvm/TableGen/Record.h"
#include "llvm/TableGen/TableGenBackend.h"
#include <cstdint>
+#include <string>
using namespace llvm;
@@ -108,6 +111,68 @@ static void EmitARMTargetDef(RecordKeeper &RK, raw_ostream &OS) {
<< "#undef EMIT_EXTENSIONS\n"
<< "#endif // EMIT_EXTENSIONS\n"
<< "\n";
+
+ // Emit architecture information
+ OS << "#ifdef EMIT_ARCHITECTURES\n";
+
+ auto Architectures = RK.getAllDerivedDefinitionsIfDefined("Architecture64");
+ std::vector<std::string> CppSpellings;
+ for (const Record *Rec : Architectures) {
+ const int Major = Rec->getValueAsInt("Major");
+ const int Minor = Rec->getValueAsInt("Minor");
+ const std::string ProfileLower = Rec->getValueAsString("Profile").str();
+ const std::string ProfileUpper = Rec->getValueAsString("Profile").upper();
+
+ if (ProfileLower != "a" && ProfileLower != "r")
+ PrintFatalError(Rec->getLoc(),
+ "error: Profile must be one of 'a' or 'r', got '" +
+ ProfileLower + "'");
+
+ // Name of the object in C++
+ const std::string CppSpelling =
+ Minor == 0 ? "ARMV" + std::to_string(Major) + ProfileUpper.c_str()
+ : "ARMV" + std::to_string(Major) + "_" +
+ std::to_string(Minor) + ProfileUpper.c_str();
+ OS << "inline constexpr ArchInfo " << CppSpelling << " = {\n";
+ CppSpellings.push_back(CppSpelling);
+
+ OS << llvm::format(" VersionTuple{%d, %d},\n", Major, Minor);
+ OS << llvm::format(" %sProfile,\n", ProfileUpper.c_str());
+
+ // Name as spelled for -march.
+ if (Minor == 0)
+ OS << llvm::format(" \"armv%d-%s\",\n", Major, ProfileLower.c_str());
+ else
+ OS << llvm::format(" \"armv%d.%d-%s\",\n", Major, Minor,
+ ProfileLower.c_str());
+
+ // SubtargetFeature::Name, used for -target-feature. Here the "+" is added.
+ const auto TargetFeatureName = Rec->getValueAsString("Name");
+ OS << " \"+" << TargetFeatureName << "\",\n";
+
+ // Construct the list of default extensions
+ OS << " (AArch64::ExtensionBitset({";
+ for (auto *E : Rec->getValueAsListOfDefs("DefaultExts")) {
+ // Only process subclasses of Extension
+ OS << "AArch64::" << E->getValueAsString("ArchExtKindSpelling").upper()
+ << ", ";
+ }
+ OS << "}))\n";
+
+ OS << "};\n";
+ }
+
+ OS << "\n"
+ << "/// The set of all architectures\n"
+ << "static constexpr std::array<const ArchInfo *, " << CppSpellings.size()
+ << "> ArchInfos = {\n";
+ for (auto CppSpelling : CppSpellings)
+ OS << " &" << CppSpelling << ",\n";
+ OS << "};\n";
+
+ OS << "#undef EMIT_ARCHITECTURES\n"
+ << "#endif // EMIT_ARCHITECTURES\n"
+ << "\n";
}
static TableGen::Emitter::Opt
>From 52b8af6cde23d6ceacbc33f292e0bff1265501b5 Mon Sep 17 00:00:00 2001
From: Tomas Matheson <tomas.matheson at arm.com>
Date: Tue, 14 May 2024 17:20:45 +0100
Subject: [PATCH 2/2] [AArch64][TargetParser] move CPUInfo into tablegen
---
.../llvm/TargetParser/AArch64TargetParser.h | 319 +-------------
llvm/lib/Target/AArch64/AArch64Processors.td | 399 +++++++++++-------
llvm/utils/TableGen/ARMTargetDefEmitter.cpp | 41 +-
3 files changed, 285 insertions(+), 474 deletions(-)
diff --git a/llvm/include/llvm/TargetParser/AArch64TargetParser.h b/llvm/include/llvm/TargetParser/AArch64TargetParser.h
index 0c89b7859975c..2402f02ab99c1 100644
--- a/llvm/include/llvm/TargetParser/AArch64TargetParser.h
+++ b/llvm/include/llvm/TargetParser/AArch64TargetParser.h
@@ -307,323 +307,8 @@ struct CpuInfo {
}
};
-inline constexpr CpuInfo CpuInfos[] = {
- {"cortex-a34", ARMV8A,
- AArch64::ExtensionBitset(
- {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_CRC})},
- {"cortex-a35", ARMV8A,
- AArch64::ExtensionBitset(
- {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_CRC})},
- {"cortex-a53", ARMV8A,
- AArch64::ExtensionBitset(
- {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_CRC})},
- {"cortex-a55", ARMV8_2A,
- AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2,
- AArch64::AEK_FP16, AArch64::AEK_DOTPROD,
- AArch64::AEK_RCPC})},
- {"cortex-a510", ARMV9A,
- AArch64::ExtensionBitset(
- {AArch64::AEK_BF16, AArch64::AEK_I8MM, AArch64::AEK_SB,
- AArch64::AEK_PAUTH, AArch64::AEK_MTE, AArch64::AEK_SSBS,
- AArch64::AEK_SVE, AArch64::AEK_SVE2, AArch64::AEK_SVE2BITPERM,
- AArch64::AEK_FP16FML})},
- {"cortex-a520", ARMV9_2A,
- AArch64::ExtensionBitset(
- {AArch64::AEK_SB, AArch64::AEK_SSBS, AArch64::AEK_MTE,
- AArch64::AEK_FP16FML, AArch64::AEK_PAUTH, AArch64::AEK_SVE2BITPERM,
- AArch64::AEK_FLAGM, AArch64::AEK_PERFMON, AArch64::AEK_PREDRES})},
- {"cortex-a520ae", ARMV9_2A,
- AArch64::ExtensionBitset(
- {AArch64::AEK_SB, AArch64::AEK_SSBS, AArch64::AEK_MTE,
- AArch64::AEK_FP16FML, AArch64::AEK_PAUTH, AArch64::AEK_SVE2BITPERM,
- AArch64::AEK_FLAGM, AArch64::AEK_PERFMON, AArch64::AEK_PREDRES})},
- {"cortex-a57", ARMV8A,
- AArch64::ExtensionBitset(
- {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_CRC})},
- {"cortex-a65", ARMV8_2A,
- AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2,
- AArch64::AEK_DOTPROD, AArch64::AEK_FP16,
- AArch64::AEK_RCPC, AArch64::AEK_SSBS})},
- {"cortex-a65ae", ARMV8_2A,
- AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2,
- AArch64::AEK_DOTPROD, AArch64::AEK_FP16,
- AArch64::AEK_RCPC, AArch64::AEK_SSBS})},
- {"cortex-a72", ARMV8A,
- AArch64::ExtensionBitset(
- {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_CRC})},
- {"cortex-a73", ARMV8A,
- AArch64::ExtensionBitset(
- {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_CRC})},
- {"cortex-a75", ARMV8_2A,
- AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2,
- AArch64::AEK_FP16, AArch64::AEK_DOTPROD,
- AArch64::AEK_RCPC})},
- {"cortex-a76", ARMV8_2A,
- AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2,
- AArch64::AEK_FP16, AArch64::AEK_DOTPROD,
- AArch64::AEK_RCPC, AArch64::AEK_SSBS})},
- {"cortex-a76ae", ARMV8_2A,
- AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2,
- AArch64::AEK_FP16, AArch64::AEK_DOTPROD,
- AArch64::AEK_RCPC, AArch64::AEK_SSBS})},
- {"cortex-a77", ARMV8_2A,
- AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2,
- AArch64::AEK_FP16, AArch64::AEK_RCPC,
- AArch64::AEK_DOTPROD, AArch64::AEK_SSBS})},
- {"cortex-a78", ARMV8_2A,
- AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2,
- AArch64::AEK_FP16, AArch64::AEK_DOTPROD,
- AArch64::AEK_RCPC, AArch64::AEK_SSBS,
- AArch64::AEK_PROFILE})},
- {"cortex-a78ae", ARMV8_2A,
- AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2,
- AArch64::AEK_FP16, AArch64::AEK_DOTPROD,
- AArch64::AEK_RCPC, AArch64::AEK_SSBS,
- AArch64::AEK_PROFILE})},
- {"cortex-a78c", ARMV8_2A,
- AArch64::ExtensionBitset(
- {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_FP16,
- AArch64::AEK_DOTPROD, AArch64::AEK_RCPC, AArch64::AEK_SSBS,
- AArch64::AEK_PROFILE, AArch64::AEK_FLAGM, AArch64::AEK_PAUTH})},
- {"cortex-a710", ARMV9A,
- AArch64::ExtensionBitset({AArch64::AEK_MTE, AArch64::AEK_PAUTH,
- AArch64::AEK_FLAGM, AArch64::AEK_SB,
- AArch64::AEK_I8MM, AArch64::AEK_FP16FML,
- AArch64::AEK_SVE, AArch64::AEK_SVE2,
- AArch64::AEK_SVE2BITPERM, AArch64::AEK_BF16})},
- {"cortex-a715", ARMV9A,
- AArch64::ExtensionBitset(
- {AArch64::AEK_SB, AArch64::AEK_SSBS, AArch64::AEK_MTE,
- AArch64::AEK_FP16, AArch64::AEK_FP16FML, AArch64::AEK_PAUTH,
- AArch64::AEK_I8MM, AArch64::AEK_PREDRES, AArch64::AEK_PERFMON,
- AArch64::AEK_PROFILE, AArch64::AEK_SVE, AArch64::AEK_SVE2BITPERM,
- AArch64::AEK_BF16, AArch64::AEK_FLAGM})},
- {"cortex-a720", ARMV9_2A,
- AArch64::ExtensionBitset({AArch64::AEK_SB, AArch64::AEK_SSBS,
- AArch64::AEK_MTE, AArch64::AEK_FP16FML,
- AArch64::AEK_PAUTH, AArch64::AEK_SVE2BITPERM,
- AArch64::AEK_FLAGM, AArch64::AEK_PERFMON,
- AArch64::AEK_PREDRES, AArch64::AEK_PROFILE})},
- {"cortex-a720ae", ARMV9_2A,
- AArch64::ExtensionBitset({AArch64::AEK_SB, AArch64::AEK_SSBS,
- AArch64::AEK_MTE, AArch64::AEK_FP16FML,
- AArch64::AEK_PAUTH, AArch64::AEK_SVE2BITPERM,
- AArch64::AEK_FLAGM, AArch64::AEK_PERFMON,
- AArch64::AEK_PREDRES, AArch64::AEK_PROFILE})},
- {"cortex-r82", ARMV8R,
- AArch64::ExtensionBitset({AArch64::AEK_LSE, AArch64::AEK_FLAGM,
- AArch64::AEK_PERFMON, AArch64::AEK_PREDRES})},
- {"cortex-r82ae", ARMV8R,
- AArch64::ExtensionBitset({AArch64::AEK_LSE, AArch64::AEK_FLAGM,
- AArch64::AEK_PERFMON, AArch64::AEK_PREDRES})},
- {"cortex-x1", ARMV8_2A,
- AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2,
- AArch64::AEK_FP16, AArch64::AEK_DOTPROD,
- AArch64::AEK_RCPC, AArch64::AEK_SSBS,
- AArch64::AEK_PROFILE})},
- {"cortex-x1c", ARMV8_2A,
- AArch64::ExtensionBitset(
- {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_FP16,
- AArch64::AEK_DOTPROD, AArch64::AEK_RCPC, AArch64::AEK_SSBS,
- AArch64::AEK_PAUTH, AArch64::AEK_PROFILE, AArch64::AEK_FLAGM})},
- {"cortex-x2", ARMV9A,
- AArch64::ExtensionBitset(
- {AArch64::AEK_MTE, AArch64::AEK_BF16, AArch64::AEK_I8MM,
- AArch64::AEK_PAUTH, AArch64::AEK_SSBS, AArch64::AEK_SB,
- AArch64::AEK_SVE, AArch64::AEK_SVE2, AArch64::AEK_SVE2BITPERM,
- AArch64::AEK_FP16FML, AArch64::AEK_FLAGM})},
- {"cortex-x3", ARMV9A,
- AArch64::ExtensionBitset(
- {AArch64::AEK_SVE, AArch64::AEK_PERFMON, AArch64::AEK_PROFILE,
- AArch64::AEK_BF16, AArch64::AEK_I8MM, AArch64::AEK_MTE,
- AArch64::AEK_SVE2BITPERM, AArch64::AEK_SB, AArch64::AEK_PAUTH,
- AArch64::AEK_FP16, AArch64::AEK_FP16FML, AArch64::AEK_PREDRES,
- AArch64::AEK_FLAGM, AArch64::AEK_SSBS})},
- {"cortex-x4", ARMV9_2A,
- AArch64::ExtensionBitset({AArch64::AEK_SB, AArch64::AEK_SSBS,
- AArch64::AEK_MTE, AArch64::AEK_FP16FML,
- AArch64::AEK_PAUTH, AArch64::AEK_SVE2BITPERM,
- AArch64::AEK_FLAGM, AArch64::AEK_PERFMON,
- AArch64::AEK_PREDRES, AArch64::AEK_PROFILE})},
- {"neoverse-e1", ARMV8_2A,
- AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2,
- AArch64::AEK_DOTPROD, AArch64::AEK_FP16,
- AArch64::AEK_RCPC, AArch64::AEK_SSBS})},
- {"neoverse-n1", ARMV8_2A,
- AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2,
- AArch64::AEK_DOTPROD, AArch64::AEK_FP16,
- AArch64::AEK_PROFILE, AArch64::AEK_RCPC,
- AArch64::AEK_SSBS})},
- {"neoverse-n2", ARMV9A,
- AArch64::ExtensionBitset(
- {AArch64::AEK_BF16, AArch64::AEK_DOTPROD, AArch64::AEK_FP16,
- AArch64::AEK_FP16FML, AArch64::AEK_I8MM, AArch64::AEK_MTE,
- AArch64::AEK_SB, AArch64::AEK_SSBS, AArch64::AEK_SVE,
- AArch64::AEK_SVE2, AArch64::AEK_SVE2BITPERM})},
- {"neoverse-n3", ARMV9_2A,
- AArch64::ExtensionBitset({AArch64::AEK_MTE, AArch64::AEK_SSBS,
- AArch64::AEK_SB, AArch64::AEK_PREDRES,
- AArch64::AEK_FP16FML, AArch64::AEK_PAUTH,
- AArch64::AEK_FLAGM, AArch64::AEK_PERFMON,
- AArch64::AEK_RAND, AArch64::AEK_SVE2BITPERM,
- AArch64::AEK_PROFILE, AArch64::AEK_PERFMON})},
- {"neoverse-512tvb", ARMV8_4A,
- AArch64::ExtensionBitset(
- {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_SHA3,
- AArch64::AEK_SM4, AArch64::AEK_SVE, AArch64::AEK_SSBS,
- AArch64::AEK_FP16, AArch64::AEK_BF16, AArch64::AEK_DOTPROD,
- AArch64::AEK_PROFILE, AArch64::AEK_RAND, AArch64::AEK_FP16FML,
- AArch64::AEK_I8MM})},
- {"neoverse-v1", ARMV8_4A,
- AArch64::ExtensionBitset(
- {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_SHA3,
- AArch64::AEK_SM4, AArch64::AEK_SVE, AArch64::AEK_SSBS,
- AArch64::AEK_FP16, AArch64::AEK_BF16, AArch64::AEK_DOTPROD,
- AArch64::AEK_PROFILE, AArch64::AEK_RAND, AArch64::AEK_FP16FML,
- AArch64::AEK_I8MM})},
- {"neoverse-v2", ARMV9A,
- AArch64::ExtensionBitset(
- {AArch64::AEK_SVE, AArch64::AEK_SVE2, AArch64::AEK_SSBS,
- AArch64::AEK_FP16, AArch64::AEK_BF16, AArch64::AEK_RAND,
- AArch64::AEK_DOTPROD, AArch64::AEK_PROFILE, AArch64::AEK_SVE2BITPERM,
- AArch64::AEK_FP16FML, AArch64::AEK_I8MM, AArch64::AEK_MTE})},
- {"neoverse-v3", ARMV9_2A,
- AArch64::ExtensionBitset(
- {AArch64::AEK_PROFILE, AArch64::AEK_MTE, AArch64::AEK_SSBS,
- AArch64::AEK_SB, AArch64::AEK_PREDRES, AArch64::AEK_LS64,
- AArch64::AEK_BRBE, AArch64::AEK_PAUTH, AArch64::AEK_FLAGM,
- AArch64::AEK_PERFMON, AArch64::AEK_RAND, AArch64::AEK_SVE2BITPERM,
- AArch64::AEK_FP16FML})},
- {"neoverse-v3ae", ARMV9_2A,
- (AArch64::ExtensionBitset(
- {AArch64::AEK_PROFILE, AArch64::AEK_MTE, AArch64::AEK_SSBS,
- AArch64::AEK_SB, AArch64::AEK_PREDRES, AArch64::AEK_LS64,
- AArch64::AEK_BRBE, AArch64::AEK_PAUTH, AArch64::AEK_FLAGM,
- AArch64::AEK_PERFMON, AArch64::AEK_RAND, AArch64::AEK_SVE2BITPERM,
- AArch64::AEK_FP16FML}))},
- {"cyclone", ARMV8A,
- AArch64::ExtensionBitset(
- {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_NONE})},
- {"apple-a7", ARMV8A,
- AArch64::ExtensionBitset(
- {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_NONE})},
- {"apple-a8", ARMV8A,
- AArch64::ExtensionBitset(
- {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_NONE})},
- {"apple-a9", ARMV8A,
- AArch64::ExtensionBitset(
- {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_NONE})},
- {"apple-a10", ARMV8A,
- AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2,
- AArch64::AEK_CRC, AArch64::AEK_RDM})},
- {"apple-a11", ARMV8_2A,
- AArch64::ExtensionBitset(
- {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_FP16})},
- {"apple-a12", ARMV8_3A,
- AArch64::ExtensionBitset(
- {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_FP16})},
- {"apple-a13", ARMV8_4A,
- AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2,
- AArch64::AEK_SHA3, AArch64::AEK_FP16,
- AArch64::AEK_FP16FML})},
- {"apple-a14", ARMV8_5A,
- AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2,
- AArch64::AEK_SHA3, AArch64::AEK_FP16,
- AArch64::AEK_FP16FML})},
- {"apple-a15", ARMV8_6A,
- AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2,
- AArch64::AEK_SHA3, AArch64::AEK_FP16,
- AArch64::AEK_FP16FML})},
- {"apple-a16", ARMV8_6A,
- AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2,
- AArch64::AEK_SHA3, AArch64::AEK_FP16,
- AArch64::AEK_FP16FML})},
- {"apple-a17", ARMV8_6A,
- AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2,
- AArch64::AEK_SHA3, AArch64::AEK_FP16,
- AArch64::AEK_FP16FML})},
-
- {"apple-m1", ARMV8_5A,
- AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2,
- AArch64::AEK_SHA3, AArch64::AEK_FP16,
- AArch64::AEK_FP16FML})},
- {"apple-m2", ARMV8_6A,
- AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2,
- AArch64::AEK_SHA3, AArch64::AEK_FP16,
- AArch64::AEK_FP16FML})},
- {"apple-m3", ARMV8_6A,
- AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2,
- AArch64::AEK_SHA3, AArch64::AEK_FP16,
- AArch64::AEK_FP16FML})},
-
- {"apple-s4", ARMV8_3A,
- AArch64::ExtensionBitset(
- {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_FP16})},
- {"apple-s5", ARMV8_3A,
- AArch64::ExtensionBitset(
- {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_FP16})},
- {"exynos-m3", ARMV8A,
- AArch64::ExtensionBitset(
- {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_CRC})},
- {"exynos-m4", ARMV8_2A,
- AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2,
- AArch64::AEK_DOTPROD, AArch64::AEK_FP16})},
- {"exynos-m5", ARMV8_2A,
- AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2,
- AArch64::AEK_DOTPROD, AArch64::AEK_FP16})},
- {"falkor", ARMV8A,
- AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2,
- AArch64::AEK_CRC, AArch64::AEK_RDM})},
- {"saphira", ARMV8_3A,
- AArch64::ExtensionBitset(
- {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_PROFILE})},
- {"kryo", ARMV8A,
- AArch64::ExtensionBitset(
- {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_CRC})},
- {"thunderx2t99", ARMV8_1A,
- AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2})},
- {"thunderx3t110", ARMV8_3A,
- AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2})},
- {"thunderx", ARMV8A,
- AArch64::ExtensionBitset(
- {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_CRC})},
- {"thunderxt88", ARMV8A,
- AArch64::ExtensionBitset(
- {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_CRC})},
- {"thunderxt81", ARMV8A,
- AArch64::ExtensionBitset(
- {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_CRC})},
- {"thunderxt83", ARMV8A,
- AArch64::ExtensionBitset(
- {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_CRC})},
- {"tsv110", ARMV8_2A,
- AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2,
- AArch64::AEK_DOTPROD, AArch64::AEK_FP16,
- AArch64::AEK_FP16FML, AArch64::AEK_PROFILE,
- AArch64::AEK_JSCVT, AArch64::AEK_FCMA})},
- {"a64fx", ARMV8_2A,
- AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2,
- AArch64::AEK_FP16, AArch64::AEK_SVE})},
- {"carmel", ARMV8_2A,
- AArch64::ExtensionBitset(
- {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_FP16})},
- {"ampere1", ARMV8_6A,
- AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2,
- AArch64::AEK_SHA3, AArch64::AEK_FP16,
- AArch64::AEK_SB, AArch64::AEK_SSBS,
- AArch64::AEK_RAND})},
- {"ampere1a", ARMV8_6A,
- AArch64::ExtensionBitset(
- {AArch64::AEK_FP16, AArch64::AEK_RAND, AArch64::AEK_SM4,
- AArch64::AEK_SHA3, AArch64::AEK_SHA2, AArch64::AEK_AES,
- AArch64::AEK_MTE, AArch64::AEK_SB, AArch64::AEK_SSBS})},
- {"ampere1b", ARMV8_7A,
- AArch64::ExtensionBitset({AArch64::AEK_FP16, AArch64::AEK_RAND,
- AArch64::AEK_SM4, AArch64::AEK_SHA3,
- AArch64::AEK_SHA2, AArch64::AEK_AES,
- AArch64::AEK_MTE, AArch64::AEK_SB,
- AArch64::AEK_SSBS, AArch64::AEK_CSSC})},
-};
+#define EMIT_CPU_INFO
+#include "llvm/TargetParser/AArch64TargetParserDef.inc"
// Name alias.
struct Alias {
diff --git a/llvm/lib/Target/AArch64/AArch64Processors.td b/llvm/lib/Target/AArch64/AArch64Processors.td
index f2286ae17dba5..638033a89b9a0 100644
--- a/llvm/lib/Target/AArch64/AArch64Processors.td
+++ b/llvm/lib/Target/AArch64/AArch64Processors.td
@@ -812,178 +812,271 @@ def ProcessorFeatures {
list<SubtargetFeature> Generic = [FeatureFPARMv8, FeatureNEON, FeatureETE];
}
+class AArch64Processor<
+ string n,
+ Architecture64 arch,
+ SchedMachineModel m,
+ list<SubtargetFeature> f,
+ list<SubtargetFeature> tunef,
+ list<Extension> default_extensions
+> : ProcessorModel<n, m, f, tunef> {
+ // The base architecture for this processor.
+ Architecture64 Arch = arch;
+
+ // The set of extensions enabled by default for this processor.
+ list<Extension> DefaultExts = default_extensions;
+}
+
// FeatureFuseAdrpAdd is enabled under Generic to allow linker merging
// optimizations.
-def : ProcessorModel<"generic", CortexA510Model, ProcessorFeatures.Generic,
+def : AArch64Processor<"generic", HasV9_0aOps, CortexA510Model, ProcessorFeatures.Generic,
[FeatureFuseAES, FeatureFuseAdrpAdd, FeaturePostRAScheduler,
- FeatureEnableSelectOptimize]>;
-def : ProcessorModel<"cortex-a35", CortexA53Model, ProcessorFeatures.A53,
- [TuneA35]>;
-def : ProcessorModel<"cortex-a34", CortexA53Model, ProcessorFeatures.A53,
- [TuneA35]>;
-def : ProcessorModel<"cortex-a53", CortexA53Model, ProcessorFeatures.A53,
- [TuneA53]>;
-def : ProcessorModel<"cortex-a55", CortexA55Model, ProcessorFeatures.A55,
- [TuneA55]>;
-def : ProcessorModel<"cortex-a510", CortexA510Model, ProcessorFeatures.A510,
- [TuneA510]>;
-def : ProcessorModel<"cortex-a520", CortexA510Model, ProcessorFeatures.A520,
- [TuneA520]>;
-def : ProcessorModel<"cortex-a520ae", CortexA510Model, ProcessorFeatures.A520AE,
- [TuneA520AE]>;
-def : ProcessorModel<"cortex-a57", CortexA57Model, ProcessorFeatures.A53,
- [TuneA57]>;
-def : ProcessorModel<"cortex-a65", CortexA53Model, ProcessorFeatures.A65,
- [TuneA65]>;
-def : ProcessorModel<"cortex-a65ae", CortexA53Model, ProcessorFeatures.A65,
- [TuneA65]>;
-def : ProcessorModel<"cortex-a72", CortexA57Model, ProcessorFeatures.A53,
- [TuneA72]>;
-def : ProcessorModel<"cortex-a73", CortexA57Model, ProcessorFeatures.A53,
- [TuneA73]>;
-def : ProcessorModel<"cortex-a75", CortexA57Model, ProcessorFeatures.A55,
- [TuneA75]>;
-def : ProcessorModel<"cortex-a76", CortexA57Model, ProcessorFeatures.A76,
- [TuneA76]>;
-def : ProcessorModel<"cortex-a76ae", CortexA57Model, ProcessorFeatures.A76,
- [TuneA76]>;
-def : ProcessorModel<"cortex-a77", CortexA57Model, ProcessorFeatures.A77,
- [TuneA77]>;
-def : ProcessorModel<"cortex-a78", CortexA57Model, ProcessorFeatures.A78,
- [TuneA78]>;
-def : ProcessorModel<"cortex-a78ae", CortexA57Model, ProcessorFeatures.A78AE,
- [TuneA78AE]>;
-def : ProcessorModel<"cortex-a78c", CortexA57Model, ProcessorFeatures.A78C,
- [TuneA78C]>;
-def : ProcessorModel<"cortex-a710", NeoverseN2Model, ProcessorFeatures.A710,
- [TuneA710]>;
-def : ProcessorModel<"cortex-a715", NeoverseN2Model, ProcessorFeatures.A715,
- [TuneA715]>;
-def : ProcessorModel<"cortex-a720", NeoverseN2Model, ProcessorFeatures.A720,
- [TuneA720]>;
-def : ProcessorModel<"cortex-a720ae", NeoverseN2Model, ProcessorFeatures.A720AE,
- [TuneA720AE]>;
-def : ProcessorModel<"cortex-r82", CortexA55Model, ProcessorFeatures.R82,
- [TuneR82]>;
-def : ProcessorModel<"cortex-r82ae", CortexA55Model, ProcessorFeatures.R82AE,
- [TuneR82AE]>;
-def : ProcessorModel<"cortex-x1", CortexA57Model, ProcessorFeatures.X1,
- [TuneX1]>;
-def : ProcessorModel<"cortex-x1c", CortexA57Model, ProcessorFeatures.X1C,
- [TuneX1]>;
-def : ProcessorModel<"cortex-x2", NeoverseN2Model, ProcessorFeatures.X2,
- [TuneX2]>;
-def : ProcessorModel<"cortex-x3", NeoverseN2Model, ProcessorFeatures.X3,
- [TuneX3]>;
-def : ProcessorModel<"cortex-x4", NeoverseN2Model, ProcessorFeatures.X4,
- [TuneX4]>;
-def : ProcessorModel<"neoverse-e1", CortexA53Model,
- ProcessorFeatures.NeoverseE1, [TuneNeoverseE1]>;
-def : ProcessorModel<"neoverse-n1", NeoverseN1Model,
- ProcessorFeatures.NeoverseN1, [TuneNeoverseN1]>;
-def : ProcessorModel<"neoverse-n2", NeoverseN2Model,
- ProcessorFeatures.NeoverseN2, [TuneNeoverseN2]>;
-def : ProcessorModel<"neoverse-n3", NeoverseN2Model,
- ProcessorFeatures.NeoverseN3, [TuneNeoverseN3]>;
-def : ProcessorModel<"neoverse-512tvb", NeoverseV1Model,
- ProcessorFeatures.Neoverse512TVB, [TuneNeoverse512TVB]>;
-def : ProcessorModel<"neoverse-v1", NeoverseV1Model,
- ProcessorFeatures.NeoverseV1, [TuneNeoverseV1]>;
-def : ProcessorModel<"neoverse-v2", NeoverseV2Model,
- ProcessorFeatures.NeoverseV2, [TuneNeoverseV2]>;
-def : ProcessorModel<"neoverse-v3", NeoverseV2Model,
- ProcessorFeatures.NeoverseV3, [TuneNeoverseV3]>;
-def : ProcessorModel<"neoverse-v3ae", NeoverseV2Model,
- ProcessorFeatures.NeoverseV3AE, [TuneNeoverseV3AE]>;
-def : ProcessorModel<"exynos-m3", ExynosM3Model, ProcessorFeatures.ExynosM3,
- [TuneExynosM3]>;
-def : ProcessorModel<"exynos-m4", ExynosM4Model, ProcessorFeatures.ExynosM4,
- [TuneExynosM4]>;
-def : ProcessorModel<"exynos-m5", ExynosM5Model, ProcessorFeatures.ExynosM4,
- [TuneExynosM4]>;
-def : ProcessorModel<"falkor", FalkorModel, ProcessorFeatures.Falkor,
- [TuneFalkor]>;
-def : ProcessorModel<"saphira", FalkorModel, ProcessorFeatures.Saphira,
- [TuneSaphira]>;
-def : ProcessorModel<"kryo", KryoModel, ProcessorFeatures.A53, [TuneKryo]>;
+ FeatureEnableSelectOptimize],
+ [/*FIXME what are the default features for generic?*/]>;
+
+// Alias for the latest Apple processor model supported by LLVM.
+def : ProcessorModel<"apple-latest", CycloneModel, ProcessorFeatures.AppleA16,
+ [TuneAppleA16]>;
+
+def : AArch64Processor<"cortex-a34", HasV8_0aOps, CortexA53Model, ProcessorFeatures.A53,
+ [TuneA35],
+ [FeatureAES, FeatureSHA2, FeatureCRC]>;
+def : AArch64Processor<"cortex-a35", HasV8_0aOps, CortexA53Model, ProcessorFeatures.A53,
+ [TuneA35],
+ [FeatureAES, FeatureSHA2, FeatureCRC]>;
+def : AArch64Processor<"cortex-a53", HasV8_0aOps, CortexA53Model, ProcessorFeatures.A53,
+ [TuneA53],
+ [FeatureAES, FeatureSHA2, FeatureCRC]>;
+def : AArch64Processor<"cortex-a55", HasV8_2aOps, CortexA55Model, ProcessorFeatures.A55,
+ [TuneA55],
+ [FeatureAES, FeatureSHA2, FeatureFullFP16, FeatureDotProd, FeatureRCPC]>;
+def : AArch64Processor<"cortex-a510", HasV9_0aOps, CortexA510Model, ProcessorFeatures.A510,
+ [TuneA510],
+ [FeatureBF16, FeatureMatMulInt8, FeatureSB, FeaturePAuth, FeatureMTE, FeatureSSBS, FeatureSVE, FeatureSVE2, FeatureSVE2BitPerm, FeatureFP16FML]>;
+def : AArch64Processor<"cortex-a520", HasV9_2aOps, CortexA510Model, ProcessorFeatures.A520,
+ [TuneA520],
+ [FeatureSB, FeatureSSBS, FeatureMTE, FeatureFP16FML, FeaturePAuth, FeatureSVE2BitPerm, FeatureFlagM, FeaturePerfMon, FeaturePredRes]>;
+def : AArch64Processor<"cortex-a520ae", HasV9_2aOps, CortexA510Model, ProcessorFeatures.A520AE,
+ [TuneA520AE],
+ [FeatureSB, FeatureSSBS, FeatureMTE, FeatureFP16FML, FeaturePAuth, FeatureSVE2BitPerm, FeatureFlagM, FeaturePerfMon, FeaturePredRes]>;
+def : AArch64Processor<"cortex-a57", HasV8_0aOps, CortexA57Model, ProcessorFeatures.A53,
+ [TuneA57],
+ [FeatureAES, FeatureSHA2, FeatureCRC]>;
+def : AArch64Processor<"cortex-a65", HasV8_2aOps, CortexA53Model, ProcessorFeatures.A65,
+ [TuneA65],
+ [FeatureAES, FeatureSHA2, FeatureDotProd, FeatureFullFP16, FeatureRCPC, FeatureSSBS]>;
+def : AArch64Processor<"cortex-a65ae", HasV8_2aOps, CortexA53Model, ProcessorFeatures.A65,
+ [TuneA65],
+ [FeatureAES, FeatureSHA2, FeatureDotProd, FeatureFullFP16, FeatureRCPC, FeatureSSBS]>;
+def : AArch64Processor<"cortex-a72", HasV8_0aOps, CortexA57Model, ProcessorFeatures.A53,
+ [TuneA72],
+ [FeatureAES, FeatureSHA2, FeatureCRC]>;
+def : AArch64Processor<"cortex-a73", HasV8_0aOps, CortexA57Model, ProcessorFeatures.A53,
+ [TuneA73],
+ [FeatureAES, FeatureSHA2, FeatureCRC]>;
+def : AArch64Processor<"cortex-a75", HasV8_2aOps, CortexA57Model, ProcessorFeatures.A55,
+ [TuneA75],
+ [FeatureAES, FeatureSHA2, FeatureFullFP16, FeatureDotProd, FeatureRCPC]>;
+def : AArch64Processor<"cortex-a76", HasV8_2aOps, CortexA57Model, ProcessorFeatures.A76,
+ [TuneA76],
+ [FeatureAES, FeatureSHA2, FeatureFullFP16, FeatureDotProd, FeatureRCPC, FeatureSSBS]>;
+def : AArch64Processor<"cortex-a76ae", HasV8_2aOps, CortexA57Model, ProcessorFeatures.A76,
+ [TuneA76],
+ [FeatureAES, FeatureSHA2, FeatureFullFP16, FeatureDotProd, FeatureRCPC, FeatureSSBS]>;
+def : AArch64Processor<"cortex-a77", HasV8_2aOps, CortexA57Model, ProcessorFeatures.A77,
+ [TuneA77],
+ [FeatureAES, FeatureSHA2, FeatureFullFP16, FeatureRCPC, FeatureDotProd, FeatureSSBS]>;
+def : AArch64Processor<"cortex-a78", HasV8_2aOps, CortexA57Model, ProcessorFeatures.A78,
+ [TuneA78],
+ [FeatureAES, FeatureSHA2, FeatureFullFP16, FeatureDotProd, FeatureRCPC, FeatureSSBS, FeatureSPE]>;
+def : AArch64Processor<"cortex-a78ae", HasV8_2aOps, CortexA57Model, ProcessorFeatures.A78AE,
+ [TuneA78AE],
+ [FeatureAES, FeatureSHA2, FeatureFullFP16, FeatureDotProd, FeatureRCPC, FeatureSSBS, FeatureSPE]>;
+def : AArch64Processor<"cortex-a78c", HasV8_2aOps, CortexA57Model, ProcessorFeatures.A78C,
+ [TuneA78C],
+ [FeatureAES, FeatureSHA2, FeatureFullFP16, FeatureDotProd, FeatureRCPC, FeatureSSBS, FeatureSPE, FeatureFlagM, FeaturePAuth]>;
+def : AArch64Processor<"cortex-a710", HasV9_0aOps, NeoverseN2Model, ProcessorFeatures.A710,
+ [TuneA710],
+ [FeatureMTE, FeaturePAuth, FeatureFlagM, FeatureSB, FeatureMatMulInt8, FeatureFP16FML, FeatureSVE, FeatureSVE2, FeatureSVE2BitPerm, FeatureBF16]>;
+def : AArch64Processor<"cortex-a715", HasV9_0aOps, NeoverseN2Model, ProcessorFeatures.A715,
+ [TuneA715],
+ [FeatureSB, FeatureSSBS, FeatureMTE, FeatureFullFP16, FeatureFP16FML, FeaturePAuth, FeatureMatMulInt8, FeaturePredRes, FeaturePerfMon, FeatureSPE, FeatureSVE, FeatureSVE2BitPerm, FeatureBF16, FeatureFlagM]>;
+def : AArch64Processor<"cortex-a720", HasV9_2aOps, NeoverseN2Model, ProcessorFeatures.A720,
+ [TuneA720],
+ [FeatureSB, FeatureSSBS, FeatureMTE, FeatureFP16FML, FeaturePAuth, FeatureSVE2BitPerm, FeatureFlagM, FeaturePerfMon, FeaturePredRes, FeatureSPE]>;
+def : AArch64Processor<"cortex-a720ae", HasV9_2aOps, NeoverseN2Model, ProcessorFeatures.A720AE,
+ [TuneA720AE],
+ [FeatureSB, FeatureSSBS, FeatureMTE, FeatureFP16FML, FeaturePAuth, FeatureSVE2BitPerm, FeatureFlagM, FeaturePerfMon, FeaturePredRes, FeatureSPE]>;
+def : AArch64Processor<"cortex-r82", HasV8_0rOps, CortexA55Model, ProcessorFeatures.R82,
+ [TuneR82],
+ [FeatureLSE, FeatureFlagM, FeaturePerfMon, FeaturePredRes]>;
+def : AArch64Processor<"cortex-r82ae", HasV8_0rOps, CortexA55Model, ProcessorFeatures.R82AE,
+ [TuneR82AE],
+ [FeatureLSE, FeatureFlagM, FeaturePerfMon, FeaturePredRes]>;
+def : AArch64Processor<"cortex-x1", HasV8_2aOps, CortexA57Model, ProcessorFeatures.X1,
+ [TuneX1],
+ [FeatureAES, FeatureSHA2, FeatureFullFP16, FeatureDotProd, FeatureRCPC, FeatureSSBS, FeatureSPE]>;
+def : AArch64Processor<"cortex-x1c", HasV8_2aOps, CortexA57Model, ProcessorFeatures.X1C,
+ [TuneX1],
+ [FeatureAES, FeatureSHA2, FeatureFullFP16, FeatureDotProd, FeatureRCPC, FeatureSSBS, FeaturePAuth, FeatureSPE, FeatureFlagM]>;
+def : AArch64Processor<"cortex-x2", HasV9_0aOps, NeoverseN2Model, ProcessorFeatures.X2,
+ [TuneX2],
+ [FeatureMTE, FeatureBF16, FeatureMatMulInt8, FeaturePAuth, FeatureSSBS, FeatureSB, FeatureSVE, FeatureSVE2, FeatureSVE2BitPerm, FeatureFP16FML, FeatureFlagM]>;
+def : AArch64Processor<"cortex-x3", HasV9_0aOps, NeoverseN2Model, ProcessorFeatures.X3,
+ [TuneX3],
+ [FeatureSVE, FeaturePerfMon, FeatureSPE, FeatureBF16, FeatureMatMulInt8, FeatureMTE, FeatureSVE2BitPerm, FeatureSB, FeaturePAuth, FeatureFullFP16, FeatureFP16FML, FeaturePredRes, FeatureFlagM, FeatureSSBS]>;
+def : AArch64Processor<"cortex-x4", HasV9_2aOps, NeoverseN2Model, ProcessorFeatures.X4,
+ [TuneX4],
+ [FeatureSB, FeatureSSBS, FeatureMTE, FeatureFP16FML, FeaturePAuth, FeatureSVE2BitPerm, FeatureFlagM, FeaturePerfMon, FeaturePredRes, FeatureSPE]>;
+def : AArch64Processor<"neoverse-e1", HasV8_2aOps, CortexA53Model, ProcessorFeatures.NeoverseE1,
+ [TuneNeoverseE1],
+ [FeatureAES, FeatureSHA2, FeatureDotProd, FeatureFullFP16, FeatureRCPC, FeatureSSBS]>;
+def : AArch64Processor<"neoverse-n1", HasV8_2aOps, NeoverseN1Model, ProcessorFeatures.NeoverseN1,
+ [TuneNeoverseN1],
+ [FeatureAES, FeatureSHA2, FeatureDotProd, FeatureFullFP16, FeatureSPE, FeatureRCPC, FeatureSSBS]>;
+def : AArch64Processor<"neoverse-n2", HasV9_0aOps, NeoverseN2Model, ProcessorFeatures.NeoverseN2,
+ [TuneNeoverseN2],
+ [FeatureBF16, FeatureDotProd, FeatureFullFP16, FeatureFP16FML, FeatureMatMulInt8, FeatureMTE, FeatureSB, FeatureSSBS, FeatureSVE, FeatureSVE2, FeatureSVE2BitPerm]>;
+def : AArch64Processor<"neoverse-n3", HasV9_2aOps, NeoverseN2Model, ProcessorFeatures.NeoverseN3,
+ [TuneNeoverseN3],
+ [FeatureMTE, FeatureSSBS, FeatureSB, FeaturePredRes, FeatureFP16FML, FeaturePAuth, FeatureFlagM, FeaturePerfMon, FeatureRandGen, FeatureSVE2BitPerm, FeatureSPE, FeaturePerfMon]>;
+def : AArch64Processor<"neoverse-512tvb", HasV8_4aOps, NeoverseV1Model, ProcessorFeatures.Neoverse512TVB,
+ [TuneNeoverse512TVB],
+ [FeatureAES, FeatureSHA2, FeatureSHA3, FeatureSM4, FeatureSVE, FeatureSSBS, FeatureFullFP16, FeatureBF16, FeatureDotProd, FeatureSPE, FeatureRandGen, FeatureFP16FML, FeatureMatMulInt8]>;
+def : AArch64Processor<"neoverse-v1", HasV8_4aOps, NeoverseV1Model, ProcessorFeatures.NeoverseV1,
+ [TuneNeoverseV1],
+ [FeatureAES, FeatureSHA2, FeatureSHA3, FeatureSM4, FeatureSVE, FeatureSSBS, FeatureFullFP16, FeatureBF16, FeatureDotProd, FeatureSPE, FeatureRandGen, FeatureFP16FML, FeatureMatMulInt8]>;
+def : AArch64Processor<"neoverse-v2", HasV9_0aOps, NeoverseV2Model, ProcessorFeatures.NeoverseV2,
+ [TuneNeoverseV2],
+ [FeatureSVE, FeatureSVE2, FeatureSSBS, FeatureFullFP16, FeatureBF16, FeatureRandGen, FeatureDotProd, FeatureSPE, FeatureSVE2BitPerm, FeatureFP16FML, FeatureMatMulInt8, FeatureMTE]>;
+def : AArch64Processor<"neoverse-v3", HasV9_2aOps, NeoverseV2Model, ProcessorFeatures.NeoverseV3,
+ [TuneNeoverseV3],
+ [FeatureSPE, FeatureMTE, FeatureSSBS, FeatureSB, FeaturePredRes, FeatureLS64, FeatureBRBE, FeaturePAuth, FeatureFlagM, FeaturePerfMon, FeatureRandGen, FeatureSVE2BitPerm, FeatureFP16FML]>;
+def : AArch64Processor<"neoverse-v3ae", HasV9_2aOps, NeoverseV2Model, ProcessorFeatures.NeoverseV3AE,
+ [TuneNeoverseV3AE],
+ [FeatureSPE, FeatureMTE, FeatureSSBS, FeatureSB, FeaturePredRes, FeatureLS64, FeatureBRBE, FeaturePAuth, FeatureFlagM, FeaturePerfMon, FeatureRandGen, FeatureSVE2BitPerm, FeatureFP16FML]>;
+def : AArch64Processor<"exynos-m3", HasV8_0aOps, ExynosM3Model, ProcessorFeatures.ExynosM3,
+ [TuneExynosM3],
+ [FeatureAES, FeatureSHA2, FeatureCRC]>;
+def : AArch64Processor<"exynos-m4", HasV8_2aOps, ExynosM4Model, ProcessorFeatures.ExynosM4,
+ [TuneExynosM4],
+ [FeatureAES, FeatureSHA2, FeatureDotProd, FeatureFullFP16]>;
+def : AArch64Processor<"exynos-m5", HasV8_2aOps, ExynosM5Model, ProcessorFeatures.ExynosM4,
+ [TuneExynosM4],
+ [FeatureAES, FeatureSHA2, FeatureDotProd, FeatureFullFP16]>;
+def : AArch64Processor<"falkor", HasV8_0aOps, FalkorModel, ProcessorFeatures.Falkor,
+ [TuneFalkor],
+ [FeatureAES, FeatureSHA2, FeatureCRC, FeatureRDM]>;
+def : AArch64Processor<"saphira", HasV8_3aOps, FalkorModel, ProcessorFeatures.Saphira,
+ [TuneSaphira],
+ [FeatureAES, FeatureSHA2, FeatureSPE]>;
+def : AArch64Processor<"kryo", HasV8_0aOps, KryoModel, ProcessorFeatures.A53,
+ [TuneKryo],
+ [FeatureAES, FeatureSHA2, FeatureCRC]>;
// Cavium ThunderX/ThunderX T8X Processors
-def : ProcessorModel<"thunderx", ThunderXT8XModel, ProcessorFeatures.ThunderX,
- [TuneThunderX]>;
-def : ProcessorModel<"thunderxt88", ThunderXT8XModel,
- ProcessorFeatures.ThunderX, [TuneThunderXT88]>;
-def : ProcessorModel<"thunderxt81", ThunderXT8XModel,
- ProcessorFeatures.ThunderX, [TuneThunderXT81]>;
-def : ProcessorModel<"thunderxt83", ThunderXT8XModel,
- ProcessorFeatures.ThunderX, [TuneThunderXT83]>;
+def : AArch64Processor<"thunderx", HasV8_0aOps, ThunderXT8XModel, ProcessorFeatures.ThunderX,
+ [TuneThunderX],
+ [FeatureAES, FeatureSHA2, FeatureCRC]>;
+def : AArch64Processor<"thunderxt88", HasV8_0aOps, ThunderXT8XModel, ProcessorFeatures.ThunderX,
+ [TuneThunderXT88],
+ [FeatureAES, FeatureSHA2, FeatureCRC]>;
+def : AArch64Processor<"thunderxt81", HasV8_0aOps, ThunderXT8XModel, ProcessorFeatures.ThunderX,
+ [TuneThunderXT81],
+ [FeatureAES, FeatureSHA2, FeatureCRC]>;
+def : AArch64Processor<"thunderxt83", HasV8_0aOps, ThunderXT8XModel, ProcessorFeatures.ThunderX,
+ [TuneThunderXT83],
+ [FeatureAES, FeatureSHA2, FeatureCRC]>;
// Cavium ThunderX2T9X Processors. Formerly Broadcom Vulcan.
-def : ProcessorModel<"thunderx2t99", ThunderX2T99Model,
- ProcessorFeatures.ThunderX2T99, [TuneThunderX2T99]>;
+def : AArch64Processor<"thunderx2t99", HasV8_1aOps, ThunderX2T99Model, ProcessorFeatures.ThunderX2T99,
+ [TuneThunderX2T99],
+ [FeatureAES, FeatureSHA2]>;
// Marvell ThunderX3T110 Processors.
-def : ProcessorModel<"thunderx3t110", ThunderX3T110Model,
- ProcessorFeatures.ThunderX3T110, [TuneThunderX3T110]>;
-def : ProcessorModel<"tsv110", TSV110Model, ProcessorFeatures.TSV110,
- [TuneTSV110]>;
+def : AArch64Processor<"thunderx3t110", HasV8_3aOps, ThunderX3T110Model, ProcessorFeatures.ThunderX3T110,
+ [TuneThunderX3T110],
+ [FeatureAES, FeatureSHA2]>;
+def : AArch64Processor<"tsv110", HasV8_2aOps, TSV110Model, ProcessorFeatures.TSV110,
+ [TuneTSV110],
+ [FeatureAES, FeatureSHA2, FeatureDotProd, FeatureFullFP16, FeatureFP16FML, FeatureSPE, FeatureJS, FeatureComplxNum]>;
// Support cyclone as an alias for apple-a7 so we can still LTO old bitcode.
-def : ProcessorModel<"cyclone", CycloneModel, ProcessorFeatures.AppleA7,
- [TuneAppleA7]>;
+def : AArch64Processor<"cyclone", HasV8_0aOps, CycloneModel, ProcessorFeatures.AppleA7,
+ [TuneAppleA7],
+ [FeatureAES, FeatureSHA2]>;
// iPhone and iPad CPUs
-def : ProcessorModel<"apple-a7", CycloneModel, ProcessorFeatures.AppleA7,
- [TuneAppleA7]>;
-def : ProcessorModel<"apple-a8", CycloneModel, ProcessorFeatures.AppleA7,
- [TuneAppleA7]>;
-def : ProcessorModel<"apple-a9", CycloneModel, ProcessorFeatures.AppleA7,
- [TuneAppleA7]>;
-def : ProcessorModel<"apple-a10", CycloneModel, ProcessorFeatures.AppleA10,
- [TuneAppleA10]>;
-def : ProcessorModel<"apple-a11", CycloneModel, ProcessorFeatures.AppleA11,
- [TuneAppleA11]>;
-def : ProcessorModel<"apple-a12", CycloneModel, ProcessorFeatures.AppleA12,
- [TuneAppleA12]>;
-def : ProcessorModel<"apple-a13", CycloneModel, ProcessorFeatures.AppleA13,
- [TuneAppleA13]>;
-def : ProcessorModel<"apple-a14", CycloneModel, ProcessorFeatures.AppleA14,
- [TuneAppleA14]>;
-def : ProcessorModel<"apple-a15", CycloneModel, ProcessorFeatures.AppleA15,
- [TuneAppleA15]>;
-def : ProcessorModel<"apple-a16", CycloneModel, ProcessorFeatures.AppleA16,
- [TuneAppleA16]>;
-def : ProcessorModel<"apple-a17", CycloneModel, ProcessorFeatures.AppleA17,
- [TuneAppleA17]>;
+def : AArch64Processor<"apple-a7", HasV8_0aOps, CycloneModel, ProcessorFeatures.AppleA7,
+ [TuneAppleA7],
+ [FeatureAES, FeatureSHA2]>;
+def : AArch64Processor<"apple-a8", HasV8_0aOps, CycloneModel, ProcessorFeatures.AppleA7,
+ [TuneAppleA7],
+ [FeatureAES, FeatureSHA2]>;
+def : AArch64Processor<"apple-a9", HasV8_0aOps, CycloneModel, ProcessorFeatures.AppleA7,
+ [TuneAppleA7],
+ [FeatureAES, FeatureSHA2]>;
+def : AArch64Processor<"apple-a10", HasV8_0aOps, CycloneModel, ProcessorFeatures.AppleA10,
+ [TuneAppleA10],
+ [FeatureAES, FeatureSHA2, FeatureCRC, FeatureRDM]>;
+def : AArch64Processor<"apple-a11", HasV8_2aOps, CycloneModel, ProcessorFeatures.AppleA11,
+ [TuneAppleA11],
+ [FeatureAES, FeatureSHA2, FeatureFullFP16]>;
+def : AArch64Processor<"apple-a12", HasV8_3aOps, CycloneModel, ProcessorFeatures.AppleA12,
+ [TuneAppleA12],
+ [FeatureAES, FeatureSHA2, FeatureFullFP16]>;
+def : AArch64Processor<"apple-a13", HasV8_4aOps, CycloneModel, ProcessorFeatures.AppleA13,
+ [TuneAppleA13],
+ [FeatureAES, FeatureSHA2, FeatureSHA3, FeatureFullFP16, FeatureFP16FML]>;
+def : AArch64Processor<"apple-a14", HasV8_5aOps, CycloneModel, ProcessorFeatures.AppleA14,
+ [TuneAppleA14],
+ [FeatureAES, FeatureSHA2, FeatureSHA3, FeatureFullFP16, FeatureFP16FML]>;
+def : AArch64Processor<"apple-a15", HasV8_6aOps, CycloneModel, ProcessorFeatures.AppleA15,
+ [TuneAppleA15],
+ [FeatureAES, FeatureSHA2, FeatureSHA3, FeatureFullFP16, FeatureFP16FML]>;
+// Alias for the latest Apple processor model supported by LLVM.
+def : AArch64Processor<"apple-a16", HasV8_6aOps, CycloneModel, ProcessorFeatures.AppleA16,
+ [TuneAppleA16],
+ [FeatureAES, FeatureSHA2, FeatureSHA3, FeatureFullFP16, FeatureFP16FML]>;
+def : AArch64Processor<"apple-a17", HasV8_6aOps, CycloneModel, ProcessorFeatures.AppleA17,
+ [TuneAppleA17],
+ [FeatureAES, FeatureSHA2, FeatureSHA3, FeatureFullFP16, FeatureFP16FML]>;
// Mac CPUs
-def : ProcessorModel<"apple-m1", CycloneModel, ProcessorFeatures.AppleA14,
- [TuneAppleA14]>;
-def : ProcessorModel<"apple-m2", CycloneModel, ProcessorFeatures.AppleA15,
- [TuneAppleA15]>;
-def : ProcessorModel<"apple-m3", CycloneModel, ProcessorFeatures.AppleA16,
- [TuneAppleA16]>;
+def : AArch64Processor<"apple-m1", HasV8_5aOps, CycloneModel, ProcessorFeatures.AppleA14,
+ [TuneAppleA14],
+ [FeatureAES, FeatureSHA2, FeatureSHA3, FeatureFullFP16, FeatureFP16FML]>;
+def : AArch64Processor<"apple-m2", HasV8_6aOps, CycloneModel, ProcessorFeatures.AppleA15,
+ [TuneAppleA15],
+ [FeatureAES, FeatureSHA2, FeatureSHA3, FeatureFullFP16, FeatureFP16FML]>;
+def : AArch64Processor<"apple-m3", HasV8_6aOps, CycloneModel, ProcessorFeatures.AppleA16,
+ [TuneAppleA16],
+ [FeatureAES, FeatureSHA2, FeatureSHA3, FeatureFullFP16, FeatureFP16FML]>;
// watch CPUs.
-def : ProcessorModel<"apple-s4", CycloneModel, ProcessorFeatures.AppleA12,
- [TuneAppleA12]>;
-def : ProcessorModel<"apple-s5", CycloneModel, ProcessorFeatures.AppleA12,
- [TuneAppleA12]>;
-
-// Alias for the latest Apple processor model supported by LLVM.
-def : ProcessorModel<"apple-latest", CycloneModel, ProcessorFeatures.AppleA16,
- [TuneAppleA16]>;
+def : AArch64Processor<"apple-s4", HasV8_3aOps, CycloneModel, ProcessorFeatures.AppleA12,
+ [TuneAppleA12],
+ [FeatureAES, FeatureSHA2, FeatureFullFP16]>;
+def : AArch64Processor<"apple-s5", HasV8_3aOps, CycloneModel, ProcessorFeatures.AppleA12,
+ [TuneAppleA12],
+ [FeatureAES, FeatureSHA2, FeatureFullFP16]>;
// Fujitsu A64FX
-def : ProcessorModel<"a64fx", A64FXModel, ProcessorFeatures.A64FX,
- [TuneA64FX]>;
+def : AArch64Processor<"a64fx", HasV8_2aOps, A64FXModel, ProcessorFeatures.A64FX,
+ [TuneA64FX],
+ [FeatureAES, FeatureSHA2, FeatureFullFP16, FeatureSVE]>;
// Nvidia Carmel
-def : ProcessorModel<"carmel", NoSchedModel, ProcessorFeatures.Carmel,
- [TuneCarmel]>;
+def : AArch64Processor<"carmel", HasV8_2aOps, NoSchedModel, ProcessorFeatures.Carmel,
+ [TuneCarmel],
+ [FeatureAES, FeatureSHA2, FeatureFullFP16]>;
// Ampere Computing
-def : ProcessorModel<"ampere1", Ampere1Model, ProcessorFeatures.Ampere1,
- [TuneAmpere1]>;
+def : AArch64Processor<"ampere1", HasV8_6aOps, Ampere1Model, ProcessorFeatures.Ampere1,
+ [TuneAmpere1],
+ [FeatureAES, FeatureSHA2, FeatureSHA3, FeatureFullFP16, FeatureSB, FeatureSSBS, FeatureRandGen]>;
-def : ProcessorModel<"ampere1a", Ampere1Model, ProcessorFeatures.Ampere1A,
- [TuneAmpere1A]>;
+def : AArch64Processor<"ampere1a", HasV8_6aOps, Ampere1Model, ProcessorFeatures.Ampere1A,
+ [TuneAmpere1A],
+ [FeatureFullFP16, FeatureRandGen, FeatureSM4, FeatureSHA3, FeatureSHA2, FeatureAES, FeatureMTE, FeatureSB, FeatureSSBS]>;
-def : ProcessorModel<"ampere1b", Ampere1BModel, ProcessorFeatures.Ampere1B,
- [TuneAmpere1B]>;
+def : AArch64Processor<"ampere1b", HasV8_7aOps, Ampere1BModel, ProcessorFeatures.Ampere1B,
+ [TuneAmpere1B],
+ [FeatureFullFP16, FeatureRandGen, FeatureSM4, FeatureSHA3, FeatureSHA2, FeatureAES, FeatureMTE, FeatureSB, FeatureSSBS, FeatureCSSC]>;
diff --git a/llvm/utils/TableGen/ARMTargetDefEmitter.cpp b/llvm/utils/TableGen/ARMTargetDefEmitter.cpp
index 70050020865e0..c2d9d92570888 100644
--- a/llvm/utils/TableGen/ARMTargetDefEmitter.cpp
+++ b/llvm/utils/TableGen/ARMTargetDefEmitter.cpp
@@ -115,6 +115,13 @@ static void EmitARMTargetDef(RecordKeeper &RK, raw_ostream &OS) {
// Emit architecture information
OS << "#ifdef EMIT_ARCHITECTURES\n";
+ // Return the C++ name of the of an ArchInfo object
+ auto ArchInfoName = [](int Major, int Minor, StringRef Profile) {
+ return Minor == 0 ? "ARMV" + std::to_string(Major) + Profile.upper()
+ : "ARMV" + std::to_string(Major) + "_" +
+ std::to_string(Minor) + Profile.upper();
+ };
+
auto Architectures = RK.getAllDerivedDefinitionsIfDefined("Architecture64");
std::vector<std::string> CppSpellings;
for (const Record *Rec : Architectures) {
@@ -129,10 +136,7 @@ static void EmitARMTargetDef(RecordKeeper &RK, raw_ostream &OS) {
ProfileLower + "'");
// Name of the object in C++
- const std::string CppSpelling =
- Minor == 0 ? "ARMV" + std::to_string(Major) + ProfileUpper.c_str()
- : "ARMV" + std::to_string(Major) + "_" +
- std::to_string(Minor) + ProfileUpper.c_str();
+ const std::string CppSpelling = ArchInfoName(Major, Minor, ProfileUpper);
OS << "inline constexpr ArchInfo " << CppSpelling << " = {\n";
CppSpellings.push_back(CppSpelling);
@@ -173,6 +177,35 @@ static void EmitARMTargetDef(RecordKeeper &RK, raw_ostream &OS) {
OS << "#undef EMIT_ARCHITECTURES\n"
<< "#endif // EMIT_ARCHITECTURES\n"
<< "\n";
+
+ // Emit CPU information
+ OS << "#ifdef EMIT_CPU_INFO\n"
+ << "inline constexpr CpuInfo CpuInfos[] = {\n";
+
+ for (const Record *Rec :
+ RK.getAllDerivedDefinitionsIfDefined("AArch64Processor")) {
+ auto Name = Rec->getValueAsString("Name");
+ auto Arch = Rec->getValueAsDef("Arch");
+ auto Major = Arch->getValueAsInt("Major");
+ auto Minor = Arch->getValueAsInt("Minor");
+ auto Profile = Arch->getValueAsString("Profile");
+ auto ArchInfo = ArchInfoName(Major, Minor, Profile);
+
+ OS << " {\n"
+ << " \"" << Name << "\",\n"
+ << " " << ArchInfo << ",\n"
+ << " AArch64::ExtensionBitset({\n";
+ for (auto E : Rec->getValueAsListOfDefs("DefaultExts"))
+ OS << " AArch64::"
+ << E->getValueAsString("ArchExtKindSpelling").upper() << ",\n";
+ OS << " })\n"
+ << " },\n";
+ }
+ OS << "};\n";
+
+ OS << "#undef EMIT_CPU_INFO\n"
+ << "#endif // EMIT_CPU_INFO\n"
+ << "\n";
}
static TableGen::Emitter::Opt
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