[llvm] [RISCV] Improve constant materialisation for stores of i8 negative constants (PR #92131)

[Philip Reames via llvm-commits]

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@@ -902,6 +902,11 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
       return;
     }
     int64_t Imm = ConstNode->getSExtValue();
+    // If only the lower 8 bits are used, try to convert this to a simm6 by
+    // sign-extending bit 7. This is neutral without the C extension, and
+    // allows C.LI to be used if C is present.
+    if (isUInt<8>(Imm) && isInt<6>(SignExtend64<8>(Imm)) && hasAllBUsers(Node))
+      Imm = SignExtend64<6>(Imm);
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preames wrote:

For code clarity, can you replace this with SignExtend64<8>(Imm)?  In the context of the check just above, they should be the same, but having them match is slightly easier to follow.

https://github.com/llvm/llvm-project/pull/92131