[llvm] 31fb0ae - [PowerPC] Regenerate and_sext.ll with test checks

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2024-05-14T11:58:48+01:00
New Revision: 31fb0ae23d3d1a1b90198a68c80c9116d844a01f

URL: https://github.com/llvm/llvm-project/commit/31fb0ae23d3d1a1b90198a68c80c9116d844a01f
DIFF: https://github.com/llvm/llvm-project/commit/31fb0ae23d3d1a1b90198a68c80c9116d844a01f.diff

LOG: [PowerPC] Regenerate and_sext.ll with test checks

I've kept the grep checks for extsh/extsb instructions, but we can now see the actual codegen as well

Added: 
    

Modified: 
    llvm/test/CodeGen/PowerPC/and_sext.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/PowerPC/and_sext.ll b/llvm/test/CodeGen/PowerPC/and_sext.ll
index 3b576ca18ee74..b67b86bd5132b 100644
--- a/llvm/test/CodeGen/PowerPC/and_sext.ll
+++ b/llvm/test/CodeGen/PowerPC/and_sext.ll
@@ -1,28 +1,43 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
 ; These tests should not contain a sign extend.
+; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | FileCheck %s
 ; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | not grep extsh
 ; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | not grep extsb
 
 define i32 @test1(i32 %mode.0.i.0) {
-        %tmp.79 = trunc i32 %mode.0.i.0 to i16
-        %tmp.80 = sext i16 %tmp.79 to i32
-        %tmp.81 = and i32 %tmp.80, 24
-        ret i32 %tmp.81
+; CHECK-LABEL: test1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    rlwinm 3, 3, 0, 27, 28
+; CHECK-NEXT:    blr
+  %tmp.79 = trunc i32 %mode.0.i.0 to i16
+  %tmp.80 = sext i16 %tmp.79 to i32
+  %tmp.81 = and i32 %tmp.80, 24
+  ret i32 %tmp.81
 }
 
 define signext i16 @test2(i16 signext %X, i16 signext %x)  {
-        %tmp = sext i16 %X to i32
-        %tmp1 = sext i16 %x to i32
-        %tmp2 = add i32 %tmp, %tmp1
-        %tmp4 = ashr i32 %tmp2, 1
-        %tmp5 = trunc i32 %tmp4 to i16
-        %tmp45 = sext i16 %tmp5 to i32
-        %retval = trunc i32 %tmp45 to i16
-        ret i16 %retval
+; CHECK-LABEL: test2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    add 3, 3, 4
+; CHECK-NEXT:    srawi 3, 3, 1
+; CHECK-NEXT:    blr
+  %tmp = sext i16 %X to i32
+  %tmp1 = sext i16 %x to i32
+  %tmp2 = add i32 %tmp, %tmp1
+  %tmp4 = ashr i32 %tmp2, 1
+  %tmp5 = trunc i32 %tmp4 to i16
+  %tmp45 = sext i16 %tmp5 to i32
+  %retval = trunc i32 %tmp45 to i16
+  ret i16 %retval
 }
 
 define signext i16 @test3(i32 zeroext %X)  {
-        %tmp1 = lshr i32 %X, 16
-        %tmp2 = trunc i32 %tmp1 to i16
-        ret i16 %tmp2
+; CHECK-LABEL: test3:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    srawi 3, 3, 16
+; CHECK-NEXT:    blr
+  %tmp1 = lshr i32 %X, 16
+  %tmp2 = trunc i32 %tmp1 to i16
+  ret i16 %tmp2
 }