[llvm] 9f80f43 - [Hexagon] Regenerate asr-rnd.ll + asr-rnd64.ll to show all test checks

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2024-05-14T10:49:35+01:00
New Revision: 9f80f437c0b698478c6396c8c44ba094f7199144

URL: https://github.com/llvm/llvm-project/commit/9f80f437c0b698478c6396c8c44ba094f7199144
DIFF: https://github.com/llvm/llvm-project/commit/9f80f437c0b698478c6396c8c44ba094f7199144.diff

LOG: [Hexagon] Regenerate asr-rnd.ll + asr-rnd64.ll to show all test checks

These are affected by upcoming support for AVG legalization

Added: 
    

Modified: 
    llvm/test/CodeGen/Hexagon/asr-rnd.ll
    llvm/test/CodeGen/Hexagon/asr-rnd64.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/Hexagon/asr-rnd.ll b/llvm/test/CodeGen/Hexagon/asr-rnd.ll
index bc77e2a7a3ad4..cd088dd8f0138 100644
--- a/llvm/test/CodeGen/Hexagon/asr-rnd.ll
+++ b/llvm/test/CodeGen/Hexagon/asr-rnd.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
 ; RUN: llc -march=hexagon < %s | FileCheck %s
 ;
 ; Check if we generate rounding-asr instruction.  It is equivalent to
@@ -6,8 +7,19 @@ target triple = "hexagon"
 
 ; Function Attrs: nounwind
 define i32 @f0(i32 %a0) #0 {
+; CHECK-LABEL: f0:
+; CHECK:       // %bb.0: // %b0
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r0 = asr(r0,#10):rnd
+; CHECK-NEXT:     r1 = r0
+; CHECK-NEXT:     r29 = add(r29,#-8)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r29 = add(r29,#8)
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:     memw(r29+#4) = r1
+; CHECK-NEXT:    }
 b0:
-; CHECK: asr{{.*}}:rnd
   %v0 = alloca i32, align 4
   store i32 %a0, ptr %v0, align 4
   %v1 = load i32, ptr %v0, align 4
@@ -19,8 +31,19 @@ b0:
 
 ; Function Attrs: nounwind
 define i64 @f1(i64 %a0) #0 {
+; CHECK-LABEL: f1:
+; CHECK:       // %bb.0: // %b0
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r1:0 = asr(r1:0,#17):rnd
+; CHECK-NEXT:     r3:2 = combine(r1,r0)
+; CHECK-NEXT:     r29 = add(r29,#-8)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r29 = add(r29,#8)
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:     memd(r29+#0) = r3:2
+; CHECK-NEXT:    }
 b0:
-; CHECK: asr{{.*}}:rnd
   %v0 = alloca i64, align 8
   store i64 %a0, ptr %v0, align 8
   %v1 = load i64, ptr %v0, align 8

diff  --git a/llvm/test/CodeGen/Hexagon/asr-rnd64.ll b/llvm/test/CodeGen/Hexagon/asr-rnd64.ll
index 4928483e5be68..e32bdff7d764a 100644
--- a/llvm/test/CodeGen/Hexagon/asr-rnd64.ll
+++ b/llvm/test/CodeGen/Hexagon/asr-rnd64.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
 ; RUN: llc -march=hexagon < %s | FileCheck %s
 ;
 ; Check if we generate rounding-asr instruction.  It is equivalent to
@@ -6,8 +7,20 @@
 target triple = "hexagon"
 
 define i32 @f0(i32 %a0) {
+; CHECK-LABEL: f0:
+; CHECK:         .cfi_startproc
+; CHECK-NEXT:  // %bb.0: // %b0
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r0 = asr(r0,#10):rnd
+; CHECK-NEXT:     r1 = r0
+; CHECK-NEXT:     r29 = add(r29,#-8)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r29 = add(r29,#8)
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:     memw(r29+#4) = r1
+; CHECK-NEXT:    }
 b0:
-; CHECK: asr{{.*}}:rnd
   %v0 = alloca i32, align 4
   store i32 %a0, ptr %v0, align 4
   %v1 = load i32, ptr %v0, align 4
@@ -18,8 +31,20 @@ b0:
 }
 
 define i64 @f1(i64 %a0) {
+; CHECK-LABEL: f1:
+; CHECK:         .cfi_startproc
+; CHECK-NEXT:  // %bb.0: // %b0
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r1:0 = asr(r1:0,#17):rnd
+; CHECK-NEXT:     r3:2 = combine(r1,r0)
+; CHECK-NEXT:     r29 = add(r29,#-8)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r29 = add(r29,#8)
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:     memd(r29+#0) = r3:2
+; CHECK-NEXT:    }
 b0:
-; CHECK: asr{{.*}}:rnd
   %v0 = alloca i64, align 8
   store i64 %a0, ptr %v0, align 8
   %v1 = load i64, ptr %v0, align 8