[llvm] cf9a5a1 - [SPIR-V] Support saturation arithmetic intrinsics in SPIR-V Backend (#91722)

[via llvm-commits]

Author: Vyacheslav Levytskyy
Date: 2024-05-14T09:22:37+02:00
New Revision: cf9a5a162b701b4c27eda1ddf823137ed16ca235

URL: https://github.com/llvm/llvm-project/commit/cf9a5a162b701b4c27eda1ddf823137ed16ca235
DIFF: https://github.com/llvm/llvm-project/commit/cf9a5a162b701b4c27eda1ddf823137ed16ca235.diff

LOG: [SPIR-V] Support saturation arithmetic intrinsics in SPIR-V Backend (#91722)

This PR is to support saturation arithmetic intrinsics in SPIR-V
Backend.

Added: 
    llvm/test/CodeGen/SPIRV/llvm-intrinsics/satur-arith.ll

Modified: 
    llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
    llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
index 2051cdc7e01ff..517a9b490ebad 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
@@ -495,6 +495,15 @@ bool SPIRVInstructionSelector::spvSelect(Register ResVReg,
   case TargetOpcode::G_UMULH:
     return selectExtInst(ResVReg, ResType, I, CL::u_mul_hi);
 
+  case TargetOpcode::G_SADDSAT:
+    return selectExtInst(ResVReg, ResType, I, CL::s_add_sat);
+  case TargetOpcode::G_UADDSAT:
+    return selectExtInst(ResVReg, ResType, I, CL::u_add_sat);
+  case TargetOpcode::G_SSUBSAT:
+    return selectExtInst(ResVReg, ResType, I, CL::s_sub_sat);
+  case TargetOpcode::G_USUBSAT:
+    return selectExtInst(ResVReg, ResType, I, CL::u_sub_sat);
+
   case TargetOpcode::G_SEXT:
     return selectExt(ResVReg, ResType, I, true);
   case TargetOpcode::G_ANYEXT:

diff  --git a/llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp b/llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp
index e7b35555293a3..42d36fd30ed6f 100644
--- a/llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp
@@ -304,6 +304,10 @@ SPIRVLegalizerInfo::SPIRVLegalizerInfo(const SPIRVSubtarget &ST) {
 
     // Struct return types become a single scalar, so cannot easily legalize.
     getActionDefinitionsBuilder({G_SMULH, G_UMULH}).alwaysLegal();
+
+    // supported saturation arithmetic
+    getActionDefinitionsBuilder({G_SADDSAT, G_UADDSAT, G_SSUBSAT, G_USUBSAT})
+        .legalFor(allIntScalarsAndVectors);
   }
 
   getLegacyLegalizerInfo().computeTables();

diff  --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/satur-arith.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/satur-arith.ll
new file mode 100644
index 0000000000000..5b59206ff7f2d
--- /dev/null
+++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/satur-arith.ll
@@ -0,0 +1,37 @@
+; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}
+
+; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
+
+; CHECK: OpExtInstImport "OpenCL.std"
+; CHECK-DAG: OpName %[[#Foo:]] "foo"
+; CHECK-DAG: OpName %[[#Bar:]] "bar"
+; CHECK: %[[#Foo]] = OpFunction
+; CHECK: %[[#]] = OpExtInst %[[#]] %[[#]] u_add_sat
+; CHECK-NEXT: %[[#]] = OpExtInst %[[#]] %[[#]] u_sub_sat
+; CHECK-NEXT: %[[#]] = OpExtInst %[[#]] %[[#]] s_add_sat
+; CHECK-NEXT: %[[#]] = OpExtInst %[[#]] %[[#]] s_sub_sat
+; CHECK: %[[#Bar]] = OpFunction
+; CHECK: %[[#]] = OpExtInst %[[#]] %[[#]] u_add_sat
+; CHECK-NEXT: %[[#]] = OpExtInst %[[#]] %[[#]] u_sub_sat
+; CHECK-NEXT: %[[#]] = OpExtInst %[[#]] %[[#]] s_add_sat
+; CHECK-NEXT: %[[#]] = OpExtInst %[[#]] %[[#]] s_sub_sat
+
+define spir_func void @foo(i16 %x, i16 %y) {
+entry:
+  %r1 = tail call i16 @llvm.uadd.sat.i16(i16 %x, i16 %y)
+  %r2 = tail call i16 @llvm.usub.sat.i16(i16 %x, i16 %y)
+  %r3 = tail call i16 @llvm.sadd.sat.i16(i16 %x, i16 %y)
+  %r4 = tail call i16 @llvm.ssub.sat.i16(i16 %x, i16 %y)
+  ret void
+}
+
+define spir_func void @bar(<4 x i32> %x, <4 x i32> %y) {
+entry:
+  %r1 = tail call <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32> %x, <4 x i32> %y)
+  %r2 = tail call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> %x, <4 x i32> %y)
+  %r3 = tail call <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> %x, <4 x i32> %y)
+  %r4 = tail call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> %x, <4 x i32> %y)
+  ret void
+}