[llvm] [RISCV] Support postRA vsetvl insertion pass (PR #70549)

[Piyou Chen via llvm-commits]

BeMg wrote:

Here is a idea to teach the scheduler to be aware of the VSETVL status between RVV instructions in https://github.com/BeMg/llvm-project/commit/1535c7fa9aea08487655ce61bcc9f0cf55a00a42. It reduces the vsetvli instructions after moving the vsetvl pass after post-ra without increasing spill/reload. This also could be extended to make the scheduler aware of register pressure cause by VSETVL moving, as mentioned in https://github.com/llvm/llvm-project/pull/91440#discussion_r1596880182.

![Screenshot 2024-05-14 at 2 11 18 PM](https://github.com/llvm/llvm-project/assets/9087370/23b1d65f-ce48-4d6a-b06b-28f298d97dda)



https://github.com/llvm/llvm-project/pull/70549