[llvm] b1c958e - [AArch64] Clarify atomic load/store size condition (NFCI) (#91907)

[via llvm-commits]

Author: Nikita Popov
Date: 2024-05-14T10:06:10+09:00
New Revision: b1c958e50e5d58040c53e2aa822f4dfbcbf9c273

URL: https://github.com/llvm/llvm-project/commit/b1c958e50e5d58040c53e2aa822f4dfbcbf9c273
DIFF: https://github.com/llvm/llvm-project/commit/b1c958e50e5d58040c53e2aa822f4dfbcbf9c273.diff

LOG: [AArch64] Clarify atomic load/store size condition (NFCI) (#91907)

This is currently bailing out on MemSizeInBytes larger than 64 bytes.
However, the following code can only handle sizes up to 8 bytes.
Possibly there was confusion here between MemSizeInBytes and
MemSizeInBits.

I *think* that this can't actually result in an out of bounds read of
the opcode table because we'll only ever mark loads/stores of up to 8
bytes as legal (16 byte atomics are custom-legalized earlier). As such,
I've changed this condition to an assert.

Added: 
    

Modified: 
    llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
index 1b65ae7b47826..3b3c1fc8b27bf 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
@@ -2861,8 +2861,8 @@ bool AArch64InstructionSelector::select(MachineInstr &I) {
         Order != AtomicOrdering::Unordered &&
         Order != AtomicOrdering::Monotonic) {
       assert(!isa<GZExtLoad>(LdSt));
-      if (MemSizeInBytes > 64)
-        return false;
+      assert(MemSizeInBytes <= 8 &&
+             "128-bit atomics should already be custom-legalized");
 
       if (isa<GLoad>(LdSt)) {
         static constexpr unsigned LDAPROpcodes[] = {