[llvm] [RISCV] Reduce the amount of similar code in RISCVInstPrinter::printRlist. NFC (PR #92053)

[Craig Topper via llvm-commits]

https://github.com/topperc created https://github.com/llvm/llvm-project/pull/92053

Remove the switch statement and instead do range checks to know which pieces we need to print.

>From b76d5337394fa153329b2c9a059faeab41a7a290 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Mon, 13 May 2024 17:06:45 -0700
Subject: [PATCH] [RISCV] Reduce the amount of similar code in
 RISCVInstPrinter::printRlist. NFC

Remove the switch statement and instead do range checks to know
which pieces we need to print.
---
 .../RISCV/MCTargetDesc/RISCVInstPrinter.cpp   | 70 +++++++------------
 1 file changed, 26 insertions(+), 44 deletions(-)

diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
index 663d4bad767de..48b669c78cade 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
@@ -216,62 +216,44 @@ void RISCVInstPrinter::printVTypeI(const MCInst *MI, unsigned OpNo,
   RISCVVType::printVType(Imm, O);
 }
 
+// Print a Zcmp RList. If we are printing architectural register names rather
+// than ABI register names, we need to print "{x1, x8-x9, x18-x27}" for all
+// registers. Otherwise, we print "{ra, s0-s11}".
 void RISCVInstPrinter::printRlist(const MCInst *MI, unsigned OpNo,
                                   const MCSubtargetInfo &STI, raw_ostream &O) {
   unsigned Imm = MI->getOperand(OpNo).getImm();
   O << "{";
-  switch (Imm) {
-  case RISCVZC::RLISTENCODE::RA:
-    printRegName(O, RISCV::X1);
-    break;
-  case RISCVZC::RLISTENCODE::RA_S0:
-    printRegName(O, RISCV::X1);
-    O << ", ";
-    printRegName(O, RISCV::X8);
-    break;
-  case RISCVZC::RLISTENCODE::RA_S0_S1:
-    printRegName(O, RISCV::X1);
-    O << ", ";
-    printRegName(O, RISCV::X8);
-    O << '-';
-    printRegName(O, RISCV::X9);
-    break;
-  case RISCVZC::RLISTENCODE::RA_S0_S2:
-    printRegName(O, RISCV::X1);
-    O << ", ";
-    printRegName(O, RISCV::X8);
-    O << '-';
-    if (ArchRegNames) {
-      printRegName(O, RISCV::X9);
-      O << ", ";
-    }
-    printRegName(O, RISCV::X18);
-    break;
-  case RISCVZC::RLISTENCODE::RA_S0_S3:
-  case RISCVZC::RLISTENCODE::RA_S0_S4:
-  case RISCVZC::RLISTENCODE::RA_S0_S5:
-  case RISCVZC::RLISTENCODE::RA_S0_S6:
-  case RISCVZC::RLISTENCODE::RA_S0_S7:
-  case RISCVZC::RLISTENCODE::RA_S0_S8:
-  case RISCVZC::RLISTENCODE::RA_S0_S9:
-  case RISCVZC::RLISTENCODE::RA_S0_S11:
-    printRegName(O, RISCV::X1);
+  printRegName(O, RISCV::X1);
+
+  if (Imm >= RISCVZC::RLISTENCODE::RA_S0) {
     O << ", ";
     printRegName(O, RISCV::X8);
+  }
+
+  if (Imm >= RISCVZC::RLISTENCODE::RA_S0_S1) {
     O << '-';
-    if (ArchRegNames) {
+    if (Imm == RISCVZC::RLISTENCODE::RA_S0_S1 || ArchRegNames)
       printRegName(O, RISCV::X9);
+  }
+
+  if (Imm >= RISCVZC::RLISTENCODE::RA_S0_S2) {
+    if (ArchRegNames)
       O << ", ";
+    if (Imm == RISCVZC::RLISTENCODE::RA_S0_S2 || ArchRegNames)
       printRegName(O, RISCV::X18);
+  }
+
+  if (Imm >= RISCVZC::RLISTENCODE::RA_S0_S3) {
+    if (ArchRegNames)
       O << '-';
-    }
-    printRegName(O, RISCV::X19 + (Imm == RISCVZC::RLISTENCODE::RA_S0_S11
-                                      ? 8
-                                      : Imm - RISCVZC::RLISTENCODE::RA_S0_S3));
-    break;
-  default:
-    llvm_unreachable("invalid register list");
+    unsigned Offset = (Imm - RISCVZC::RLISTENCODE::RA_S0_S3);
+    // Encodings for S3-S9 are contiguous. There is no encoding for S10, so we
+    // must skip to S11(X27).
+    if (Imm == RISCVZC::RLISTENCODE::RA_S0_S11)
+      ++Offset;
+    printRegName(O, RISCV::X19 + Offset);
   }
+
   O << "}";
 }