[llvm] 4357712 - [RISCV] Inogre CallingConv::RISCV_VectorCall in getCalleeSavedRegs if V/Zve is not enabled.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2024-05-13T16:04:09-07:00
New Revision: 435771228caf77cce35406ecf57a49a06e227fe4

URL: https://github.com/llvm/llvm-project/commit/435771228caf77cce35406ecf57a49a06e227fe4
DIFF: https://github.com/llvm/llvm-project/commit/435771228caf77cce35406ecf57a49a06e227fe4.diff

LOG: [RISCV] Inogre CallingConv::RISCV_VectorCall in getCalleeSavedRegs if V/Zve is not enabled.

We can't save vector registers without V/Zve.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
index 129b4cb4e8cb7..caa5dbc15f8bd 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
@@ -72,7 +72,8 @@ RISCVRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
   }
 
   bool HasVectorCSR =
-      MF->getFunction().getCallingConv() == CallingConv::RISCV_VectorCall;
+      MF->getFunction().getCallingConv() == CallingConv::RISCV_VectorCall &&
+      Subtarget.hasVInstructions();
 
   switch (Subtarget.getTargetABI()) {
   default: