[llvm] RISCVAsmParser: Make diagnostics more conventional (PR #92024)
via llvm-commits
llvm-commits at lists.llvm.org
Mon May 13 13:29:46 PDT 2024
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-mc
Author: Fangrui Song (MaskRay)
<details>
<summary>Changes</summary>
Most diagnostics obey
https://llvm.org/docs/CodingStandards.html#error-and-warning-messages
but some diverge. Fix them.
While here, adjust some diagnostics.
---
Patch is 53.95 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/92024.diff
13 Files Affected:
- (modified) llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp (+21-22)
- (modified) llvm/test/MC/RISCV/option-invalid.s (+3-3)
- (modified) llvm/test/MC/RISCV/rv32xtheadmempair-invalid.s (+4-4)
- (modified) llvm/test/MC/RISCV/rv32zcmp-invalid.s (+1-1)
- (modified) llvm/test/MC/RISCV/rv64xtheadmempair-invalid.s (+6-6)
- (modified) llvm/test/MC/RISCV/rv64zcmp-invalid.s (+1-1)
- (modified) llvm/test/MC/RISCV/rvv/invalid.s (+130-130)
- (modified) llvm/test/MC/RISCV/rvv/xsfvcp-invalid.s (+4-4)
- (modified) llvm/test/MC/RISCV/rvv/zvbb-invalid.s (+3-3)
- (modified) llvm/test/MC/RISCV/rvv/zvkned-invalid.s (+5-5)
- (modified) llvm/test/MC/RISCV/rvv/zvknh-invalid.s (+6-6)
- (modified) llvm/test/MC/RISCV/rvv/zvksed-invalid.s (+1-1)
- (modified) llvm/test/MC/RISCV/rvv/zvksh-invalid.s (+2-2)
``````````diff
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index 6af1d5010d3a4..d2a23ce6a64f5 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -2829,12 +2829,12 @@ bool RISCVAsmParser::parseDirectiveOption() {
if (isDigit(Arch.back()))
return Error(
- Loc, "Extension version number parsing not currently implemented");
+ Loc, "extension version number parsing not currently implemented");
std::string Feature = RISCVISAInfo::getTargetFeatureForExtension(Arch);
if (!enableExperimentalExtension() &&
StringRef(Feature).starts_with("experimental-"))
- return Error(Loc, "Unexpected experimental extensions.");
+ return Error(Loc, "unexpected experimental extensions");
auto Ext = llvm::lower_bound(RISCVFeatureKV, Feature);
if (Ext == std::end(RISCVFeatureKV) || StringRef(Ext->Key) != Feature)
return Error(Loc, "unknown extension feature");
@@ -2867,9 +2867,9 @@ bool RISCVAsmParser::parseDirectiveOption() {
if (getSTI().hasFeature(Feature.Value) &&
Feature.Implies.test(Ext->Value))
return Error(Loc,
- Twine("Can't disable ") + Ext->Key + " extension, " +
+ Twine("can't disable ") + Ext->Key + " extension; " +
Feature.Key + " extension requires " + Ext->Key +
- " extension be enabled");
+ " extension");
}
clearFeatureBits(Ext->Value, Ext->Key);
@@ -3382,8 +3382,8 @@ bool RISCVAsmParser::validateInstruction(MCInst &Inst,
unsigned TempReg = Inst.getOperand(1).getReg();
if (DestReg == TempReg) {
SMLoc Loc = Operands.back()->getStartLoc();
- return Error(Loc, "The temporary vector register cannot be the same as "
- "the destination register.");
+ return Error(Loc, "the temporary vector register cannot be the same as "
+ "the destination register");
}
}
@@ -3395,8 +3395,7 @@ bool RISCVAsmParser::validateInstruction(MCInst &Inst,
// The encoding with rd1 == rd2 == rs1 is reserved for XTHead load pair.
if (Rs1 == Rd1 && Rs1 == Rd2) {
SMLoc Loc = Operands[1]->getStartLoc();
- return Error(Loc, "The source register and destination registers "
- "cannot be equal.");
+ return Error(Loc, "rs1, rd1, and rd2 cannot all be the same");
}
}
@@ -3405,7 +3404,7 @@ bool RISCVAsmParser::validateInstruction(MCInst &Inst,
unsigned Rd2 = Inst.getOperand(1).getReg();
if (Rd1 == Rd2) {
SMLoc Loc = Operands[1]->getStartLoc();
- return Error(Loc, "'rs1' and 'rs2' must be different.");
+ return Error(Loc, "rs1 and rs2 must be different");
}
}
@@ -3416,10 +3415,10 @@ bool RISCVAsmParser::validateInstruction(MCInst &Inst,
// depending on the data width.
if (IsTHeadMemPair32 && Inst.getOperand(4).getImm() != 3) {
SMLoc Loc = Operands.back()->getStartLoc();
- return Error(Loc, "Operand must be constant 3.");
+ return Error(Loc, "operand must be constant 3");
} else if (IsTHeadMemPair64 && Inst.getOperand(4).getImm() != 4) {
SMLoc Loc = Operands.back()->getStartLoc();
- return Error(Loc, "Operand must be constant 4.");
+ return Error(Loc, "operand must be constant 4");
}
const MCInstrDesc &MCID = MII.get(Opcode);
@@ -3434,14 +3433,14 @@ bool RISCVAsmParser::validateInstruction(MCInst &Inst,
if (MCID.TSFlags & RISCVII::VS1Constraint) {
unsigned VCIXRs1 = Inst.getOperand(Inst.getNumOperands() - 1).getReg();
if (VCIXDst == VCIXRs1)
- return Error(VCIXDstLoc, "The destination vector register group cannot"
- " overlap the source vector register group.");
+ return Error(VCIXDstLoc, "the destination vector register group cannot"
+ " overlap the source vector register group");
}
if (MCID.TSFlags & RISCVII::VS2Constraint) {
unsigned VCIXRs2 = Inst.getOperand(Inst.getNumOperands() - 2).getReg();
if (VCIXDst == VCIXRs2)
- return Error(VCIXDstLoc, "The destination vector register group cannot"
- " overlap the source vector register group.");
+ return Error(VCIXDstLoc, "the destination vector register group cannot"
+ " overlap the source vector register group");
}
return false;
}
@@ -3457,14 +3456,14 @@ bool RISCVAsmParser::validateInstruction(MCInst &Inst,
if (MCID.TSFlags & RISCVII::VS2Constraint) {
unsigned CheckReg = Inst.getOperand(Offset + 1).getReg();
if (DestReg == CheckReg)
- return Error(Loc, "The destination vector register group cannot overlap"
- " the source vector register group.");
+ return Error(Loc, "the destination vector register group cannot overlap"
+ " the source vector register group");
}
if ((MCID.TSFlags & RISCVII::VS1Constraint) && Inst.getOperand(Offset + 2).isReg()) {
unsigned CheckReg = Inst.getOperand(Offset + 2).getReg();
if (DestReg == CheckReg)
- return Error(Loc, "The destination vector register group cannot overlap"
- " the source vector register group.");
+ return Error(Loc, "the destination vector register group cannot overlap"
+ " the source vector register group");
}
if ((MCID.TSFlags & RISCVII::VMConstraint) && (DestReg == RISCV::V0)) {
// vadc, vsbc are special cases. These instructions have no mask register.
@@ -3474,7 +3473,7 @@ bool RISCVAsmParser::validateInstruction(MCInst &Inst,
Opcode == RISCV::VSBC_VXM || Opcode == RISCV::VFMERGE_VFM ||
Opcode == RISCV::VMERGE_VIM || Opcode == RISCV::VMERGE_VVM ||
Opcode == RISCV::VMERGE_VXM)
- return Error(Loc, "The destination vector register group cannot be V0.");
+ return Error(Loc, "the destination vector register group cannot be V0");
// Regardless masked or unmasked version, the number of operands is the
// same. For example, "viota.m v0, v2" is "viota.m v0, v2, NoRegister"
@@ -3485,8 +3484,8 @@ bool RISCVAsmParser::validateInstruction(MCInst &Inst,
"Unexpected register for mask operand");
if (DestReg == CheckReg)
- return Error(Loc, "The destination vector register group cannot overlap"
- " the mask register.");
+ return Error(Loc, "the destination vector register group cannot overlap"
+ " the mask register");
}
return false;
}
diff --git a/llvm/test/MC/RISCV/option-invalid.s b/llvm/test/MC/RISCV/option-invalid.s
index ee520e08746a3..7f6de5f38c528 100644
--- a/llvm/test/MC/RISCV/option-invalid.s
+++ b/llvm/test/MC/RISCV/option-invalid.s
@@ -34,14 +34,14 @@
# CHECK: :[[#@LINE+1]]:18: error: expected comma
.option arch, +c foo
-# CHECK: :[[#@LINE+1]]:16: error: Extension version number parsing not currently implemented
+# CHECK: :[[#@LINE+1]]:16: error: extension version number parsing not currently implemented
.option arch, +c2p0
.option arch, +d
-# CHECK: :[[#@LINE+1]]:16: error: Can't disable f extension, d extension requires f extension be enabled
+# CHECK: :[[#@LINE+1]]:16: error: can't disable f extension; d extension requires f extension
.option arch, -f
-# CHECK: :[[#@LINE+1]]:16: error: Can't disable zicsr extension, f extension requires zicsr extension be enabled
+# CHECK: :[[#@LINE+1]]:16: error: can't disable zicsr extension; f extension requires zicsr extension
.option arch, -zicsr
# CHECK: :[[#@LINE+1]]:20: error: 'f' and 'zfinx' extensions are incompatible
diff --git a/llvm/test/MC/RISCV/rv32xtheadmempair-invalid.s b/llvm/test/MC/RISCV/rv32xtheadmempair-invalid.s
index 94319dea1c170..9124218c1f8f5 100644
--- a/llvm/test/MC/RISCV/rv32xtheadmempair-invalid.s
+++ b/llvm/test/MC/RISCV/rv32xtheadmempair-invalid.s
@@ -8,13 +8,13 @@ th.sdd a0, a1, (a2) # CHECK: [[@LINE]]:1: error: too few operands for in
th.sdd a0, a1, (a2), 3, 5 # CHECK: [[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
th.lwud t0, t1, (t2), 5, 4 # CHECK: [[@LINE]]:23: error: immediate must be an integer in the range [0, 3]
th.lwud t0, t1, (t2) # CHECK: [[@LINE]]:1: error: too few operands for instruction
-th.lwud t0, t1, (t2), 3, 5 # CHECK: [[@LINE]]:26: error: Operand must be constant 3.
+th.lwud t0, t1, (t2), 3, 5 # CHECK: [[@LINE]]:26: error: operand must be constant 3
th.lwd a3, a4, (a5), 5, 4 # CHECK: [[@LINE]]:22: error: immediate must be an integer in the range [0, 3]
th.lwd a3, a4, (a5) # CHECK: [[@LINE]]:1: error: too few operands for instruction
-th.lwd a3, a4, (a5), 3, 5 # CHECK: [[@LINE]]:25: error: Operand must be constant 3.
+th.lwd a3, a4, (a5), 3, 5 # CHECK: [[@LINE]]:25: error: operand must be constant 3
th.swd t3, t4, (t5), 5, 4 # CHECK: [[@LINE]]:22: error: immediate must be an integer in the range [0, 3]
th.swd t3, t4, (t5) # CHECK: [[@LINE]]:1: error: too few operands for instruction
-th.swd t3, t4, (t5), 3, 5 # CHECK: [[@LINE]]:25: error: Operand must be constant 3.
-th.lwud x6, x6, (x6), 2, 3 # CHECK: [[@LINE]]:9: error: The source register and destination registers cannot be equal.
+th.swd t3, t4, (t5), 3, 5 # CHECK: [[@LINE]]:25: error: operand must be constant 3
+th.lwud x6, x6, (x6), 2, 3 # CHECK: [[@LINE]]:9: error: rs1, rd1, and rd2 cannot all be the same
th.ldd t0, t1, (t2), 2, 4 # CHECK: [[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
th.sdd t0, t1, (t2), 2, 4 # CHECK: [[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
diff --git a/llvm/test/MC/RISCV/rv32zcmp-invalid.s b/llvm/test/MC/RISCV/rv32zcmp-invalid.s
index 1acea187585f8..2ed82bc55be3f 100644
--- a/llvm/test/MC/RISCV/rv32zcmp-invalid.s
+++ b/llvm/test/MC/RISCV/rv32zcmp-invalid.s
@@ -4,7 +4,7 @@
# CHECK-ERROR: error: invalid operand for instruction
cm.mvsa01 a1, a2
-# CHECK-ERROR: error: 'rs1' and 'rs2' must be different
+# CHECK-ERROR: error: rs1 and rs2 must be different
cm.mvsa01 s0, s0
# CHECK-ERROR: error: invalid operand for instruction
diff --git a/llvm/test/MC/RISCV/rv64xtheadmempair-invalid.s b/llvm/test/MC/RISCV/rv64xtheadmempair-invalid.s
index cf56a1fcccaf8..342db21bbca62 100644
--- a/llvm/test/MC/RISCV/rv64xtheadmempair-invalid.s
+++ b/llvm/test/MC/RISCV/rv64xtheadmempair-invalid.s
@@ -2,17 +2,17 @@
th.ldd t0, t1, (t2), 5, 4 # CHECK: [[@LINE]]:22: error: immediate must be an integer in the range [0, 3]
th.ldd t0, t1, (t2) # CHECK: [[@LINE]]:1: error: too few operands for instruction
-th.ldd t0, t1, (t2), 3, 5 # CHECK: [[@LINE]]:25: error: Operand must be constant 4.
+th.ldd t0, t1, (t2), 3, 5 # CHECK: [[@LINE]]:25: error: operand must be constant 4
th.sdd a0, a1, (a2), 5, 4 # CHECK: [[@LINE]]:22: error: immediate must be an integer in the range [0, 3]
th.sdd a0, a1, (a2) # CHECK: [[@LINE]]:1: error: too few operands for instruction
-th.sdd a0, a1, (a2), 3, 5 # CHECK: [[@LINE]]:25: error: Operand must be constant 4.
+th.sdd a0, a1, (a2), 3, 5 # CHECK: [[@LINE]]:25: error: operand must be constant 4
th.lwud t0, t1, (t2), 5, 4 # CHECK: [[@LINE]]:23: error: immediate must be an integer in the range [0, 3]
th.lwud t0, t1, (t2) # CHECK: [[@LINE]]:1: error: too few operands for instruction
-th.lwud t0, t1, (t2), 3, 5 # CHECK: [[@LINE]]:26: error: Operand must be constant 3.
+th.lwud t0, t1, (t2), 3, 5 # CHECK: [[@LINE]]:26: error: operand must be constant 3
th.lwd a3, a4, (a5), 5, 4 # CHECK: [[@LINE]]:22: error: immediate must be an integer in the range [0, 3]
th.lwd a3, a4, (a5) # CHECK: [[@LINE]]:1: error: too few operands for instruction
-th.lwd a3, a4, (a5), 3, 5 # CHECK: [[@LINE]]:25: error: Operand must be constant 3.
+th.lwd a3, a4, (a5), 3, 5 # CHECK: [[@LINE]]:25: error: operand must be constant 3
th.swd t3, t4, (t5), 5, 4 # CHECK: [[@LINE]]:22: error: immediate must be an integer in the range [0, 3]
th.swd t3, t4, (t5) # CHECK: [[@LINE]]:1: error: too few operands for instruction
-th.swd t3, t4, (t5), 3, 5 # CHECK: [[@LINE]]:25: error: Operand must be constant 3.
-th.lwud x6, x6, (x6), 2, 3 # CHECK: [[@LINE]]:9: error: The source register and destination registers cannot be equal.
+th.swd t3, t4, (t5), 3, 5 # CHECK: [[@LINE]]:25: error: operand must be constant 3
+th.lwud x6, x6, (x6), 2, 3 # CHECK: [[@LINE]]:9: error: rs1, rd1, and rd2 cannot all be the same
diff --git a/llvm/test/MC/RISCV/rv64zcmp-invalid.s b/llvm/test/MC/RISCV/rv64zcmp-invalid.s
index bf34554095ea5..8f353e8a7bb47 100644
--- a/llvm/test/MC/RISCV/rv64zcmp-invalid.s
+++ b/llvm/test/MC/RISCV/rv64zcmp-invalid.s
@@ -4,7 +4,7 @@
# CHECK-ERROR: error: invalid operand for instruction
cm.mvsa01 a1, a2
-# CHECK-ERROR: error: 'rs1' and 'rs2' must be different
+# CHECK-ERROR: error: rs1 and rs2 must be different
cm.mvsa01 s0, s0
# CHECK-ERROR: error: invalid operand for instruction
diff --git a/llvm/test/MC/RISCV/rvv/invalid.s b/llvm/test/MC/RISCV/rvv/invalid.s
index 09fd2c3bebf03..8c50f7ed048ca 100644
--- a/llvm/test/MC/RISCV/rvv/invalid.s
+++ b/llvm/test/MC/RISCV/rvv/invalid.s
@@ -96,471 +96,471 @@ vmslt.vi v1, v2, 17
# CHECK-ERROR: immediate must be in the range [-15, 16]
viota.m v0, v2, v0.t
-# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+# CHECK-ERROR: the destination vector register group cannot overlap the mask register
# CHECK-ERROR-LABEL: viota.m v0, v2, v0.t
viota.m v2, v2
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR: the destination vector register group cannot overlap the source vector register group
# CHECK-ERROR-LABEL: viota.m v2, v2
vfwcvt.xu.f.v v0, v2, v0.t
-# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+# CHECK-ERROR: the destination vector register group cannot overlap the mask register
# CHECK-ERROR-LABEL: vfwcvt.xu.f.v v0, v2, v0.t
vfwcvt.xu.f.v v2, v2
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR: the destination vector register group cannot overlap the source vector register group
# CHECK-ERROR-LABEL: vfwcvt.xu.f.v v2, v2
vfwcvt.x.f.v v0, v2, v0.t
-# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+# CHECK-ERROR: the destination vector register group cannot overlap the mask register
# CHECK-ERROR-LABEL: vfwcvt.x.f.v v0, v2, v0.t
vfwcvt.x.f.v v2, v2
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR: the destination vector register group cannot overlap the source vector register group
# CHECK-ERROR-LABEL: vfwcvt.x.f.v v2, v2
vfwcvt.f.xu.v v0, v2, v0.t
-# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+# CHECK-ERROR: the destination vector register group cannot overlap the mask register
# CHECK-ERROR-LABEL: vfwcvt.f.xu.v v0, v2, v0.t
vfwcvt.f.xu.v v2, v2
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR: the destination vector register group cannot overlap the source vector register group
# CHECK-ERROR-LABEL: vfwcvt.f.xu.v v2, v2
vfwcvt.f.x.v v0, v2, v0.t
-# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+# CHECK-ERROR: the destination vector register group cannot overlap the mask register
# CHECK-ERROR-LABEL: vfwcvt.f.x.v v0, v2, v0.t
vfwcvt.f.x.v v2, v2
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR: the destination vector register group cannot overlap the source vector register group
# CHECK-ERROR-LABEL: vfwcvt.f.x.v v2, v2
vfwcvt.f.f.v v0, v2, v0.t
-# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+# CHECK-ERROR: the destination vector register group cannot overlap the mask register
# CHECK-ERROR-LABEL: vfwcvt.f.f.v v0, v2, v0.t
vfwcvt.f.f.v v2, v2
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR: the destination vector register group cannot overlap the source vector register group
# CHECK-ERROR-LABEL: vfwcvt.f.f.v v2, v2
vslideup.vx v0, v2, a0, v0.t
-# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+# CHECK-ERROR: the destination vector register group cannot overlap the mask register
# CHECK-ERROR-LABEL: vslideup.vx v0, v2, a0, v0.t
vslideup.vx v2, v2, a0
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR: the destination vector register group cannot overlap the source vector register group
# CHECK-ERROR-LABEL: vslideup.vx v2, v2, a0
vslideup.vi v0, v2, 31, v0.t
-# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+# CHECK-ERROR: the destination vector register group cannot overlap the mask register
# CHECK-ERROR-LABEL: vslideup.vi v0, v2, 31, v0.t
vslideup.vi v2, v2, 31
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR: the destination vector register group cannot overlap the source vector register group
# CHECK-ERROR-LABEL: vslideup.vi v2, v2, 31
vslide1up.vx v0, v2, a0, v0.t
-# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+# CHECK-ERROR: the destination vector register group cannot overlap the mask register
# CHECK-ERROR-LABEL: vslide1up.vx v0, v2, a0, v0.t
vslide1up.vx v2, v2, a0
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR: the destination vector register group cannot overlap the source vector register group
# CHECK-ERROR-LABEL: vslide1up.vx v2, v2, a0
vrgather.vv v0, v2, v4, v0.t
-# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+# CHECK-ERROR: the destination vector register group cannot overlap the mask register
# CHECK-ERROR-LABEL: vrgather.vv v0, v2, v4, v0.t
vrgather.vv v2, v2, v4
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR: the destination vector register group cannot overlap the source vector register group
# CHECK-ERROR-LABEL: vrgather.vv v2, v2, v4
vrgather.vx v0, v2, a0, v0.t
-# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+# CHECK-ERROR: the destination vector register group cannot overlap the mask register
# CHECK-ERROR-LABEL: vrgather.vx v0, v2, a0, v0.t
vrgather.vx v2, v2, a0
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR: the destination vector register group cannot overlap the source vector register group
# CHECK-ERROR-LABEL: vrgather.vx v2, v2, a0
vrgather.vi v0, v2, 31, v0.t
-# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+# CHECK-ERROR: the destination vector register group cannot overlap the mask register
# CHECK-ERROR-LABEL: vrgather.vi v0, v2, 31, v0.t
vrgather.vi v2, v2, 31
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR: the destination vector register group cannot overlap the source vector register group
# CHECK-ERROR-LABEL: vrgather.vi v2, v2, 31
vwaddu.vv v0, v2, v4, v0.t
-# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+# CHECK-ERROR: the destination vector register group cannot overlap the mask register
# CHECK-ERROR-LABEL: vwaddu.vv v0, v2, v4, v0.t
vwaddu.vv v2, v2, v4
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR: the destination vector register group cannot overlap the source vector register group
# CHECK-ERROR-LABEL: vwaddu.vv v2, v2, v4
vwsubu.vv v0, v...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/92024
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