[llvm] [RISCV] Only allow up to e64 in vsetvli (PR #92010)

[Palmer Dabbelt via llvm-commits]

https://github.com/palmer-dabbelt created https://github.com/llvm/llvm-project/pull/92010

These larger SEWs aren't in the ratified V spec.  Thanks to dzaima and sorear on IRC for pointing this one out.

>From 9e10eade15efb91215e32b7d62f39936fa79a59b Mon Sep 17 00:00:00 2001
From: Palmer Dabbelt <palmer at rivosinc.com>
Date: Mon, 13 May 2024 11:45:08 -0700
Subject: [PATCH] [RISCV] Only allow up to e64 in vsetvli

These larger SEWs aren't in the ratified V spec.  Thanks to dzaima and
sorear on IRC for pointing this one out.

Signed-off-by: Palmer Dabbelt <palmer at rivosinc.com>
---
 llvm/include/llvm/TargetParser/RISCVTargetParser.h | 2 +-
 llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/llvm/include/llvm/TargetParser/RISCVTargetParser.h b/llvm/include/llvm/TargetParser/RISCVTargetParser.h
index cdd19189f8dc7..5b1494efe7bdc 100644
--- a/llvm/include/llvm/TargetParser/RISCVTargetParser.h
+++ b/llvm/include/llvm/TargetParser/RISCVTargetParser.h
@@ -61,7 +61,7 @@ enum {
 namespace RISCVVType {
 // Is this a SEW value that can be encoded into the VTYPE format.
 inline static bool isValidSEW(unsigned SEW) {
-  return isPowerOf2_32(SEW) && SEW >= 8 && SEW <= 1024;
+  return isPowerOf2_32(SEW) && SEW >= 8 && SEW <= 64;
 }
 
 // Is this a LMUL value that can be encoded into the VTYPE format.
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index 123b37442329f..6bdd038bd07e9 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -2227,7 +2227,7 @@ bool RISCVAsmParser::generateVTypeError(SMLoc ErrorLoc) {
   return Error(
       ErrorLoc,
       "operand must be "
-      "e[8|16|32|64|128|256|512|1024],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]");
+      "e[8|16|32|64],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]");
 }
 
 ParseStatus RISCVAsmParser::parseMaskReg(OperandVector &Operands) {