[llvm] 4a67f80 - [test] Fix check prefixes
Fangrui Song via llvm-commits
llvm-commits at lists.llvm.org
Mon May 13 11:25:17 PDT 2024
Author: Fangrui Song
Date: 2024-05-13T11:25:12-07:00
New Revision: 4a67f809828e11988c6a097cb400fd7cbbf47628
URL: https://github.com/llvm/llvm-project/commit/4a67f809828e11988c6a097cb400fd7cbbf47628
DIFF: https://github.com/llvm/llvm-project/commit/4a67f809828e11988c6a097cb400fd7cbbf47628.diff
LOG: [test] Fix check prefixes
Added:
Modified:
llvm/test/CodeGen/AArch64/aarch64_tree_tests.ll
llvm/test/CodeGen/SPARC/inlineasm-bad.ll
llvm/test/MC/AArch64/SVE/index.s
llvm/test/MC/XCOFF/inlineasm.s
llvm/test/Transforms/PhaseOrdering/lifetime-sanitizer.ll
llvm/test/tools/dsymutil/ARM/dwarf5-macho.test
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/aarch64_tree_tests.ll b/llvm/test/CodeGen/AArch64/aarch64_tree_tests.ll
index 0a06765a8f75b..f66f96cf463bb 100644
--- a/llvm/test/CodeGen/AArch64/aarch64_tree_tests.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64_tree_tests.ll
@@ -1,19 +1,18 @@
-; RUN: llc < %s | FileCheck %s
+; RUN: llc < %s | FileCheck %s
; ModuleID = 'aarch64_tree_tests.bc'
target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
target triple = "arm64--linux-gnu"
-; FIXME: Misspelled CHECK-LABEL
-; CHECK-LABLE: @aarch64_tree_tests_and
-; CHECK: .hword 32768
-; CHECK: .hword 32767
-; CHECK: .hword 4664
-; CHECK: .hword 32767
-; CHECK: .hword 32768
-; CHECK: .hword 32768
-; CHECK: .hword 0
-; CHECK: .hword 0
+; CHECK-LABEL: .LCPI0_0:
+; CHECK-NEXT: .hword 32768
+; CHECK-NEXT: .hword 32767
+; CHECK-NEXT: .hword 4664
+; CHECK-NEXT: .hword 32767
+; CHECK-NEXT: .hword 32768
+; CHECK-NEXT: .hword 32768
+; CHECK-NEXT: .hword 0
+; CHECK-NEXT: .hword 0
; Function Attrs: nounwind readnone
define <8 x i16> @aarch64_tree_tests_and(<8 x i16> %a) {
@@ -23,16 +22,15 @@ entry:
ret <8 x i16> %ret
}
-; FIXME: Misspelled CHECK-LABEL
-; CHECK-LABLE: @aarch64_tree_tests_or
-; CHECK: .hword 32768
-; CHECK: .hword 32766
-; CHECK: .hword 4664
-; CHECK: .hword 32766
-; CHECK: .hword 32768
-; CHECK: .hword 32768
-; CHECK: .hword 65535
-; CHECK: .hword 65535
+; CHECK-LABEL: .LCPI1_0:
+; CHECK-NEXT: .hword 32768
+; CHECK-NEXT: .hword 32766
+; CHECK-NEXT: .hword 4664
+; CHECK-NEXT: .hword 32766
+; CHECK-NEXT: .hword 32768
+; CHECK-NEXT: .hword 32768
+; CHECK-NEXT: .hword 65535
+; CHECK-NEXT: .hword 65535
; Function Attrs: nounwind readnone
define <8 x i16> @aarch64_tree_tests_or(<8 x i16> %a) {
diff --git a/llvm/test/CodeGen/SPARC/inlineasm-bad.ll b/llvm/test/CodeGen/SPARC/inlineasm-bad.ll
index 07eb67df6e5f7..bfcf98ed7fd51 100644
--- a/llvm/test/CodeGen/SPARC/inlineasm-bad.ll
+++ b/llvm/test/CodeGen/SPARC/inlineasm-bad.ll
@@ -12,9 +12,8 @@ entry:
ret void
}
-; CHECK-label:test_twinword_error
-; CHECK: error: Hi part of pair should point to an even-numbered register
-; CHECK: error: (note that in some cases it might be necessary to manually bind the input/output registers instead of relying on automatic allocation)
+; CHECK: <unknown>:0: error: Hi part of pair should point to an even-numbered register
+; CHECK: <unknown>:0: error: (note that in some cases it might be necessary to manually bind the input/output registers instead of relying on automatic allocation)
define i64 @test_twinword_error(){
%1 = tail call i64 asm sideeffect "rd %asr5, ${0:L} \0A\09 srlx ${0:L}, 32, ${0:H}", "={i1}"()
diff --git a/llvm/test/MC/AArch64/SVE/index.s b/llvm/test/MC/AArch64/SVE/index.s
index c06fab25a82f4..d4c106b9f0bf4 100644
--- a/llvm/test/MC/AArch64/SVE/index.s
+++ b/llvm/test/MC/AArch64/SVE/index.s
@@ -180,16 +180,16 @@ index z21.b, w10, w21
// CHECK-UNKNOWN: 04354d55 <unknown>
index z31.h, wzr, wzr
-// check-inst: index z31.h, wzr, wzr
-// check-encoding: [0xff,0x4f,0x7f,0x04]
-// check-error: instruction requires: sve or sme
-// check-unknown: ff 4f 7f 04 <unknown>
+// CHECK-INST: index z31.h, wzr, wzr
+// CHECK-ENCODING: [0xff,0x4f,0x7f,0x04]
+// CHECK-ERROR: instruction requires: sve or sme
+// CHECK-UNKNOWN: 047f4fff <unknown>
index z0.h, w0, w0
-// check-inst: index z0.h, w0, w0
-// check-encoding: [0x00,0x4c,0x60,0x04]
-// check-error: instruction requires: sve or sme
-// check-unknown: 00 4c 60 04 <unknown>
+// CHECK-INST: index z0.h, w0, w0
+// CHECK-ENCODING: [0x00,0x4c,0x60,0x04]
+// CHECK-ERROR: instruction requires: sve or sme
+// CHECK-UNKNOWN: 04604c00 <unknown>
index z31.s, wzr, wzr
// CHECK-INST: index z31.s, wzr, wzr
diff --git a/llvm/test/MC/XCOFF/inlineasm.s b/llvm/test/MC/XCOFF/inlineasm.s
index 85a40024711a1..e92d403f45a3a 100644
--- a/llvm/test/MC/XCOFF/inlineasm.s
+++ b/llvm/test/MC/XCOFF/inlineasm.s
@@ -1,6 +1,6 @@
// RUN: llvm-mc -filetype=asm -triple powerpc-ibm-aix-xcoff %s | FileCheck %s
-// CHECK-label: .csect .text[PR],2
+// CHECK-LABEL: .csect ..text..[PR],5
// CHECK:L..tmp0:
// CHECK-NEXT: lwarx 3, 0, 4
// CHECK-NEXT: cmpw 5, 3
diff --git a/llvm/test/Transforms/PhaseOrdering/lifetime-sanitizer.ll b/llvm/test/Transforms/PhaseOrdering/lifetime-sanitizer.ll
index 5f4d389265a86..21fa234535cad 100644
--- a/llvm/test/Transforms/PhaseOrdering/lifetime-sanitizer.ll
+++ b/llvm/test/Transforms/PhaseOrdering/lifetime-sanitizer.ll
@@ -1,11 +1,11 @@
-; RUN: opt < %s -O0 -S | FileCheck %s
-; RUN: opt < %s -O1 -S | FileCheck %s
-; RUN: opt < %s -O2 -S | FileCheck %s
-; RUN: opt < %s -O3 -S | FileCheck %s
-; RUN: opt < %s -passes='default<O0>' -S | FileCheck %s
-; RUN: opt < %s -passes='default<O1>' -S | FileCheck %s
-; RUN: opt < %s -passes='default<O2>' -S | FileCheck %s
-; RUN: opt < %s -passes='default<O3>' -S | FileCheck %s
+; RUN: opt < %s -O0 -S | FileCheck %s --check-prefixes=CHECK,NOOPT
+; RUN: opt < %s -O1 -S | FileCheck %s --check-prefixes=CHECK,OPT
+; RUN: opt < %s -O2 -S | FileCheck %s --check-prefixes=CHECK,OPT
+; RUN: opt < %s -O3 -S | FileCheck %s --check-prefixes=CHECK,OPT
+; RUN: opt < %s -passes='default<O0>' -S | FileCheck %s --check-prefixes=CHECK,NOOPT
+; RUN: opt < %s -passes='default<O1>' -S | FileCheck %s --check-prefixes=CHECK,OPT
+; RUN: opt < %s -passes='default<O2>' -S | FileCheck %s --check-prefixes=CHECK,OPT
+; RUN: opt < %s -passes='default<O3>' -S | FileCheck %s --check-prefixes=CHECK,OPT
declare void @llvm.lifetime.start.p0(i64, ptr nocapture)
declare void @llvm.lifetime.end.p0(i64, ptr nocapture)
@@ -63,7 +63,9 @@ entry:
call void @llvm.lifetime.start.p0(i64 1, ptr %text)
call void @llvm.lifetime.end.p0(i64 1, ptr %text)
- ; CHECK-NO: call void @llvm.lifetime
+ ; OPT-NOT: call void @llvm.lifetime
+ ; NOOPT: call void @llvm.lifetime.start
+ ; NOOPT-NEXT: call void @llvm.lifetime.end
call void @foo(ptr %text) ; Keep alloca alive
diff --git a/llvm/test/tools/dsymutil/ARM/dwarf5-macho.test b/llvm/test/tools/dsymutil/ARM/dwarf5-macho.test
index 5268324c2e100..08c8bba739281 100644
--- a/llvm/test/tools/dsymutil/ARM/dwarf5-macho.test
+++ b/llvm/test/tools/dsymutil/ARM/dwarf5-macho.test
@@ -109,16 +109,16 @@ CHECK-NEXT: 0x0000000e: [DW_RLE_offset_pair ]: {{.*}}[0x[[RANGELIST_OFFSET_STAR
CHECK-NEXT: 0x00000011: [DW_RLE_end_of_list ]
CHECK: .debug_names contents:
-CHECK-NEX:T Name Index @ 0x0 {
-CHECK-NEX:T Header {
-CHECK-NEX:T Length: 0x7C
-CHECK-NEX:T Format: DWARF32
-CHECK-NEX:T Version: 5
-CHECK-NEX:T CU count: 1
-CHECK-NEX:T Local TU count: 0
-CHECK-NEX:T Foreign TU count: 0
-CHECK-NEX:T Bucket count: 3
-CHECK-NEX:T Name count: 3
-CHECK-NEX:T Abbreviations table size: 0xD
-CHECK-NEX:T Augmentation: 'LLVM0700'
-CHECK-NEX:T }
+CHECK-NEXT: Name Index @ 0x0 {
+CHECK-NEXT: Header {
+CHECK-NEXT: Length:
+CHECK-NEXT: Format: DWARF32
+CHECK-NEXT: Version: 5
+CHECK-NEXT: CU count: 1
+CHECK-NEXT: Local TU count: 0
+CHECK-NEXT: Foreign TU count: 0
+CHECK-NEXT: Bucket count: 3
+CHECK-NEXT: Name count: 3
+CHECK-NEXT: Abbreviations table size:
+CHECK-NEXT: Augmentation: 'LLVM0700'
+CHECK-NEXT: }
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