[llvm] [LLVM][CodeGen][SVE] Improve custom lowering for EXTRACT_SUBVECTOR. (PR #90963)

[Paul Walker via llvm-commits]

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@@ -13856,45 +13856,52 @@ AArch64TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
 
 SDValue AArch64TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
                                                       SelectionDAG &DAG) const {
-  assert(Op.getValueType().isFixedLengthVector() &&
+  EVT VT = Op.getValueType();
+  assert(VT.isFixedLengthVector() &&
          "Only cases that extract a fixed length vector are supported!");
-
   EVT InVT = Op.getOperand(0).getValueType();
-  unsigned Idx = Op.getConstantOperandVal(1);
-  unsigned Size = Op.getValueSizeInBits();
 
   // If we don't have legal types yet, do nothing
-  if (!DAG.getTargetLoweringInfo().isTypeLegal(InVT))
+  if (!isTypeLegal(InVT))
     return SDValue();
 
-  if (InVT.isScalableVector()) {
-    // This will be matched by custom code during ISelDAGToDAG.
-    if (Idx == 0 && isPackedVectorType(InVT, DAG))
+  if (InVT.is128BitVector()) {
+    assert(VT.is64BitVector() && "Extracting unexpected vector type!");
----------------
paulwalker-arm wrote:

Yes. We can be sure that if the input is type legal then the result must also be type legal.  That means for operation legalisation the only NEON sized combination that can happen is extracting a 64-bit vector from a 128-bit vector.  The only exception is when the result type matches the input type and the index is zero, but that is a NOP that is handled within `SelectionDAG::getNode()` and so is not worth considering at this point in the pipeline.

https://github.com/llvm/llvm-project/pull/90963