[llvm] [AArch64][TargetParser] Move extension aliases into tablegen (PR #91970)
Tomas Matheson via llvm-commits
llvm-commits at lists.llvm.org
Mon May 13 10:00:54 PDT 2024
https://github.com/tmatheson-arm updated https://github.com/llvm/llvm-project/pull/91970
>From a577bf54336d166e8e0f27c8569542f86b3aa445 Mon Sep 17 00:00:00 2001
From: Tomas Matheson <tomas.matheson at arm.com>
Date: Mon, 13 May 2024 14:30:49 +0100
Subject: [PATCH 1/4] [AArch64] Move extension aliases into tablegen
Allow only one alias.
---
.../llvm/TargetParser/AArch64TargetParser.h | 16 ++++++++--------
llvm/lib/Target/AArch64/AArch64Features.td | 5 +++++
llvm/lib/TargetParser/AArch64TargetParser.cpp | 18 +++++-------------
llvm/utils/TableGen/ARMTargetDefEmitter.cpp | 6 +++++-
4 files changed, 23 insertions(+), 22 deletions(-)
diff --git a/llvm/include/llvm/TargetParser/AArch64TargetParser.h b/llvm/include/llvm/TargetParser/AArch64TargetParser.h
index 20c3f95173c28..71178c078c19f 100644
--- a/llvm/include/llvm/TargetParser/AArch64TargetParser.h
+++ b/llvm/include/llvm/TargetParser/AArch64TargetParser.h
@@ -18,6 +18,7 @@
#include "llvm/ADT/Bitset.h"
#include "llvm/ADT/StringMap.h"
#include "llvm/ADT/StringRef.h"
+#include "llvm/ADT/StringSet.h"
#include "llvm/Support/VersionTuple.h"
#include <array>
#include <vector>
@@ -114,11 +115,13 @@ using ExtensionBitset = Bitset<AEK_NUM_EXTENSIONS>;
// SubtargetFeature which may represent either an actual extension or some
// internal LLVM property.
struct ExtensionInfo {
- StringRef Name; // Human readable name, e.g. "profile".
- ArchExtKind ID; // Corresponding to the ArchExtKind, this
- // extensions representation in the bitfield.
- StringRef Feature; // -mattr enable string, e.g. "+spe"
- StringRef NegFeature; // -mattr disable string, e.g. "-spe"
+public:
+ StringRef Name; // Human readable name, e.g. "profile".
+ std::optional<StringRef> Alias; // An alias for this extension, if one exists.
+ ArchExtKind ID; // Corresponding to the ArchExtKind, this
+ // extensions representation in the bitfield.
+ StringRef Feature; // -mattr enable string, e.g. "+spe"
+ StringRef NegFeature; // -mattr disable string, e.g. "-spe"
CPUFeatures CPUFeature; // Function Multi Versioning (FMV) bitfield value
// set in __aarch64_cpu_features
StringRef DependentFeatures; // FMV enabled features string,
@@ -674,8 +677,6 @@ struct Alias {
inline constexpr Alias CpuAliases[] = {{"cobalt-100", "neoverse-n2"},
{"grace", "neoverse-v2"}};
-inline constexpr Alias ExtAliases[] = {{"rdma", "rdm"}};
-
const ExtensionInfo &getExtensionByID(ArchExtKind(ExtID));
bool getExtensionFeatures(
@@ -684,7 +685,6 @@ bool getExtensionFeatures(
StringRef getArchExtFeature(StringRef ArchExt);
StringRef resolveCPUAlias(StringRef CPU);
-StringRef resolveExtAlias(StringRef ArchExt);
// Information by Name
const ArchInfo *getArchForCpu(StringRef CPU);
diff --git a/llvm/lib/Target/AArch64/AArch64Features.td b/llvm/lib/Target/AArch64/AArch64Features.td
index 920ca7f4fbfcb..b9c26e99ae034 100644
--- a/llvm/lib/Target/AArch64/AArch64Features.td
+++ b/llvm/lib/Target/AArch64/AArch64Features.td
@@ -39,6 +39,10 @@ class Extension<
// not doing so.
string MArchName = TargetFeatureName;
+ // An alias that can be used on the command line, if the extension has one.
+ // Used for correcting historical names while remaining backwards compatible.
+ string MArchAlias = "";
+
// Function MultiVersioning (FMV) properties
// A C++ expression giving the number of the bit in the FMV ABI.
@@ -163,6 +167,7 @@ def FeatureOutlineAtomics : SubtargetFeature<"outline-atomics", "OutlineAtomics"
def FeatureFMV : SubtargetFeature<"fmv", "HasFMV", "true",
"Enable Function Multi Versioning support.">;
+let MArchAlias = "rdma" in
def FeatureRDM : Extension<"rdm", "RDM",
"Enable ARMv8.1 Rounding Double Multiply Add/Subtract instructions (FEAT_RDM)",
[FeatureNEON],
diff --git a/llvm/lib/TargetParser/AArch64TargetParser.cpp b/llvm/lib/TargetParser/AArch64TargetParser.cpp
index 026214e7e2eac..32db865f1feb3 100644
--- a/llvm/lib/TargetParser/AArch64TargetParser.cpp
+++ b/llvm/lib/TargetParser/AArch64TargetParser.cpp
@@ -12,6 +12,7 @@
//===----------------------------------------------------------------------===//
#include "llvm/TargetParser/AArch64TargetParser.h"
+#include "llvm/ADT/STLExtras.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/Format.h"
#include "llvm/Support/raw_ostream.h"
@@ -74,13 +75,6 @@ StringRef AArch64::resolveCPUAlias(StringRef Name) {
return Name;
}
-StringRef AArch64::resolveExtAlias(StringRef Name) {
- for (const auto &A : ExtAliases)
- if (A.AltName == Name)
- return A.Name;
- return Name;
-}
-
StringRef AArch64::getArchExtFeature(StringRef ArchExt) {
bool IsNegated = ArchExt.starts_with("no");
StringRef ArchExtBase = IsNegated ? ArchExt.drop_front(2) : ArchExt;
@@ -120,13 +114,11 @@ const AArch64::ArchInfo *AArch64::parseArch(StringRef Arch) {
return {};
}
-std::optional<AArch64::ExtensionInfo> AArch64::parseArchExtension(StringRef ArchExt) {
- // Resolve aliases first.
- ArchExt = resolveExtAlias(ArchExt);
-
- // Then find the Extension name.
+std::optional<AArch64::ExtensionInfo>
+AArch64::parseArchExtension(StringRef ArchExt) {
+ assert(!ArchExt.empty());
for (const auto &A : Extensions) {
- if (ArchExt == A.Name)
+ if (ArchExt == A.Name || ArchExt == A.Alias)
return A;
}
return {};
diff --git a/llvm/utils/TableGen/ARMTargetDefEmitter.cpp b/llvm/utils/TableGen/ARMTargetDefEmitter.cpp
index 4a46f2ea95869..0e90f57af4938 100644
--- a/llvm/utils/TableGen/ARMTargetDefEmitter.cpp
+++ b/llvm/utils/TableGen/ARMTargetDefEmitter.cpp
@@ -89,6 +89,10 @@ static void EmitARMTargetDef(RecordKeeper &RK, raw_ostream &OS) {
auto AEK = Rec->getValueAsString("ArchExtKindSpelling").upper();
OS << " ";
OS << "{\"" << Rec->getValueAsString("MArchName") << "\"";
+ if (auto Alias = Rec->getValueAsString("MArchAlias"); Alias.empty())
+ OS << ", {}";
+ else
+ OS << ", \"" << Alias << "\"";
OS << ", AArch64::" << AEK;
if (AEK == "AEK_NONE") {
// HACK: don't emit posfeat/negfeat strings for FMVOnlyExtensions.
@@ -102,7 +106,7 @@ static void EmitARMTargetDef(RecordKeeper &RK, raw_ostream &OS) {
OS << ", " << (uint64_t)Rec->getValueAsInt("FMVPriority");
OS << "},\n";
};
- OS << " {\"none\", AArch64::AEK_NONE, {}, {}, FEAT_INIT, \"\", "
+ OS << " {\"none\", {}, AArch64::AEK_NONE, {}, {}, FEAT_INIT, \"\", "
"ExtensionInfo::MaxFMVPriority},\n";
OS << "};\n"
<< "#undef EMIT_EXTENSIONS\n"
>From a8bd28789e7500eb02427829639075581b36d36f Mon Sep 17 00:00:00 2001
From: Tomas Matheson <tomas.matheson at arm.com>
Date: Mon, 13 May 2024 15:23:01 +0100
Subject: [PATCH 2/4] Remove unused code
---
llvm/include/llvm/TargetParser/AArch64TargetParser.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/llvm/include/llvm/TargetParser/AArch64TargetParser.h b/llvm/include/llvm/TargetParser/AArch64TargetParser.h
index 71178c078c19f..b662a74e5fc68 100644
--- a/llvm/include/llvm/TargetParser/AArch64TargetParser.h
+++ b/llvm/include/llvm/TargetParser/AArch64TargetParser.h
@@ -18,7 +18,6 @@
#include "llvm/ADT/Bitset.h"
#include "llvm/ADT/StringMap.h"
#include "llvm/ADT/StringRef.h"
-#include "llvm/ADT/StringSet.h"
#include "llvm/Support/VersionTuple.h"
#include <array>
#include <vector>
@@ -115,7 +114,6 @@ using ExtensionBitset = Bitset<AEK_NUM_EXTENSIONS>;
// SubtargetFeature which may represent either an actual extension or some
// internal LLVM property.
struct ExtensionInfo {
-public:
StringRef Name; // Human readable name, e.g. "profile".
std::optional<StringRef> Alias; // An alias for this extension, if one exists.
ArchExtKind ID; // Corresponding to the ArchExtKind, this
>From 8447b6e4c38e6e1428f79275e41cafc0c858553d Mon Sep 17 00:00:00 2001
From: Tomas Matheson <tomas.matheson at arm.com>
Date: Mon, 13 May 2024 15:26:06 +0100
Subject: [PATCH 3/4] remove unnecessary #include "llvm/ADT/STLExtras.h"
---
llvm/lib/TargetParser/AArch64TargetParser.cpp | 1 -
1 file changed, 1 deletion(-)
diff --git a/llvm/lib/TargetParser/AArch64TargetParser.cpp b/llvm/lib/TargetParser/AArch64TargetParser.cpp
index 32db865f1feb3..9f29e05e47eab 100644
--- a/llvm/lib/TargetParser/AArch64TargetParser.cpp
+++ b/llvm/lib/TargetParser/AArch64TargetParser.cpp
@@ -12,7 +12,6 @@
//===----------------------------------------------------------------------===//
#include "llvm/TargetParser/AArch64TargetParser.h"
-#include "llvm/ADT/STLExtras.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/Format.h"
#include "llvm/Support/raw_ostream.h"
>From fc5dda8996a85b0ceff19039f1640c31ecd84e19 Mon Sep 17 00:00:00 2001
From: Tomas Matheson <tomas.matheson at arm.com>
Date: Mon, 13 May 2024 17:15:44 +0100
Subject: [PATCH 4/4] [AArch64][TargetParser] move ArchInfo into tablegen
---
.../llvm/TargetParser/AArch64TargetParser.h | 48 +----
llvm/lib/Target/AArch64/AArch64Features.td | 173 +++++++++++-------
llvm/utils/TableGen/ARMTargetDefEmitter.cpp | 34 ++++
3 files changed, 144 insertions(+), 111 deletions(-)
diff --git a/llvm/include/llvm/TargetParser/AArch64TargetParser.h b/llvm/include/llvm/TargetParser/AArch64TargetParser.h
index b662a74e5fc68..b3fff3c99025a 100644
--- a/llvm/include/llvm/TargetParser/AArch64TargetParser.h
+++ b/llvm/include/llvm/TargetParser/AArch64TargetParser.h
@@ -239,8 +239,8 @@ enum ArchProfile { AProfile = 'A', RProfile = 'R', InvalidProfile = '?' };
struct ArchInfo {
VersionTuple Version; // Architecture version, major + minor.
ArchProfile Profile; // Architecuture profile
- StringRef Name; // Human readable name, e.g. "armv8.1-a"
- StringRef ArchFeature; // Command line feature flag, e.g. +v8a
+ StringRef Name; // Name as supplied to -march e.g. "armv8.1-a"
+ StringRef ArchFeature; // Name as supplied to -target-feature, e.g. "+v8a"
AArch64::ExtensionBitset
DefaultExts; // bitfield of default extensions ArchExtKind
@@ -289,48 +289,8 @@ struct ArchInfo {
static std::optional<ArchInfo> findBySubArch(StringRef SubArch);
};
-// clang-format off
-inline constexpr ArchInfo ARMV8A = { VersionTuple{8, 0}, AProfile, "armv8-a", "+v8a", (
- AArch64::ExtensionBitset({AArch64::AEK_FP, AArch64::AEK_SIMD})), };
-inline constexpr ArchInfo ARMV8_1A = { VersionTuple{8, 1}, AProfile, "armv8.1-a", "+v8.1a", (ARMV8A.DefaultExts |
- AArch64::ExtensionBitset({AArch64::AEK_CRC, AArch64::AEK_LSE, AArch64::AEK_RDM}))};
-inline constexpr ArchInfo ARMV8_2A = { VersionTuple{8, 2}, AProfile, "armv8.2-a", "+v8.2a", (ARMV8_1A.DefaultExts |
- AArch64::ExtensionBitset({AArch64::AEK_RAS}))};
-inline constexpr ArchInfo ARMV8_3A = { VersionTuple{8, 3}, AProfile, "armv8.3-a", "+v8.3a", (ARMV8_2A.DefaultExts |
- AArch64::ExtensionBitset({AArch64::AEK_FCMA, AArch64::AEK_JSCVT, AArch64::AEK_PAUTH, AArch64::AEK_RCPC}))};
-inline constexpr ArchInfo ARMV8_4A = { VersionTuple{8, 4}, AProfile, "armv8.4-a", "+v8.4a", (ARMV8_3A.DefaultExts |
- AArch64::ExtensionBitset({AArch64::AEK_DOTPROD}))};
-inline constexpr ArchInfo ARMV8_5A = { VersionTuple{8, 5}, AProfile, "armv8.5-a", "+v8.5a", (ARMV8_4A.DefaultExts)};
-inline constexpr ArchInfo ARMV8_6A = { VersionTuple{8, 6}, AProfile, "armv8.6-a", "+v8.6a", (ARMV8_5A.DefaultExts |
- AArch64::ExtensionBitset({AArch64::AEK_BF16, AArch64::AEK_I8MM}))};
-inline constexpr ArchInfo ARMV8_7A = { VersionTuple{8, 7}, AProfile, "armv8.7-a", "+v8.7a", (ARMV8_6A.DefaultExts)};
-inline constexpr ArchInfo ARMV8_8A = { VersionTuple{8, 8}, AProfile, "armv8.8-a", "+v8.8a", (ARMV8_7A.DefaultExts |
- AArch64::ExtensionBitset({AArch64::AEK_MOPS, AArch64::AEK_HBC}))};
-inline constexpr ArchInfo ARMV8_9A = { VersionTuple{8, 9}, AProfile, "armv8.9-a", "+v8.9a", (ARMV8_8A.DefaultExts |
- AArch64::ExtensionBitset({AArch64::AEK_SPECRES2, AArch64::AEK_CSSC, AArch64::AEK_RASV2}))};
-inline constexpr ArchInfo ARMV9A = { VersionTuple{9, 0}, AProfile, "armv9-a", "+v9a", (ARMV8_5A.DefaultExts |
- AArch64::ExtensionBitset({AArch64::AEK_FP16, AArch64::AEK_SVE, AArch64::AEK_SVE2}))};
-inline constexpr ArchInfo ARMV9_1A = { VersionTuple{9, 1}, AProfile, "armv9.1-a", "+v9.1a", (ARMV9A.DefaultExts |
- AArch64::ExtensionBitset({AArch64::AEK_BF16, AArch64::AEK_I8MM}))};
-inline constexpr ArchInfo ARMV9_2A = { VersionTuple{9, 2}, AProfile, "armv9.2-a", "+v9.2a", (ARMV9_1A.DefaultExts)};
-inline constexpr ArchInfo ARMV9_3A = { VersionTuple{9, 3}, AProfile, "armv9.3-a", "+v9.3a", (ARMV9_2A.DefaultExts |
- AArch64::ExtensionBitset({AArch64::AEK_MOPS, AArch64::AEK_HBC}))};
-inline constexpr ArchInfo ARMV9_4A = { VersionTuple{9, 4}, AProfile, "armv9.4-a", "+v9.4a", (ARMV9_3A.DefaultExts |
- AArch64::ExtensionBitset({AArch64::AEK_SPECRES2, AArch64::AEK_CSSC, AArch64::AEK_RASV2}))};
-inline constexpr ArchInfo ARMV9_5A = { VersionTuple{9, 5}, AProfile, "armv9.5-a", "+v9.5a", (ARMV9_4A.DefaultExts |
- AArch64::ExtensionBitset({AArch64::AEK_CPA}))};
-// For v8-R, we do not enable crypto and align with GCC that enables a more minimal set of optional architecture extensions.
-inline constexpr ArchInfo ARMV8R = { VersionTuple{8, 0}, RProfile, "armv8-r", "+v8r", (ARMV8_5A.DefaultExts |
- AArch64::ExtensionBitset({AArch64::AEK_SSBS,
- AArch64::AEK_FP16, AArch64::AEK_FP16FML, AArch64::AEK_SB}).flip(AArch64::AEK_LSE))};
-// clang-format on
-
-// The set of all architectures
-static constexpr std::array<const ArchInfo *, 17> ArchInfos = {
- &ARMV8A, &ARMV8_1A, &ARMV8_2A, &ARMV8_3A, &ARMV8_4A, &ARMV8_5A,
- &ARMV8_6A, &ARMV8_7A, &ARMV8_8A, &ARMV8_9A, &ARMV9A, &ARMV9_1A,
- &ARMV9_2A, &ARMV9_3A, &ARMV9_4A, &ARMV9_5A, &ARMV8R,
-};
+#define EMIT_ARCHITECTURES
+#include "llvm/TargetParser/AArch64TargetParserDef.inc"
// Details of a specific CPU.
struct CpuInfo {
diff --git a/llvm/lib/Target/AArch64/AArch64Features.td b/llvm/lib/Target/AArch64/AArch64Features.td
index b9c26e99ae034..e7562fdd289cc 100644
--- a/llvm/lib/Target/AArch64/AArch64Features.td
+++ b/llvm/lib/Target/AArch64/AArch64Features.td
@@ -792,77 +792,112 @@ def FeatureTLBIW : Extension<"tlbiw", "TLBIW",
//===----------------------------------------------------------------------===//
// Architectures.
//
-def HasV8_0aOps : SubtargetFeature<"v8a", "HasV8_0aOps", "true",
- "Support ARM v8.0a instructions", [FeatureEL2VMSA, FeatureEL3]>;
-
-def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
- "Support ARM v8.1a instructions", [HasV8_0aOps, FeatureCRC, FeatureLSE,
- FeatureRDM, FeaturePAN, FeatureLOR, FeatureVH]>;
-
-def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true",
- "Support ARM v8.2a instructions", [HasV8_1aOps, FeaturePsUAO,
- FeaturePAN_RWV, FeatureRAS, FeatureCCPP]>;
-
-def HasV8_3aOps : SubtargetFeature<"v8.3a", "HasV8_3aOps", "true",
- "Support ARM v8.3a instructions", [HasV8_2aOps, FeatureRCPC, FeaturePAuth,
- FeatureJS, FeatureCCIDX, FeatureComplxNum]>;
-
-def HasV8_4aOps : SubtargetFeature<"v8.4a", "HasV8_4aOps", "true",
- "Support ARM v8.4a instructions", [HasV8_3aOps, FeatureDotProd,
- FeatureNV, FeatureMPAM, FeatureDIT,
- FeatureTRACEV8_4, FeatureAM, FeatureSEL2, FeatureTLB_RMI,
- FeatureFlagM, FeatureRCPC_IMMO, FeatureLSE2]>;
+class Architecture64<
+ string spelling, // Spelling for C++ code
+ int major, int minor, string profile,
+ string st_field_name, string march_name, string target_feature_name,
+ list<SubtargetFeature> implied_features,
+ list<Extension> default_extensions
+> : SubtargetFeature<march_name, st_field_name, "true",
+ !strconcat(target_feature_name, " architecture"), implied_features> {
+ string Spelling = spelling;
+ int Major = major;
+ int Minor = minor;
+ string Profile = profile;
+ string MArchName = march_name;
+ string TargetFeatureName = target_feature_name;
+ list<Extension> DefaultExts = default_extensions; // Extensions enabled by default.
+}
-def HasV8_5aOps : SubtargetFeature<
- "v8.5a", "HasV8_5aOps", "true", "Support ARM v8.5a instructions",
+def HasV8_0aOps : Architecture64<"ARMV8A",
+ 8, 0, "AProfile",
+ "HasV8_0aOps", "armv8-a", "v8a",
+ [FeatureEL2VMSA, FeatureEL3],
+ [FeatureFPARMv8, FeatureNEON]>;
+def HasV8_1aOps : Architecture64<"ARMV8_1A",
+ 8, 1, "AProfile",
+ "HasV8_1aOps", "armv8.1-a", "+v8.1a",
+ [HasV8_0aOps, FeatureCRC, FeatureLSE, FeatureRDM, FeaturePAN, FeatureLOR, FeatureVH],
+ !listconcat(HasV8_0aOps.DefaultExts, [FeatureCRC, FeatureLSE, FeatureRDM])>;
+def HasV8_2aOps : Architecture64<"ARMV8_2A",
+ 8, 2, "AProfile",
+ "HasV8_2aOps", "armv8.2-a", "+v8.2a",
+ [HasV8_1aOps, FeaturePsUAO, FeaturePAN_RWV, FeatureRAS, FeatureCCPP],
+ !listconcat(HasV8_1aOps.DefaultExts, [FeatureRAS])>;
+def HasV8_3aOps : Architecture64<"ARMV8_3A",
+ 8, 3, "AProfile",
+ "HasV8_3aOps", "armv8.3-a", "+v8.3a",
+ [HasV8_2aOps, FeatureRCPC, FeaturePAuth, FeatureJS, FeatureCCIDX, FeatureComplxNum],
+ !listconcat(HasV8_2aOps.DefaultExts, [FeatureComplxNum, FeatureJS, FeaturePAuth, FeatureRCPC])>;
+def HasV8_4aOps : Architecture64<"ARMV8_4A",
+ 8, 4, "AProfile",
+ "HasV8_4aOps", "armv8.4-a", "+v8.4a",
+ [HasV8_3aOps, FeatureDotProd, FeatureNV, FeatureMPAM, FeatureDIT, FeatureTRACEV8_4, FeatureAM, FeatureSEL2, FeatureTLB_RMI, FeatureFlagM, FeatureRCPC_IMMO, FeatureLSE2],
+ !listconcat(HasV8_3aOps.DefaultExts, [FeatureDotProd])>;
+def HasV8_5aOps : Architecture64<"ARMV8_5A",
+ 8, 5, "AProfile",
+ "HasV8_5aOps", "armv8.5-a", "+v8.5a",
[HasV8_4aOps, FeatureAltFPCmp, FeatureFRInt3264, FeatureSpecRestrict,
FeatureSSBS, FeatureSB, FeaturePredRes, FeatureCacheDeepPersist,
- FeatureBranchTargetId]>;
-
-def HasV8_6aOps : SubtargetFeature<
- "v8.6a", "HasV8_6aOps", "true", "Support ARM v8.6a instructions",
+ FeatureBranchTargetId],
+ !listconcat(HasV8_4aOps.DefaultExts, [])>;
+def HasV8_6aOps : Architecture64<"ARMV8_6A",
+ 8, 6, "AProfile",
+ "HasV8_6aOps", "armv8.6-a", "+v8.6a",
[HasV8_5aOps, FeatureAMVS, FeatureBF16, FeatureFineGrainedTraps,
- FeatureEnhancedCounterVirtualization, FeatureMatMulInt8]>;
-
-def HasV8_7aOps : SubtargetFeature<
- "v8.7a", "HasV8_7aOps", "true", "Support ARM v8.7a instructions",
- [HasV8_6aOps, FeatureXS, FeatureWFxT, FeatureHCX]>;
-
-def HasV8_8aOps : SubtargetFeature<
- "v8.8a", "HasV8_8aOps", "true", "Support ARM v8.8a instructions",
- [HasV8_7aOps, FeatureHBC, FeatureMOPS, FeatureNMI]>;
-
-def HasV8_9aOps : SubtargetFeature<
- "v8.9a", "HasV8_9aOps", "true", "Support ARM v8.9a instructions",
+ FeatureEnhancedCounterVirtualization, FeatureMatMulInt8],
+ !listconcat(HasV8_5aOps.DefaultExts, [FeatureBF16, FeatureMatMulInt8])>;
+def HasV8_7aOps : Architecture64<"ARMV8_7A",
+ 8, 7, "AProfile",
+ "HasV8_7aOps", "armv8.7-a", "+v8.7a",
+ [HasV8_6aOps, FeatureXS, FeatureWFxT, FeatureHCX],
+ !listconcat(HasV8_6aOps.DefaultExts, [])>;
+def HasV8_8aOps : Architecture64<"ARMV8_8A",
+ 8, 8, "AProfile",
+ "HasV8_8aOps", "armv8.8-a", "+v8.8a",
+ [HasV8_7aOps, FeatureHBC, FeatureMOPS, FeatureNMI],
+ !listconcat(HasV8_7aOps.DefaultExts, [FeatureMOPS, FeatureHBC])>;
+def HasV8_9aOps : Architecture64<"ARMV8_9A",
+ 8, 9, "AProfile",
+ "HasV8_9aOps", "armv8.9-a", "+v8.9a",
[HasV8_8aOps, FeatureCLRBHB, FeaturePRFM_SLC, FeatureSPECRES2,
- FeatureCSSC, FeatureRASv2, FeatureCHK]>;
-
-def HasV9_0aOps : SubtargetFeature<
- "v9a", "HasV9_0aOps", "true", "Support ARM v9a instructions",
- [HasV8_5aOps, FeatureMEC, FeatureSVE2]>;
-
-def HasV9_1aOps : SubtargetFeature<
- "v9.1a", "HasV9_1aOps", "true", "Support ARM v9.1a instructions",
- [HasV8_6aOps, HasV9_0aOps]>;
-
-def HasV9_2aOps : SubtargetFeature<
- "v9.2a", "HasV9_2aOps", "true", "Support ARM v9.2a instructions",
- [HasV8_7aOps, HasV9_1aOps]>;
-
-def HasV9_3aOps : SubtargetFeature<
- "v9.3a", "HasV9_3aOps", "true", "Support ARM v9.3a instructions",
- [HasV8_8aOps, HasV9_2aOps]>;
-
-def HasV9_4aOps : SubtargetFeature<
- "v9.4a", "HasV9_4aOps", "true", "Support ARM v9.4a instructions",
- [HasV8_9aOps, HasV9_3aOps]>;
-
-def HasV9_5aOps : SubtargetFeature<
- "v9.5a", "HasV9_5aOps", "true", "Support ARM v9.5a instructions",
- [HasV9_4aOps, FeatureCPA]>;
-
-def HasV8_0rOps : SubtargetFeature<
- "v8r", "HasV8_0rOps", "true", "Support ARM v8r instructions",
+ FeatureCSSC, FeatureRASv2, FeatureCHK],
+ !listconcat(HasV8_8aOps.DefaultExts, [FeatureSPECRES2, FeatureCSSC, FeatureRASv2])>;
+def HasV9_0aOps : Architecture64<"ARMV9A",
+ 9, 0, "AProfile",
+ "HasV9_0aOps", "armv9-a", "+v9a",
+ [HasV8_5aOps, FeatureMEC, FeatureSVE2],
+ !listconcat(HasV8_5aOps.DefaultExts, [FeatureFullFP16, FeatureSVE, FeatureSVE2])>;
+def HasV9_1aOps : Architecture64<"ARMV9_1A",
+ 9, 1, "AProfile",
+ "HasV9_1aOps", "armv9.1-a", "+v9.1a",
+ [HasV8_6aOps, HasV9_0aOps],
+ !listconcat(HasV9_0aOps.DefaultExts, [FeatureBF16, FeatureMatMulInt8])>;
+def HasV9_2aOps : Architecture64<"ARMV9_2A",
+ 9, 2, "AProfile",
+ "HasV9_2aOps", "armv9.2-a", "+v9.2a",
+ [HasV8_7aOps, HasV9_1aOps],
+ !listconcat(HasV9_1aOps.DefaultExts, [])>;
+def HasV9_3aOps : Architecture64<"ARMV9_3A",
+ 9, 3, "AProfile",
+ "HasV9_3aOps", "armv9.3-a", "+v9.3a",
+ [HasV8_8aOps, HasV9_2aOps],
+ !listconcat(HasV9_2aOps.DefaultExts, [FeatureMOPS, FeatureHBC])>;
+def HasV9_4aOps : Architecture64<"ARMV9_4A",
+ 9, 4, "AProfile",
+ "HasV9_4aOps", "armv9.4-a", "+v9.4a",
+ [HasV8_9aOps, HasV9_3aOps],
+ !listconcat(HasV9_3aOps.DefaultExts, [FeatureSPECRES2, FeatureCSSC, FeatureRASv2])>;
+def HasV9_5aOps : Architecture64<"ARMV9_5A",
+ 9, 5, "AProfile",
+ "HasV9_5aOps", "armv9.5-a", "+v9.5a",
+ [HasV9_4aOps, FeatureCPA],
+ !listconcat(HasV9_4aOps.DefaultExts, [FeatureCPA])>;
+// For v8-R, we do not enable crypto and align with GCC that enables a more
+// minimal set of optional architecture extensions.
+def HasV8_0rOps : Architecture64<"ARMV8R",
+ 8, 0, "RProfile",
+ "HasV8ROps", "armv8-r", "+v8r",
[//v8.1
FeatureCRC, FeaturePAN, FeatureLSE, FeatureCONTEXTIDREL2,
//v8.2
@@ -875,7 +910,11 @@ def HasV8_0rOps : SubtargetFeature<
// Not mandatory in v8.0-R, but included here on the grounds that it
// only enables names of system registers
FeatureSpecRestrict
- ]>;
+ ],
+ !listconcat(
+ !listremove(HasV8_5aOps.DefaultExts, [FeatureLSE]), // why?
+ [FeatureSSBS, FeatureFullFP16, FeatureFP16FML, FeatureSB]
+ )>;
//===----------------------------------------------------------------------===//
// Access to privileged registers
diff --git a/llvm/utils/TableGen/ARMTargetDefEmitter.cpp b/llvm/utils/TableGen/ARMTargetDefEmitter.cpp
index 0e90f57af4938..4005d2f4c0620 100644
--- a/llvm/utils/TableGen/ARMTargetDefEmitter.cpp
+++ b/llvm/utils/TableGen/ARMTargetDefEmitter.cpp
@@ -112,6 +112,40 @@ static void EmitARMTargetDef(RecordKeeper &RK, raw_ostream &OS) {
<< "#undef EMIT_EXTENSIONS\n"
<< "#endif // EMIT_EXTENSIONS\n"
<< "\n";
+
+ // Emit architecture information
+ OS << "#ifdef EMIT_ARCHITECTURES\n";
+
+ for (const Record *Rec :
+ RK.getAllDerivedDefinitionsIfDefined("Architecture64")) {
+ OS << "inline constexpr ArchInfo " << Rec->getValueAsString("Spelling")
+ << " = {\n";
+ OS << " VersionTuple{" << Rec->getValueAsInt("Major") << ", "
+ << Rec->getValueAsInt("Minor") << "},\n";
+ OS << " " << Rec->getValueAsString("Profile") << ",\n";
+ OS << " \"" << Rec->getValueAsString("MArchName") << "\",\n";
+ OS << " \"" << Rec->getValueAsString("TargetFeatureName") << "\",\n";
+
+ // Construct the list of default extensions
+ OS << " AArch64::ExtensionBitset({";
+ for (auto *E : Rec->getValueAsListOfDefs("DefaultExts")) {
+ // Only process subclasses of Extension
+ OS << "AArch64::" << E->getValueAsString("ArchExtKindSpelling").upper()
+ << ", ";
+ }
+ OS << "})\n";
+
+ OS << "};\n";
+ }
+ OS << "// The set of all architectures\n"
+ << "static constexpr std::array<const ArchInfo *, 17> ArchInfos = {\n";
+ for (auto *Rec : RK.getAllDerivedDefinitionsIfDefined("Architecture64"))
+ OS << " &" << Rec->getValueAsString("Spelling") << ",\n";
+ OS << "};\n";
+
+ OS << "#undef EMIT_ARCHITECTURES\n"
+ << "#endif // EMIT_ARCHITECTURES\n"
+ << "\n";
}
static TableGen::Emitter::Opt
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