[llvm] [SystemZ] Simplify f128 atomic load/store (PR #90977)

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git-clang-format --diff 01e91a2dde497b71b0b85d5ec0f101a21e9c892c dba69e52692b57206bb3dab813791731a3042f34 -- llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
index cb1d7d5388..8c910386f9 100644
--- a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
@@ -6256,8 +6256,8 @@ static SDValue expandBitCastI128ToF128(SelectionDAG &DAG, SDValue Src,
     return DAG.getBitcast(MVT::f128, Src);
 
   // Otherwise, f128 must live in FP128, so do a partwise move.
-  assert(DAG.getTargetLoweringInfo().getRepRegClassFor(MVT::f128)
-         == &SystemZ::FP128BitRegClass);
+  assert(DAG.getTargetLoweringInfo().getRepRegClassFor(MVT::f128) ==
+         &SystemZ::FP128BitRegClass);
 
   SDValue Hi, Lo;
   std::tie(Lo, Hi) = DAG.SplitScalar(Src, SL, MVT::i64, MVT::i64);
@@ -6280,8 +6280,8 @@ static SDValue expandBitCastF128ToI128(SelectionDAG &DAG, SDValue Src,
     return DAG.getBitcast(MVT::i128, Src);
 
   // Otherwise, f128 must live in FP128, so do a partwise move.
-  assert(DAG.getTargetLoweringInfo().getRepRegClassFor(MVT::f128)
-         == &SystemZ::FP128BitRegClass);
+  assert(DAG.getTargetLoweringInfo().getRepRegClassFor(MVT::f128) ==
+         &SystemZ::FP128BitRegClass);
 
   SDValue LoFP =
       DAG.getTargetExtractSubreg(SystemZ::subreg_l64, SL, MVT::f64, Src);
@@ -6803,7 +6803,9 @@ SDValue SystemZTargetLowering::combineMERGE(
   return SDValue();
 }
 
-static bool isI128MovedToParts(LoadSDNode *LD, SmallVector<std::pair<SDNode *, int>, 2> &Users) {
+static bool
+isI128MovedToParts(LoadSDNode *LD,
+                   SmallVector<std::pair<SDNode *, int>, 2> &Users) {
   // Scan through all users.
   for (SDNode::use_iterator UI = LD->use_begin(), UIEnd = LD->use_end();
        UI != UIEnd; ++UI) {
@@ -6820,8 +6822,7 @@ static bool isI128MovedToParts(LoadSDNode *LD, SmallVector<std::pair<SDNode *, i
       User = *User->use_begin();
       Index = 0;
     }
-    if (User->getOpcode() != ISD::TRUNCATE ||
-        User->getValueType(0) != MVT::i64)
+    if (User->getOpcode() != ISD::TRUNCATE || User->getValueType(0) != MVT::i64)
       return false;
 
     Users.push_back(std::make_pair(User, Index));
@@ -6829,7 +6830,9 @@ static bool isI128MovedToParts(LoadSDNode *LD, SmallVector<std::pair<SDNode *, i
   return true;
 }
 
-static bool isF128MovedToParts(LoadSDNode *LD, SmallVector<std::pair<SDNode *, int>, 2> &Users) {
+static bool
+isF128MovedToParts(LoadSDNode *LD,
+                   SmallVector<std::pair<SDNode *, int>, 2> &Users) {
   // Scan through all users.
   for (SDNode::use_iterator UI = LD->use_begin(), UIEnd = LD->use_end();
        UI != UIEnd; ++UI) {
@@ -6845,9 +6848,14 @@ static bool isF128MovedToParts(LoadSDNode *LD, SmallVector<std::pair<SDNode *, i
 
     int Index;
     switch (User->getConstantOperandVal(1)) {
-      case SystemZ::subreg_l64: Index = 1; break;
-      case SystemZ::subreg_h64: Index = 0; break;
-      default: return false;
+    case SystemZ::subreg_l64:
+      Index = 1;
+      break;
+    case SystemZ::subreg_h64:
+      Index = 0;
+      break;
+    default:
+      return false;
     }
 
     Users.push_back(std::make_pair(User, Index));
@@ -6980,7 +6988,8 @@ static bool isOnlyUsedByStores(SDValue StoredVal, SelectionDAG &DAG) {
   return true;
 }
 
-static bool isI128MovedFromParts(SDValue Val, SDValue &LoPart, SDValue &HiPart) {
+static bool isI128MovedFromParts(SDValue Val, SDValue &LoPart,
+                                 SDValue &HiPart) {
   if (Val.getOpcode() != ISD::OR || !Val.getNode()->hasOneUse())
     return false;
 
@@ -7007,7 +7016,8 @@ static bool isI128MovedFromParts(SDValue Val, SDValue &LoPart, SDValue &HiPart)
   return true;
 }
 
-static bool isF128MovedFromParts(SDValue Val, SDValue &LoPart, SDValue &HiPart) {
+static bool isF128MovedFromParts(SDValue Val, SDValue &LoPart,
+                                 SDValue &HiPart) {
   if (!Val.getNode()->hasOneUse() || !Val.isMachineOpcode() ||
       Val.getMachineOpcode() != TargetOpcode::REG_SEQUENCE)
     return false;

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https://github.com/llvm/llvm-project/pull/90977