[llvm] [Exegesis][RISCV] Add RISCV support for llvm-exegesis (PR #89047)

[via llvm-commits]

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@@ -0,0 +1,412 @@
+//===-- Target.cpp ----------------------------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "../Target.h"
+
+#include "RISCVCounters.h"
+
+#include "MCTargetDesc/RISCVBaseInfo.h"
+#include "MCTargetDesc/RISCVMCTargetDesc.h"
+#include "MCTargetDesc/RISCVMatInt.h"
+#include "RISCVInstrInfo.h"
+
+// include computeAvailableFeatures and computeRequiredFeatures.
+#define GET_COMPUTE_FEATURES
+#define GET_AVAILABLE_OPCODE_CHECKER
+#include "RISCVGenInstrInfo.inc"
+#undef GET_COMPUTE_FEATURES
+#undef GET_AVAILABLE_OPCODE_CHECKER
+
+#include "llvm/CodeGen/MachineInstrBuilder.h"
+
+#include <vector>
+
+namespace llvm {
+namespace exegesis {
+
+namespace {
+
+static cl::OptionCategory
+    RISCVBenchmarkOptions("llvm-exegesis benchmark RISCV options");
+
+// TODO move perf counter data to td files (although it looks like an overkill
+// of sorts)
+
+static const char *RISCVPfmCounterNames[] = {
+    "CPU_CYCLES", // 0
+};
+
+static const PfmCountersInfo RISCVDefaultPfmCounters = {
+    RISCVPfmCounterNames[0], // Cycle counter
+    nullptr,                 // No uops counter.
+    nullptr,                 // No issue counters.
+    0};
+
+static const CpuAndPfmCounters RISCVCpuPfmCounters[] = {
+    {"", &RISCVDefaultPfmCounters},
+};
+
+class ExegesisRISCVTarget : public ExegesisTarget {
+public:
+  ExegesisRISCVTarget();
+
+  Expected<std::unique_ptr<pfm::CounterGroup>>
+  createCounter(StringRef CounterName, const LLVMState &State,
+                ArrayRef<const char *> ValidationCounters,
+                const pid_t ProcessID) const override;
+
+  bool checkOpcodeSupported(int Opcode,
+                            const MCSubtargetInfo &SI) const override;
+
+  unsigned findRegisterByName(const StringRef RegName) const override;
+
+  bool matchesArch(Triple::ArchType Arch) const override;
+
+  std::vector<MCInst> setRegTo(const MCSubtargetInfo &STI, unsigned Reg,
+                               const APInt &Value) const override;
+
+  unsigned getDefaultLoopCounterRegister(const Triple &) const override;
+
+  void decrementLoopCounterAndJump(MachineBasicBlock &MBB,
+                                   MachineBasicBlock &TargetMBB,
+                                   const MCInstrInfo &MII,
+                                   unsigned LoopRegister) const override;
+
+  unsigned getScratchMemoryRegister(const Triple &TT) const override;
+
+  void fillMemoryOperands(InstructionTemplate &IT, unsigned Reg,
+                          unsigned Offset) const override;
+
+  virtual std::vector<MCInst>
+  storeRegValueToScratch(const MCSubtargetInfo &STI, unsigned Reg,
+                         unsigned Offset) const override;
+  ArrayRef<unsigned> getUnavailableRegisters() const override;
+
+  Error randomizeTargetMCOperand(const Instruction &Instr, const Variable &Var,
+                                 MCOperand &AssignedValue,
+                                 const BitVector &ForbiddenRegs) const override;
+
+  void processInstructionReservedRegs(InstructionTemplate &IT) const override;
+
+  std::vector<InstructionTemplate>
+  generateInstructionVariants(const Instruction &Instr,
+                              unsigned MaxConfigsPerOpcode) const override;
+};
+
+ExegesisRISCVTarget::ExegesisRISCVTarget()
+    : ExegesisTarget(RISCVCpuPfmCounters, RISCV_MC::isOpcodeAvailable) {}
+
+Expected<std::unique_ptr<pfm::CounterGroup>> ExegesisRISCVTarget::createCounter(
+    StringRef CounterName, const LLVMState &State,
+    ArrayRef<const char *> ValidationCounters, const pid_t ProcessID) const {
+  if (CounterName == RISCVPfmCounterNames[0]) {
+    return createRISCVCpuCyclesCounter(pfm::PerfEvent(CounterName));
+  }
+  return make_error<Failure>(Twine("Unsupported performance counter '")
+                                 .concat(CounterName)
+                                 .concat("'"));
+}
+
+bool ExegesisRISCVTarget::checkOpcodeSupported(
+    int Opcode, const MCSubtargetInfo &SI) const {
+  auto Features = SI.getFeatureBits();
+  FeatureBitset AvailableFeatures =
+      RISCV_MC::computeAvailableFeatures(Features);
+  FeatureBitset RequiredFeatures = RISCV_MC::computeRequiredFeatures(Opcode);
+  FeatureBitset MissingFeatures =
+      (AvailableFeatures & RequiredFeatures) ^ RequiredFeatures;
+  return MissingFeatures.none();
+}
+
+#define GET_REGISTER_MATCHER
+#include "RISCVGenAsmMatcher.inc"
+
+unsigned
+ExegesisRISCVTarget::findRegisterByName(const StringRef RegName) const {
+  unsigned Reg;
+  if ((Reg = MatchRegisterName(RegName)))
+    return Reg;
+  if ((Reg = MatchRegisterAltName(RegName)))
+    return Reg;
+  return 0;
+}
+
+bool ExegesisRISCVTarget::matchesArch(Triple::ArchType Arch) const {
+  return Arch == Triple::riscv32 || Arch == Triple::riscv64;
+}
+
+// Stores constant value to a general-purpose (integer) register.
+static std::vector<MCInst> loadIntReg(const MCSubtargetInfo &STI, unsigned Reg,
+                                      const APInt &Value) {
+  RISCVMatInt::InstSeq InstSeq =
+      RISCVMatInt::generateInstSeq(Value.getSExtValue(), STI);
+  // First instruction has form 'Op DestReg, X0, Imm'
+  MCRegister SrcReg = RISCV::X0;
+  MCRegister DestReg = Reg;
+  std::vector<MCInst> MatIntInstrs;
+  MatIntInstrs.reserve(InstSeq.size());
+  for (const RISCVMatInt::Inst &Inst : InstSeq) {
+    if (Inst.getOpcode() == RISCV::LUI) {
----------------
AnastasiyaChernikova wrote:

Addressed

https://github.com/llvm/llvm-project/pull/89047