[llvm] 76508dc - [AMDGPU] Fix mode register pass for constrained FP operations (#90085)
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Fri May 3 10:47:19 PDT 2024
Author: Abhinav Garg
Date: 2024-05-03T19:47:15+02:00
New Revision: 76508dce4380e0cea2ecb396200a161f7dbefd0b
URL: https://github.com/llvm/llvm-project/commit/76508dce4380e0cea2ecb396200a161f7dbefd0b
DIFF: https://github.com/llvm/llvm-project/commit/76508dce4380e0cea2ecb396200a161f7dbefd0b.diff
LOG: [AMDGPU] Fix mode register pass for constrained FP operations (#90085)
This PR will fix the si-mode-register pass which is inserting an extra
setreg instruction in case of constrained FP operations. This pass will
be ignored for strictfp functions.
Added:
Modified:
llvm/lib/Target/AMDGPU/SIModeRegister.cpp
llvm/test/CodeGen/AMDGPU/mode-register-fpconstrain.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/SIModeRegister.cpp b/llvm/lib/Target/AMDGPU/SIModeRegister.cpp
index c01b1266a5530a..e7f448233ca347 100644
--- a/llvm/lib/Target/AMDGPU/SIModeRegister.cpp
+++ b/llvm/lib/Target/AMDGPU/SIModeRegister.cpp
@@ -430,6 +430,14 @@ void SIModeRegister::processBlockPhase3(MachineBasicBlock &MBB,
}
bool SIModeRegister::runOnMachineFunction(MachineFunction &MF) {
+ // Constrained FP intrinsics are used to support non-default rounding modes.
+ // strictfp attribute is required to mark functions with strict FP semantics
+ // having constrained FP intrinsics. This pass fixes up operations that uses
+ // a non-default rounding mode for non-strictfp functions. But it should not
+ // assume or modify any default rounding modes in case of strictfp functions.
+ const Function &F = MF.getFunction();
+ if (F.hasFnAttribute(llvm::Attribute::StrictFP))
+ return Changed;
BlockInfo.resize(MF.getNumBlockIDs());
const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
const SIInstrInfo *TII = ST.getInstrInfo();
diff --git a/llvm/test/CodeGen/AMDGPU/mode-register-fpconstrain.ll b/llvm/test/CodeGen/AMDGPU/mode-register-fpconstrain.ll
index 2403aeaa4428ad..8a29229c152fe8 100644
--- a/llvm/test/CodeGen/AMDGPU/mode-register-fpconstrain.ll
+++ b/llvm/test/CodeGen/AMDGPU/mode-register-fpconstrain.ll
@@ -9,8 +9,6 @@ define double @ignoreStrictfp(double noundef %a, double noundef %b) #0 {
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 1
-; GCN-NEXT: s_nop 1
-; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 1), 0
; GCN-NEXT: v_add_f64 v[0:1], v[0:1], v[2:3]
; GCN-NEXT: s_setpc_b64 s[30:31]
tail call void @llvm.amdgcn.s.setreg(i32 2177, i32 1)
@@ -24,8 +22,6 @@ define double @set_fpenv(double noundef %a, double noundef %b) #0 {
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 23), 4
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_TRAPSTS, 0, 5), 0
-; GCN-NEXT: s_nop 0
-; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 1), 0
; GCN-NEXT: v_add_f64 v[0:1], v[0:1], v[2:3]
; GCN-NEXT: s_setpc_b64 s[30:31]
entry:
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