[llvm] [X86] Use GFNI for vXi8 shifts/rotates (PR #89115)
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Fri May 3 10:09:03 PDT 2024
https://github.com/RKSimon updated https://github.com/llvm/llvm-project/pull/89115
>From 562b632993b68da58bad6abe301a825dd11eea0e Mon Sep 17 00:00:00 2001
From: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: Wed, 17 Apr 2024 19:11:36 +0100
Subject: [PATCH] [X86] Use GFNI for vXi8 shifts/rotates
As detailed here: https://github.com/InstLatx64/InstLatX64_Demo/blob/master/GFNI_Demo.h
We can use the gf2p8affine instruction to lower byte shifts/rotates as well as the existing bitreverse case.
There's a few other GFNI patterns we can probably handle - e.g. TZCNT/LZCNT were detailed on PR47394
Based off the original patch here: https://reviews.llvm.org/D137026
---
llvm/lib/Target/X86/X86ISelLowering.cpp | 53 +-
.../lib/Target/X86/X86TargetTransformInfo.cpp | 21 +
.../Analysis/CostModel/X86/fshl-codesize.ll | 12 +-
.../Analysis/CostModel/X86/fshl-latency.ll | 12 +-
.../CostModel/X86/fshl-sizelatency.ll | 12 +-
llvm/test/Analysis/CostModel/X86/fshl.ll | 2 +-
.../Analysis/CostModel/X86/fshr-codesize.ll | 12 +-
.../Analysis/CostModel/X86/fshr-latency.ll | 12 +-
.../CostModel/X86/fshr-sizelatency.ll | 12 +-
llvm/test/Analysis/CostModel/X86/fshr.ll | 2 +-
.../CostModel/X86/vshift-ashr-codesize.ll | 6 +-
.../CostModel/X86/vshift-ashr-latency.ll | 6 +-
.../CostModel/X86/vshift-ashr-sizelatency.ll | 6 +-
.../CostModel/X86/vshift-lshr-codesize.ll | 30 +-
.../CostModel/X86/vshift-lshr-latency.ll | 18 +-
.../CostModel/X86/vshift-lshr-sizelatency.ll | 18 +-
.../CostModel/X86/vshift-shl-codesize.ll | 30 +-
.../CostModel/X86/vshift-shl-latency.ll | 18 +-
.../CostModel/X86/vshift-shl-sizelatency.ll | 18 +-
llvm/test/CodeGen/X86/gfni-funnel-shifts.ll | 909 ++++------
llvm/test/CodeGen/X86/gfni-rotates.ll | 1490 +++++++----------
llvm/test/CodeGen/X86/gfni-shifts.ll | 823 +++------
.../CodeGen/X86/min-legal-vector-width.ll | 75 +-
23 files changed, 1474 insertions(+), 2123 deletions(-)
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index cf4a64ffded2e8..536c3233e13e88 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -29012,6 +29012,29 @@ SDValue X86TargetLowering::LowerWin64_INT128_TO_FP(SDValue Op,
return IsStrict ? DAG.getMergeValues({Result, Chain}, dl) : Result;
}
+// Generate a GFNI gf2p8affine bitmask for vXi8 bitreverse/shift/rotate.
+uint64_t getGFNICtrlImm(unsigned Opcode, unsigned Amt = 0) {
+ assert((Amt < 8) && "Shift/Rotation amount out of range");
+ switch (Opcode) {
+ case ISD::BITREVERSE:
+ return 0x8040201008040201ULL;
+ case ISD::SHL:
+ return ((0x0102040810204080ULL >> (Amt)) &
+ (0x0101010101010101ULL * (0xFF >> (Amt))));
+ case ISD::SRL:
+ return ((0x0102040810204080ULL << (Amt)) &
+ (0x0101010101010101ULL * ((0xFF << (Amt)) & 0xFF)));
+ case ISD::SRA:
+ return (getGFNICtrlImm(ISD::SRL, Amt) |
+ (0x8080808080808080ULL >> (64 - (8 * Amt))));
+ case ISD::ROTL:
+ return getGFNICtrlImm(ISD::SRL, 8 - Amt) | getGFNICtrlImm(ISD::SHL, Amt);
+ case ISD::ROTR:
+ return getGFNICtrlImm(ISD::SHL, 8 - Amt) | getGFNICtrlImm(ISD::SRL, Amt);
+ }
+ llvm_unreachable("Unsupported GFNI opcode");
+}
+
// Return true if the required (according to Opcode) shift-imm form is natively
// supported by the Subtarget
static bool supportedVectorShiftWithImm(EVT VT, const X86Subtarget &Subtarget,
@@ -29199,6 +29222,14 @@ static SDValue LowerShiftByScalarImmediate(SDValue Op, SelectionDAG &DAG,
if (VT == MVT::v16i8 && Subtarget.hasXOP())
return SDValue();
+ if (Subtarget.hasGFNI()) {
+ uint64_t ShiftMask = getGFNICtrlImm(Op.getOpcode(), ShiftAmt);
+ MVT MaskVT = MVT::getVectorVT(MVT::i64, NumElts / 8);
+ SDValue Mask = DAG.getBitcast(VT, DAG.getConstant(ShiftMask, dl, MaskVT));
+ return DAG.getNode(X86ISD::GF2P8AFFINEQB, dl, VT, R, Mask,
+ DAG.getTargetConstant(0, dl, MVT::i8));
+ }
+
if (Op.getOpcode() == ISD::SHL) {
// Make a large shift.
SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, ShiftVT, R,
@@ -29882,13 +29913,15 @@ static SDValue LowerFunnelShift(SDValue Op, const X86Subtarget &Subtarget,
uint64_t ShXAmt = IsFSHR ? (EltSizeInBits - ShiftAmt) : ShiftAmt;
uint64_t ShYAmt = IsFSHR ? ShiftAmt : (EltSizeInBits - ShiftAmt);
assert((ShXAmt + ShYAmt) == EltSizeInBits && "Illegal funnel shift");
+ MVT WideVT = MVT::getVectorVT(MVT::i16, NumElts / 2);
- if (EltSizeInBits == 8 && ShXAmt > 1 &&
- (Subtarget.hasXOP() || useVPTERNLOG(Subtarget, VT))) {
+ if (EltSizeInBits == 8 &&
+ (Subtarget.hasXOP() ||
+ (useVPTERNLOG(Subtarget, VT) &&
+ supportedVectorShiftWithImm(WideVT, Subtarget, ISD::SHL)))) {
// For vXi8 cases on Subtargets that can perform VPCMOV/VPTERNLOG
// bit-select - lower using vXi16 shifts and then perform the bitmask at
// the original vector width to handle cases where we split.
- MVT WideVT = MVT::getVectorVT(MVT::i16, NumElts / 2);
APInt MaskX = APInt::getHighBitsSet(8, 8 - ShXAmt);
APInt MaskY = APInt::getLowBitsSet(8, 8 - ShYAmt);
SDValue ShX =
@@ -30091,6 +30124,17 @@ static SDValue LowerRotate(SDValue Op, const X86Subtarget &Subtarget,
DAG.getNode(ISD::SUB, DL, VT, Z, Amt));
}
+ // Attempt to use GFNI gf2p8affine to rotate vXi8 by an uniform constant.
+ if (IsCstSplat && Subtarget.hasGFNI() && VT.getScalarType() == MVT::i8 &&
+ DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
+ uint64_t RotAmt = CstSplatValue.urem(EltSizeInBits);
+ uint64_t RotMask = getGFNICtrlImm(Opcode, RotAmt);
+ MVT MaskVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
+ SDValue Mask = DAG.getBitcast(VT, DAG.getConstant(RotMask, DL, MaskVT));
+ return DAG.getNode(X86ISD::GF2P8AFFINEQB, DL, VT, R, Mask,
+ DAG.getTargetConstant(0, DL, MVT::i8));
+ }
+
// Split 256-bit integers on XOP/pre-AVX2 targets.
if (VT.is256BitVector() && (Subtarget.hasXOP() || !Subtarget.hasAVX2()))
return splitVectorIntBinary(Op, DAG, DL);
@@ -31414,7 +31458,8 @@ static SDValue LowerBITREVERSE(SDValue Op, const X86Subtarget &Subtarget,
// If we have GFNI, we can use GF2P8AFFINEQB to reverse the bits.
if (Subtarget.hasGFNI()) {
MVT MatrixVT = MVT::getVectorVT(MVT::i64, NumElts / 8);
- SDValue Matrix = DAG.getConstant(0x8040201008040201ULL, DL, MatrixVT);
+ SDValue Matrix =
+ DAG.getConstant(getGFNICtrlImm(ISD::BITREVERSE), DL, MatrixVT);
Matrix = DAG.getBitcast(VT, Matrix);
return DAG.getNode(X86ISD::GF2P8AFFINEQB, DL, VT, In, Matrix,
DAG.getTargetConstant(0, DL, MVT::i8));
diff --git a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
index cb07c2a4b56a5c..2257370912bd9a 100644
--- a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
+++ b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
@@ -345,6 +345,24 @@ InstructionCost X86TTIImpl::getArithmeticInstrCost(
Op1Info.getNoProps(), Op2Info.getNoProps());
}
+ static const CostKindTblEntry GFNIUniformConstCostTable[] = {
+ { ISD::SHL, MVT::v16i8, { 1, 6, 1, 2 } }, // gf2p8affineqb
+ { ISD::SRL, MVT::v16i8, { 1, 6, 1, 2 } }, // gf2p8affineqb
+ { ISD::SRA, MVT::v16i8, { 1, 6, 1, 2 } }, // gf2p8affineqb
+ { ISD::SHL, MVT::v32i8, { 1, 6, 1, 2 } }, // gf2p8affineqb
+ { ISD::SRL, MVT::v32i8, { 1, 6, 1, 2 } }, // gf2p8affineqb
+ { ISD::SRA, MVT::v32i8, { 1, 6, 1, 2 } }, // gf2p8affineqb
+ { ISD::SHL, MVT::v64i8, { 1, 6, 1, 2 } }, // gf2p8affineqb
+ { ISD::SRL, MVT::v64i8, { 1, 6, 1, 2 } }, // gf2p8affineqb
+ { ISD::SRA, MVT::v64i8, { 1, 6, 1, 2 } }, // gf2p8affineqb
+ };
+
+ if (Op2Info.isUniform() && Op2Info.isConstant() && ST->hasGFNI())
+ if (const auto *Entry =
+ CostTableLookup(GFNIUniformConstCostTable, ISD, LT.second))
+ if (auto KindCost = Entry->Cost[CostKind])
+ return LT.first * *KindCost;
+
static const CostKindTblEntry AVX512BWUniformConstCostTable[] = {
{ ISD::SHL, MVT::v16i8, { 1, 7, 2, 3 } }, // psllw + pand.
{ ISD::SRL, MVT::v16i8, { 1, 7, 2, 3 } }, // psrlw + pand.
@@ -3869,6 +3887,9 @@ X86TTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
{ ISD::BITREVERSE, MVT::v2i64, { 1, 8, 2, 4 } }, // gf2p8affineqb
{ ISD::BITREVERSE, MVT::v4i64, { 1, 9, 2, 4 } }, // gf2p8affineqb
{ ISD::BITREVERSE, MVT::v8i64, { 1, 9, 2, 4 } }, // gf2p8affineqb
+ { X86ISD::VROTLI, MVT::v16i8, { 1, 6, 1, 2 } }, // gf2p8affineqb
+ { X86ISD::VROTLI, MVT::v32i8, { 1, 6, 1, 2 } }, // gf2p8affineqb
+ { X86ISD::VROTLI, MVT::v64i8, { 1, 6, 1, 2 } }, // gf2p8affineqb
};
static const CostKindTblEntry GLMCostTbl[] = {
{ ISD::FSQRT, MVT::f32, { 19, 20, 1, 1 } }, // sqrtss
diff --git a/llvm/test/Analysis/CostModel/X86/fshl-codesize.ll b/llvm/test/Analysis/CostModel/X86/fshl-codesize.ll
index a7585a4d9f39e1..71927002b599fd 100644
--- a/llvm/test/Analysis/CostModel/X86/fshl-codesize.ll
+++ b/llvm/test/Analysis/CostModel/X86/fshl-codesize.ll
@@ -1597,9 +1597,9 @@ define void @splatconstant_funnel_i8(i8 %a8, <16 x i8> %a128, <32 x i8> %a256, <
;
; AVX512GFNI-LABEL: 'splatconstant_funnel_i8'
; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %I8 = call i8 @llvm.fshl.i8(i8 %a8, i8 %b8, i8 3)
-; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16I8 = call <16 x i8> @llvm.fshl.v16i8(<16 x i8> %a128, <16 x i8> %b128, <16 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)
-; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V32I8 = call <32 x i8> @llvm.fshl.v32i8(<32 x i8> %a256, <32 x i8> %b256, <32 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)
-; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V64I8 = call <64 x i8> @llvm.fshl.v64i8(<64 x i8> %a512, <64 x i8> %b512, <64 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)
+; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16I8 = call <16 x i8> @llvm.fshl.v16i8(<16 x i8> %a128, <16 x i8> %b128, <16 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)
+; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V32I8 = call <32 x i8> @llvm.fshl.v32i8(<32 x i8> %a256, <32 x i8> %b256, <32 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)
+; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V64I8 = call <64 x i8> @llvm.fshl.v64i8(<64 x i8> %a512, <64 x i8> %b512, <64 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)
; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
;
%I8 = call i8 @llvm.fshl.i8(i8 %a8, i8 %b8, i8 3)
@@ -2871,9 +2871,9 @@ define void @splatconstant_rotate_i8(i8 %a8, <16 x i8> %a128, <32 x i8> %a256, <
;
; AVX512GFNI-LABEL: 'splatconstant_rotate_i8'
; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I8 = call i8 @llvm.fshl.i8(i8 %a8, i8 %a8, i8 3)
-; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V16I8 = call <16 x i8> @llvm.fshl.v16i8(<16 x i8> %a128, <16 x i8> %a128, <16 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)
-; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V32I8 = call <32 x i8> @llvm.fshl.v32i8(<32 x i8> %a256, <32 x i8> %a256, <32 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)
-; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V64I8 = call <64 x i8> @llvm.fshl.v64i8(<64 x i8> %a512, <64 x i8> %a512, <64 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)
+; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I8 = call <16 x i8> @llvm.fshl.v16i8(<16 x i8> %a128, <16 x i8> %a128, <16 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)
+; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V32I8 = call <32 x i8> @llvm.fshl.v32i8(<32 x i8> %a256, <32 x i8> %a256, <32 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)
+; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V64I8 = call <64 x i8> @llvm.fshl.v64i8(<64 x i8> %a512, <64 x i8> %a512, <64 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)
; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
;
%I8 = call i8 @llvm.fshl.i8(i8 %a8, i8 %a8, i8 3)
diff --git a/llvm/test/Analysis/CostModel/X86/fshl-latency.ll b/llvm/test/Analysis/CostModel/X86/fshl-latency.ll
index 7105f713fdc349..c40394ba9a7283 100644
--- a/llvm/test/Analysis/CostModel/X86/fshl-latency.ll
+++ b/llvm/test/Analysis/CostModel/X86/fshl-latency.ll
@@ -1549,9 +1549,9 @@ define void @splatconstant_funnel_i8(i8 %a8, <16 x i8> %a128, <32 x i8> %a256, <
;
; AVX512GFNI-LABEL: 'splatconstant_funnel_i8'
; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %I8 = call i8 @llvm.fshl.i8(i8 %a8, i8 %b8, i8 3)
-; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %V16I8 = call <16 x i8> @llvm.fshl.v16i8(<16 x i8> %a128, <16 x i8> %b128, <16 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)
-; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V32I8 = call <32 x i8> @llvm.fshl.v32i8(<32 x i8> %a256, <32 x i8> %b256, <32 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)
-; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V64I8 = call <64 x i8> @llvm.fshl.v64i8(<64 x i8> %a512, <64 x i8> %b512, <64 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)
+; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V16I8 = call <16 x i8> @llvm.fshl.v16i8(<16 x i8> %a128, <16 x i8> %b128, <16 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)
+; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V32I8 = call <32 x i8> @llvm.fshl.v32i8(<32 x i8> %a256, <32 x i8> %b256, <32 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)
+; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V64I8 = call <64 x i8> @llvm.fshl.v64i8(<64 x i8> %a512, <64 x i8> %b512, <64 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)
; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
;
%I8 = call i8 @llvm.fshl.i8(i8 %a8, i8 %b8, i8 3)
@@ -2823,9 +2823,9 @@ define void @splatconstant_rotate_i8(i8 %a8, <16 x i8> %a128, <32 x i8> %a256, <
;
; AVX512GFNI-LABEL: 'splatconstant_rotate_i8'
; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I8 = call i8 @llvm.fshl.i8(i8 %a8, i8 %a8, i8 3)
-; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16I8 = call <16 x i8> @llvm.fshl.v16i8(<16 x i8> %a128, <16 x i8> %a128, <16 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)
-; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V32I8 = call <32 x i8> @llvm.fshl.v32i8(<32 x i8> %a256, <32 x i8> %a256, <32 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)
-; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V64I8 = call <64 x i8> @llvm.fshl.v64i8(<64 x i8> %a512, <64 x i8> %a512, <64 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)
+; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16I8 = call <16 x i8> @llvm.fshl.v16i8(<16 x i8> %a128, <16 x i8> %a128, <16 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)
+; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V32I8 = call <32 x i8> @llvm.fshl.v32i8(<32 x i8> %a256, <32 x i8> %a256, <32 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)
+; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V64I8 = call <64 x i8> @llvm.fshl.v64i8(<64 x i8> %a512, <64 x i8> %a512, <64 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)
; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
;
%I8 = call i8 @llvm.fshl.i8(i8 %a8, i8 %a8, i8 3)
diff --git a/llvm/test/Analysis/CostModel/X86/fshl-sizelatency.ll b/llvm/test/Analysis/CostModel/X86/fshl-sizelatency.ll
index 5d7361e2931769..7b0daf50485505 100644
--- a/llvm/test/Analysis/CostModel/X86/fshl-sizelatency.ll
+++ b/llvm/test/Analysis/CostModel/X86/fshl-sizelatency.ll
@@ -1597,9 +1597,9 @@ define void @splatconstant_funnel_i8(i8 %a8, <16 x i8> %a128, <32 x i8> %a256, <
;
; AVX512GFNI-LABEL: 'splatconstant_funnel_i8'
; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %I8 = call i8 @llvm.fshl.i8(i8 %a8, i8 %b8, i8 3)
-; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V16I8 = call <16 x i8> @llvm.fshl.v16i8(<16 x i8> %a128, <16 x i8> %b128, <16 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)
-; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32I8 = call <32 x i8> @llvm.fshl.v32i8(<32 x i8> %a256, <32 x i8> %b256, <32 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)
-; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V64I8 = call <64 x i8> @llvm.fshl.v64i8(<64 x i8> %a512, <64 x i8> %b512, <64 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)
+; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16I8 = call <16 x i8> @llvm.fshl.v16i8(<16 x i8> %a128, <16 x i8> %b128, <16 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)
+; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V32I8 = call <32 x i8> @llvm.fshl.v32i8(<32 x i8> %a256, <32 x i8> %b256, <32 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)
+; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V64I8 = call <64 x i8> @llvm.fshl.v64i8(<64 x i8> %a512, <64 x i8> %b512, <64 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)
; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
;
%I8 = call i8 @llvm.fshl.i8(i8 %a8, i8 %b8, i8 3)
@@ -3111,9 +3111,9 @@ define void @splatconstant_rotate_i8(i8 %a8, <16 x i8> %a128, <32 x i8> %a256, <
;
; AVX512GFNI-LABEL: 'splatconstant_rotate_i8'
; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I8 = call i8 @llvm.fshl.i8(i8 %a8, i8 %a8, i8 3)
-; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16I8 = call <16 x i8> @llvm.fshl.v16i8(<16 x i8> %a128, <16 x i8> %a128, <16 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)
-; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V32I8 = call <32 x i8> @llvm.fshl.v32i8(<32 x i8> %a256, <32 x i8> %a256, <32 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)
-; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V64I8 = call <64 x i8> @llvm.fshl.v64i8(<64 x i8> %a512, <64 x i8> %a512, <64 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)
+; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16I8 = call <16 x i8> @llvm.fshl.v16i8(<16 x i8> %a128, <16 x i8> %a128, <16 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)
+; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V32I8 = call <32 x i8> @llvm.fshl.v32i8(<32 x i8> %a256, <32 x i8> %a256, <32 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)
+; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V64I8 = call <64 x i8> @llvm.fshl.v64i8(<64 x i8> %a512, <64 x i8> %a512, <64 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)
; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
;
%I8 = call i8 @llvm.fshl.i8(i8 %a8, i8 %a8, i8 3)
diff --git a/llvm/test/Analysis/CostModel/X86/fshl.ll b/llvm/test/Analysis/CostModel/X86/fshl.ll
index 1cbdab09acd909..127dec0a1a6f78 100644
--- a/llvm/test/Analysis/CostModel/X86/fshl.ll
+++ b/llvm/test/Analysis/CostModel/X86/fshl.ll
@@ -2811,7 +2811,7 @@ define void @splatconstant_rotate_i8(i8 %a8, <16 x i8> %a128, <32 x i8> %a256, <
; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I8 = call i8 @llvm.fshl.i8(i8 %a8, i8 %a8, i8 3)
; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I8 = call <16 x i8> @llvm.fshl.v16i8(<16 x i8> %a128, <16 x i8> %a128, <16 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)
; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V32I8 = call <32 x i8> @llvm.fshl.v32i8(<32 x i8> %a256, <32 x i8> %a256, <32 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)
-; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V64I8 = call <64 x i8> @llvm.fshl.v64i8(<64 x i8> %a512, <64 x i8> %a512, <64 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)
+; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V64I8 = call <64 x i8> @llvm.fshl.v64i8(<64 x i8> %a512, <64 x i8> %a512, <64 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)
; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
;
%I8 = call i8 @llvm.fshl.i8(i8 %a8, i8 %a8, i8 3)
diff --git a/llvm/test/Analysis/CostModel/X86/fshr-codesize.ll b/llvm/test/Analysis/CostModel/X86/fshr-codesize.ll
index ecc861dd7f8eed..92a20b938142a7 100644
--- a/llvm/test/Analysis/CostModel/X86/fshr-codesize.ll
+++ b/llvm/test/Analysis/CostModel/X86/fshr-codesize.ll
@@ -1597,9 +1597,9 @@ define void @splatconstant_funnel_i8(i8 %a8, <16 x i8> %a128, <32 x i8> %a256, <
;
; AVX512GFNI-LABEL: 'splatconstant_funnel_i8'
; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %I8 = call i8 @llvm.fshr.i8(i8 %a8, i8 %b8, i8 3)
-; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16I8 = call <16 x i8> @llvm.fshr.v16i8(<16 x i8> %a128, <16 x i8> %b128, <16 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)
-; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V32I8 = call <32 x i8> @llvm.fshr.v32i8(<32 x i8> %a256, <32 x i8> %b256, <32 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)
-; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V64I8 = call <64 x i8> @llvm.fshr.v64i8(<64 x i8> %a512, <64 x i8> %b512, <64 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)
+; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16I8 = call <16 x i8> @llvm.fshr.v16i8(<16 x i8> %a128, <16 x i8> %b128, <16 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)
+; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V32I8 = call <32 x i8> @llvm.fshr.v32i8(<32 x i8> %a256, <32 x i8> %b256, <32 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)
+; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V64I8 = call <64 x i8> @llvm.fshr.v64i8(<64 x i8> %a512, <64 x i8> %b512, <64 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)
; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
;
%I8 = call i8 @llvm.fshr.i8(i8 %a8, i8 %b8, i8 3)
@@ -2871,9 +2871,9 @@ define void @splatconstant_rotate_i8(i8 %a8, <16 x i8> %a128, <32 x i8> %a256, <
;
; AVX512GFNI-LABEL: 'splatconstant_rotate_i8'
; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I8 = call i8 @llvm.fshr.i8(i8 %a8, i8 %a8, i8 3)
-; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V16I8 = call <16 x i8> @llvm.fshr.v16i8(<16 x i8> %a128, <16 x i8> %a128, <16 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)
-; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V32I8 = call <32 x i8> @llvm.fshr.v32i8(<32 x i8> %a256, <32 x i8> %a256, <32 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)
-; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V64I8 = call <64 x i8> @llvm.fshr.v64i8(<64 x i8> %a512, <64 x i8> %a512, <64 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)
+; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I8 = call <16 x i8> @llvm.fshr.v16i8(<16 x i8> %a128, <16 x i8> %a128, <16 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)
+; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V32I8 = call <32 x i8> @llvm.fshr.v32i8(<32 x i8> %a256, <32 x i8> %a256, <32 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)
+; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V64I8 = call <64 x i8> @llvm.fshr.v64i8(<64 x i8> %a512, <64 x i8> %a512, <64 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)
; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
;
%I8 = call i8 @llvm.fshr.i8(i8 %a8, i8 %a8, i8 3)
diff --git a/llvm/test/Analysis/CostModel/X86/fshr-latency.ll b/llvm/test/Analysis/CostModel/X86/fshr-latency.ll
index 0142ad77849cac..33fadef536bf74 100644
--- a/llvm/test/Analysis/CostModel/X86/fshr-latency.ll
+++ b/llvm/test/Analysis/CostModel/X86/fshr-latency.ll
@@ -1549,9 +1549,9 @@ define void @splatconstant_funnel_i8(i8 %a8, <16 x i8> %a128, <32 x i8> %a256, <
;
; AVX512GFNI-LABEL: 'splatconstant_funnel_i8'
; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %I8 = call i8 @llvm.fshr.i8(i8 %a8, i8 %b8, i8 3)
-; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %V16I8 = call <16 x i8> @llvm.fshr.v16i8(<16 x i8> %a128, <16 x i8> %b128, <16 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)
-; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V32I8 = call <32 x i8> @llvm.fshr.v32i8(<32 x i8> %a256, <32 x i8> %b256, <32 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)
-; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V64I8 = call <64 x i8> @llvm.fshr.v64i8(<64 x i8> %a512, <64 x i8> %b512, <64 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)
+; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V16I8 = call <16 x i8> @llvm.fshr.v16i8(<16 x i8> %a128, <16 x i8> %b128, <16 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)
+; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V32I8 = call <32 x i8> @llvm.fshr.v32i8(<32 x i8> %a256, <32 x i8> %b256, <32 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)
+; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V64I8 = call <64 x i8> @llvm.fshr.v64i8(<64 x i8> %a512, <64 x i8> %b512, <64 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)
; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
;
%I8 = call i8 @llvm.fshr.i8(i8 %a8, i8 %b8, i8 3)
@@ -2823,9 +2823,9 @@ define void @splatconstant_rotate_i8(i8 %a8, <16 x i8> %a128, <32 x i8> %a256, <
;
; AVX512GFNI-LABEL: 'splatconstant_rotate_i8'
; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I8 = call i8 @llvm.fshr.i8(i8 %a8, i8 %a8, i8 3)
-; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16I8 = call <16 x i8> @llvm.fshr.v16i8(<16 x i8> %a128, <16 x i8> %a128, <16 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)
-; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V32I8 = call <32 x i8> @llvm.fshr.v32i8(<32 x i8> %a256, <32 x i8> %a256, <32 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)
-; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V64I8 = call <64 x i8> @llvm.fshr.v64i8(<64 x i8> %a512, <64 x i8> %a512, <64 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)
+; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16I8 = call <16 x i8> @llvm.fshr.v16i8(<16 x i8> %a128, <16 x i8> %a128, <16 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)
+; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V32I8 = call <32 x i8> @llvm.fshr.v32i8(<32 x i8> %a256, <32 x i8> %a256, <32 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)
+; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V64I8 = call <64 x i8> @llvm.fshr.v64i8(<64 x i8> %a512, <64 x i8> %a512, <64 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)
; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
;
%I8 = call i8 @llvm.fshr.i8(i8 %a8, i8 %a8, i8 3)
diff --git a/llvm/test/Analysis/CostModel/X86/fshr-sizelatency.ll b/llvm/test/Analysis/CostModel/X86/fshr-sizelatency.ll
index 6dafb20a0aeed0..ef831328c480e7 100644
--- a/llvm/test/Analysis/CostModel/X86/fshr-sizelatency.ll
+++ b/llvm/test/Analysis/CostModel/X86/fshr-sizelatency.ll
@@ -1597,9 +1597,9 @@ define void @splatconstant_funnel_i8(i8 %a8, <16 x i8> %a128, <32 x i8> %a256, <
;
; AVX512GFNI-LABEL: 'splatconstant_funnel_i8'
; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %I8 = call i8 @llvm.fshr.i8(i8 %a8, i8 %b8, i8 3)
-; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V16I8 = call <16 x i8> @llvm.fshr.v16i8(<16 x i8> %a128, <16 x i8> %b128, <16 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)
-; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32I8 = call <32 x i8> @llvm.fshr.v32i8(<32 x i8> %a256, <32 x i8> %b256, <32 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)
-; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V64I8 = call <64 x i8> @llvm.fshr.v64i8(<64 x i8> %a512, <64 x i8> %b512, <64 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)
+; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16I8 = call <16 x i8> @llvm.fshr.v16i8(<16 x i8> %a128, <16 x i8> %b128, <16 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)
+; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V32I8 = call <32 x i8> @llvm.fshr.v32i8(<32 x i8> %a256, <32 x i8> %b256, <32 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)
+; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V64I8 = call <64 x i8> @llvm.fshr.v64i8(<64 x i8> %a512, <64 x i8> %b512, <64 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)
; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
;
%I8 = call i8 @llvm.fshr.i8(i8 %a8, i8 %b8, i8 3)
@@ -3111,9 +3111,9 @@ define void @splatconstant_rotate_i8(i8 %a8, <16 x i8> %a128, <32 x i8> %a256, <
;
; AVX512GFNI-LABEL: 'splatconstant_rotate_i8'
; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I8 = call i8 @llvm.fshr.i8(i8 %a8, i8 %a8, i8 3)
-; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16I8 = call <16 x i8> @llvm.fshr.v16i8(<16 x i8> %a128, <16 x i8> %a128, <16 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)
-; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V32I8 = call <32 x i8> @llvm.fshr.v32i8(<32 x i8> %a256, <32 x i8> %a256, <32 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)
-; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V64I8 = call <64 x i8> @llvm.fshr.v64i8(<64 x i8> %a512, <64 x i8> %a512, <64 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)
+; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16I8 = call <16 x i8> @llvm.fshr.v16i8(<16 x i8> %a128, <16 x i8> %a128, <16 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)
+; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V32I8 = call <32 x i8> @llvm.fshr.v32i8(<32 x i8> %a256, <32 x i8> %a256, <32 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)
+; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V64I8 = call <64 x i8> @llvm.fshr.v64i8(<64 x i8> %a512, <64 x i8> %a512, <64 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)
; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
;
%I8 = call i8 @llvm.fshr.i8(i8 %a8, i8 %a8, i8 3)
diff --git a/llvm/test/Analysis/CostModel/X86/fshr.ll b/llvm/test/Analysis/CostModel/X86/fshr.ll
index ada1b9c5bdc4bf..3c233b51053ddc 100644
--- a/llvm/test/Analysis/CostModel/X86/fshr.ll
+++ b/llvm/test/Analysis/CostModel/X86/fshr.ll
@@ -2811,7 +2811,7 @@ define void @splatconstant_rotate_i8(i8 %a8, <16 x i8> %a128, <32 x i8> %a256, <
; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I8 = call i8 @llvm.fshr.i8(i8 %a8, i8 %a8, i8 3)
; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I8 = call <16 x i8> @llvm.fshr.v16i8(<16 x i8> %a128, <16 x i8> %a128, <16 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)
; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V32I8 = call <32 x i8> @llvm.fshr.v32i8(<32 x i8> %a256, <32 x i8> %a256, <32 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)
-; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V64I8 = call <64 x i8> @llvm.fshr.v64i8(<64 x i8> %a512, <64 x i8> %a512, <64 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)
+; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V64I8 = call <64 x i8> @llvm.fshr.v64i8(<64 x i8> %a512, <64 x i8> %a512, <64 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)
; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
;
%I8 = call i8 @llvm.fshr.i8(i8 %a8, i8 %a8, i8 3)
diff --git a/llvm/test/Analysis/CostModel/X86/vshift-ashr-codesize.ll b/llvm/test/Analysis/CostModel/X86/vshift-ashr-codesize.ll
index a3c24bdd1a8820..9ff975665f13b6 100644
--- a/llvm/test/Analysis/CostModel/X86/vshift-ashr-codesize.ll
+++ b/llvm/test/Analysis/CostModel/X86/vshift-ashr-codesize.ll
@@ -1676,7 +1676,7 @@ define <16 x i8> @splatconstant_shift_v16i8(<16 x i8> %a) {
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x i8> %shift
;
; AVX512GFNI-LABEL: 'splatconstant_shift_v16i8'
-; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %shift = ashr <16 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %shift = ashr <16 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x i8> %shift
;
%shift = ashr <16 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
@@ -1713,7 +1713,7 @@ define <32 x i8> @splatconstant_shift_v32i8(<32 x i8> %a) {
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <32 x i8> %shift
;
; AVX512GFNI-LABEL: 'splatconstant_shift_v32i8'
-; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %shift = ashr <32 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %shift = ashr <32 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <32 x i8> %shift
;
%shift = ashr <32 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
@@ -1750,7 +1750,7 @@ define <64 x i8> @splatconstant_shift_v64i8(<64 x i8> %a) {
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <64 x i8> %shift
;
; AVX512GFNI-LABEL: 'splatconstant_shift_v64i8'
-; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %shift = ashr <64 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %shift = ashr <64 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <64 x i8> %shift
;
%shift = ashr <64 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
diff --git a/llvm/test/Analysis/CostModel/X86/vshift-ashr-latency.ll b/llvm/test/Analysis/CostModel/X86/vshift-ashr-latency.ll
index cd4189d4a7f84d..ab300779b4341c 100644
--- a/llvm/test/Analysis/CostModel/X86/vshift-ashr-latency.ll
+++ b/llvm/test/Analysis/CostModel/X86/vshift-ashr-latency.ll
@@ -1806,7 +1806,7 @@ define <16 x i8> @splatconstant_shift_v16i8(<16 x i8> %a) {
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x i8> %shift
;
; AVX512GFNI-LABEL: 'splatconstant_shift_v16i8'
-; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %shift = ashr <16 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %shift = ashr <16 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x i8> %shift
;
%shift = ashr <16 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
@@ -1847,7 +1847,7 @@ define <32 x i8> @splatconstant_shift_v32i8(<32 x i8> %a) {
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <32 x i8> %shift
;
; AVX512GFNI-LABEL: 'splatconstant_shift_v32i8'
-; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %shift = ashr <32 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %shift = ashr <32 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <32 x i8> %shift
;
%shift = ashr <32 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
@@ -1888,7 +1888,7 @@ define <64 x i8> @splatconstant_shift_v64i8(<64 x i8> %a) {
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <64 x i8> %shift
;
; AVX512GFNI-LABEL: 'splatconstant_shift_v64i8'
-; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %shift = ashr <64 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %shift = ashr <64 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <64 x i8> %shift
;
%shift = ashr <64 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
diff --git a/llvm/test/Analysis/CostModel/X86/vshift-ashr-sizelatency.ll b/llvm/test/Analysis/CostModel/X86/vshift-ashr-sizelatency.ll
index 84ccad0294155f..1b51a2e0a1e6e5 100644
--- a/llvm/test/Analysis/CostModel/X86/vshift-ashr-sizelatency.ll
+++ b/llvm/test/Analysis/CostModel/X86/vshift-ashr-sizelatency.ll
@@ -1700,7 +1700,7 @@ define <16 x i8> @splatconstant_shift_v16i8(<16 x i8> %a) {
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x i8> %shift
;
; AVX512GFNI-LABEL: 'splatconstant_shift_v16i8'
-; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %shift = ashr <16 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %shift = ashr <16 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x i8> %shift
;
%shift = ashr <16 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
@@ -1741,7 +1741,7 @@ define <32 x i8> @splatconstant_shift_v32i8(<32 x i8> %a) {
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <32 x i8> %shift
;
; AVX512GFNI-LABEL: 'splatconstant_shift_v32i8'
-; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %shift = ashr <32 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %shift = ashr <32 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <32 x i8> %shift
;
%shift = ashr <32 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
@@ -1782,7 +1782,7 @@ define <64 x i8> @splatconstant_shift_v64i8(<64 x i8> %a) {
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <64 x i8> %shift
;
; AVX512GFNI-LABEL: 'splatconstant_shift_v64i8'
-; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %shift = ashr <64 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %shift = ashr <64 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <64 x i8> %shift
;
%shift = ashr <64 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
diff --git a/llvm/test/Analysis/CostModel/X86/vshift-lshr-codesize.ll b/llvm/test/Analysis/CostModel/X86/vshift-lshr-codesize.ll
index a0e15bb8ff738e..644fcbbfefdf95 100644
--- a/llvm/test/Analysis/CostModel/X86/vshift-lshr-codesize.ll
+++ b/llvm/test/Analysis/CostModel/X86/vshift-lshr-codesize.ll
@@ -1619,9 +1619,17 @@ define <16 x i8> @splatconstant_shift_v16i8(<16 x i8> %a) {
; XOPAVX2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %shift = lshr <16 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
; XOPAVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x i8> %shift
;
-; AVX512-LABEL: 'splatconstant_shift_v16i8'
-; AVX512-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %shift = lshr <16 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
-; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x i8> %shift
+; AVX512F-LABEL: 'splatconstant_shift_v16i8'
+; AVX512F-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %shift = lshr <16 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; AVX512F-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x i8> %shift
+;
+; AVX512BW-LABEL: 'splatconstant_shift_v16i8'
+; AVX512BW-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %shift = lshr <16 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; AVX512BW-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x i8> %shift
+;
+; AVX512GFNI-LABEL: 'splatconstant_shift_v16i8'
+; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %shift = lshr <16 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x i8> %shift
;
%shift = lshr <16 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
ret <16 x i8> %shift
@@ -1652,9 +1660,17 @@ define <32 x i8> @splatconstant_shift_v32i8(<32 x i8> %a) {
; XOPAVX2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %shift = lshr <32 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
; XOPAVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <32 x i8> %shift
;
-; AVX512-LABEL: 'splatconstant_shift_v32i8'
-; AVX512-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %shift = lshr <32 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
-; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <32 x i8> %shift
+; AVX512F-LABEL: 'splatconstant_shift_v32i8'
+; AVX512F-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %shift = lshr <32 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; AVX512F-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <32 x i8> %shift
+;
+; AVX512BW-LABEL: 'splatconstant_shift_v32i8'
+; AVX512BW-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %shift = lshr <32 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; AVX512BW-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <32 x i8> %shift
+;
+; AVX512GFNI-LABEL: 'splatconstant_shift_v32i8'
+; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %shift = lshr <32 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <32 x i8> %shift
;
%shift = lshr <32 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
ret <32 x i8> %shift
@@ -1694,7 +1710,7 @@ define <64 x i8> @splatconstant_shift_v64i8(<64 x i8> %a) {
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <64 x i8> %shift
;
; AVX512GFNI-LABEL: 'splatconstant_shift_v64i8'
-; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %shift = lshr <64 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %shift = lshr <64 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <64 x i8> %shift
;
%shift = lshr <64 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
diff --git a/llvm/test/Analysis/CostModel/X86/vshift-lshr-latency.ll b/llvm/test/Analysis/CostModel/X86/vshift-lshr-latency.ll
index 61620e2cc97ed8..f879a09d067e65 100644
--- a/llvm/test/Analysis/CostModel/X86/vshift-lshr-latency.ll
+++ b/llvm/test/Analysis/CostModel/X86/vshift-lshr-latency.ll
@@ -1778,7 +1778,7 @@ define <16 x i8> @splatconstant_shift_v16i8(<16 x i8> %a) {
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x i8> %shift
;
; AVX512GFNI-LABEL: 'splatconstant_shift_v16i8'
-; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %shift = lshr <16 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %shift = lshr <16 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x i8> %shift
;
%shift = lshr <16 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
@@ -1806,9 +1806,17 @@ define <32 x i8> @splatconstant_shift_v32i8(<32 x i8> %a) {
; XOPAVX2-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %shift = lshr <32 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
; XOPAVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <32 x i8> %shift
;
-; AVX512-LABEL: 'splatconstant_shift_v32i8'
-; AVX512-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %shift = lshr <32 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
-; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <32 x i8> %shift
+; AVX512F-LABEL: 'splatconstant_shift_v32i8'
+; AVX512F-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %shift = lshr <32 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; AVX512F-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <32 x i8> %shift
+;
+; AVX512BW-LABEL: 'splatconstant_shift_v32i8'
+; AVX512BW-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %shift = lshr <32 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; AVX512BW-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <32 x i8> %shift
+;
+; AVX512GFNI-LABEL: 'splatconstant_shift_v32i8'
+; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %shift = lshr <32 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <32 x i8> %shift
;
%shift = lshr <32 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
ret <32 x i8> %shift
@@ -1844,7 +1852,7 @@ define <64 x i8> @splatconstant_shift_v64i8(<64 x i8> %a) {
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <64 x i8> %shift
;
; AVX512GFNI-LABEL: 'splatconstant_shift_v64i8'
-; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %shift = lshr <64 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %shift = lshr <64 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <64 x i8> %shift
;
%shift = lshr <64 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
diff --git a/llvm/test/Analysis/CostModel/X86/vshift-lshr-sizelatency.ll b/llvm/test/Analysis/CostModel/X86/vshift-lshr-sizelatency.ll
index e6b6ac75b65d58..fe472342e21445 100644
--- a/llvm/test/Analysis/CostModel/X86/vshift-lshr-sizelatency.ll
+++ b/llvm/test/Analysis/CostModel/X86/vshift-lshr-sizelatency.ll
@@ -1635,9 +1635,17 @@ define <16 x i8> @splatconstant_shift_v16i8(<16 x i8> %a) {
; XOPAVX2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %shift = lshr <16 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
; XOPAVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x i8> %shift
;
-; AVX512-LABEL: 'splatconstant_shift_v16i8'
-; AVX512-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %shift = lshr <16 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
-; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x i8> %shift
+; AVX512F-LABEL: 'splatconstant_shift_v16i8'
+; AVX512F-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %shift = lshr <16 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; AVX512F-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x i8> %shift
+;
+; AVX512BW-LABEL: 'splatconstant_shift_v16i8'
+; AVX512BW-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %shift = lshr <16 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; AVX512BW-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x i8> %shift
+;
+; AVX512GFNI-LABEL: 'splatconstant_shift_v16i8'
+; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %shift = lshr <16 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x i8> %shift
;
%shift = lshr <16 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
ret <16 x i8> %shift
@@ -1677,7 +1685,7 @@ define <32 x i8> @splatconstant_shift_v32i8(<32 x i8> %a) {
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <32 x i8> %shift
;
; AVX512GFNI-LABEL: 'splatconstant_shift_v32i8'
-; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %shift = lshr <32 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %shift = lshr <32 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <32 x i8> %shift
;
%shift = lshr <32 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
@@ -1718,7 +1726,7 @@ define <64 x i8> @splatconstant_shift_v64i8(<64 x i8> %a) {
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <64 x i8> %shift
;
; AVX512GFNI-LABEL: 'splatconstant_shift_v64i8'
-; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %shift = lshr <64 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %shift = lshr <64 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <64 x i8> %shift
;
%shift = lshr <64 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
diff --git a/llvm/test/Analysis/CostModel/X86/vshift-shl-codesize.ll b/llvm/test/Analysis/CostModel/X86/vshift-shl-codesize.ll
index 265658b1e3a2da..1045b827da7cad 100644
--- a/llvm/test/Analysis/CostModel/X86/vshift-shl-codesize.ll
+++ b/llvm/test/Analysis/CostModel/X86/vshift-shl-codesize.ll
@@ -1593,9 +1593,17 @@ define <16 x i8> @splatconstant_shift_v16i8(<16 x i8> %a) {
; XOPAVX2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %shift = shl <16 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
; XOPAVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x i8> %shift
;
-; AVX512-LABEL: 'splatconstant_shift_v16i8'
-; AVX512-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %shift = shl <16 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
-; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x i8> %shift
+; AVX512F-LABEL: 'splatconstant_shift_v16i8'
+; AVX512F-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %shift = shl <16 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; AVX512F-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x i8> %shift
+;
+; AVX512BW-LABEL: 'splatconstant_shift_v16i8'
+; AVX512BW-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %shift = shl <16 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; AVX512BW-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x i8> %shift
+;
+; AVX512GFNI-LABEL: 'splatconstant_shift_v16i8'
+; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %shift = shl <16 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x i8> %shift
;
%shift = shl <16 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
ret <16 x i8> %shift
@@ -1626,9 +1634,17 @@ define <32 x i8> @splatconstant_shift_v32i8(<32 x i8> %a) {
; XOPAVX2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %shift = shl <32 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
; XOPAVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <32 x i8> %shift
;
-; AVX512-LABEL: 'splatconstant_shift_v32i8'
-; AVX512-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %shift = shl <32 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
-; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <32 x i8> %shift
+; AVX512F-LABEL: 'splatconstant_shift_v32i8'
+; AVX512F-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %shift = shl <32 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; AVX512F-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <32 x i8> %shift
+;
+; AVX512BW-LABEL: 'splatconstant_shift_v32i8'
+; AVX512BW-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %shift = shl <32 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; AVX512BW-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <32 x i8> %shift
+;
+; AVX512GFNI-LABEL: 'splatconstant_shift_v32i8'
+; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %shift = shl <32 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <32 x i8> %shift
;
%shift = shl <32 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
ret <32 x i8> %shift
@@ -1668,7 +1684,7 @@ define <64 x i8> @splatconstant_shift_v64i8(<64 x i8> %a) {
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <64 x i8> %shift
;
; AVX512GFNI-LABEL: 'splatconstant_shift_v64i8'
-; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %shift = shl <64 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %shift = shl <64 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <64 x i8> %shift
;
%shift = shl <64 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
diff --git a/llvm/test/Analysis/CostModel/X86/vshift-shl-latency.ll b/llvm/test/Analysis/CostModel/X86/vshift-shl-latency.ll
index 42c91144ff6f99..3ae71daf50a306 100644
--- a/llvm/test/Analysis/CostModel/X86/vshift-shl-latency.ll
+++ b/llvm/test/Analysis/CostModel/X86/vshift-shl-latency.ll
@@ -1738,7 +1738,7 @@ define <16 x i8> @splatconstant_shift_v16i8(<16 x i8> %a) {
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x i8> %shift
;
; AVX512GFNI-LABEL: 'splatconstant_shift_v16i8'
-; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %shift = shl <16 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %shift = shl <16 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x i8> %shift
;
%shift = shl <16 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
@@ -1766,9 +1766,17 @@ define <32 x i8> @splatconstant_shift_v32i8(<32 x i8> %a) {
; XOPAVX2-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %shift = shl <32 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
; XOPAVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <32 x i8> %shift
;
-; AVX512-LABEL: 'splatconstant_shift_v32i8'
-; AVX512-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %shift = shl <32 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
-; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <32 x i8> %shift
+; AVX512F-LABEL: 'splatconstant_shift_v32i8'
+; AVX512F-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %shift = shl <32 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; AVX512F-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <32 x i8> %shift
+;
+; AVX512BW-LABEL: 'splatconstant_shift_v32i8'
+; AVX512BW-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %shift = shl <32 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; AVX512BW-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <32 x i8> %shift
+;
+; AVX512GFNI-LABEL: 'splatconstant_shift_v32i8'
+; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %shift = shl <32 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <32 x i8> %shift
;
%shift = shl <32 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
ret <32 x i8> %shift
@@ -1804,7 +1812,7 @@ define <64 x i8> @splatconstant_shift_v64i8(<64 x i8> %a) {
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <64 x i8> %shift
;
; AVX512GFNI-LABEL: 'splatconstant_shift_v64i8'
-; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %shift = shl <64 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %shift = shl <64 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <64 x i8> %shift
;
%shift = shl <64 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
diff --git a/llvm/test/Analysis/CostModel/X86/vshift-shl-sizelatency.ll b/llvm/test/Analysis/CostModel/X86/vshift-shl-sizelatency.ll
index 47b24df063ef70..4256a73a7cf735 100644
--- a/llvm/test/Analysis/CostModel/X86/vshift-shl-sizelatency.ll
+++ b/llvm/test/Analysis/CostModel/X86/vshift-shl-sizelatency.ll
@@ -1691,9 +1691,17 @@ define <16 x i8> @splatconstant_shift_v16i8(<16 x i8> %a) {
; XOPAVX2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %shift = shl <16 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
; XOPAVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x i8> %shift
;
-; AVX512-LABEL: 'splatconstant_shift_v16i8'
-; AVX512-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %shift = shl <16 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
-; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x i8> %shift
+; AVX512F-LABEL: 'splatconstant_shift_v16i8'
+; AVX512F-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %shift = shl <16 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; AVX512F-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x i8> %shift
+;
+; AVX512BW-LABEL: 'splatconstant_shift_v16i8'
+; AVX512BW-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %shift = shl <16 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; AVX512BW-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x i8> %shift
+;
+; AVX512GFNI-LABEL: 'splatconstant_shift_v16i8'
+; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %shift = shl <16 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x i8> %shift
;
%shift = shl <16 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
ret <16 x i8> %shift
@@ -1729,7 +1737,7 @@ define <32 x i8> @splatconstant_shift_v32i8(<32 x i8> %a) {
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <32 x i8> %shift
;
; AVX512GFNI-LABEL: 'splatconstant_shift_v32i8'
-; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %shift = shl <32 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %shift = shl <32 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <32 x i8> %shift
;
%shift = shl <32 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
@@ -1766,7 +1774,7 @@ define <64 x i8> @splatconstant_shift_v64i8(<64 x i8> %a) {
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <64 x i8> %shift
;
; AVX512GFNI-LABEL: 'splatconstant_shift_v64i8'
-; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %shift = shl <64 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %shift = shl <64 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
; AVX512GFNI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <64 x i8> %shift
;
%shift = shl <64 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
diff --git a/llvm/test/CodeGen/X86/gfni-funnel-shifts.ll b/llvm/test/CodeGen/X86/gfni-funnel-shifts.ll
index afe0ebb9dcb4f0..b3ca9fb04aeb71 100644
--- a/llvm/test/CodeGen/X86/gfni-funnel-shifts.ll
+++ b/llvm/test/CodeGen/X86/gfni-funnel-shifts.ll
@@ -107,16 +107,15 @@ define <16 x i8> @var_fshl_v16i8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %amt) nou
; GFNIAVX512VL-LABEL: var_fshl_v16i8:
; GFNIAVX512VL: # %bb.0:
; GFNIAVX512VL-NEXT: vpbroadcastd {{.*#+}} xmm3 = [7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7]
-; GFNIAVX512VL-NEXT: vpand %xmm3, %xmm2, %xmm4
+; GFNIAVX512VL-NEXT: vpandn %xmm3, %xmm2, %xmm4
; GFNIAVX512VL-NEXT: vpmovzxbd {{.*#+}} zmm4 = xmm4[0],zero,zero,zero,xmm4[1],zero,zero,zero,xmm4[2],zero,zero,zero,xmm4[3],zero,zero,zero,xmm4[4],zero,zero,zero,xmm4[5],zero,zero,zero,xmm4[6],zero,zero,zero,xmm4[7],zero,zero,zero,xmm4[8],zero,zero,zero,xmm4[9],zero,zero,zero,xmm4[10],zero,zero,zero,xmm4[11],zero,zero,zero,xmm4[12],zero,zero,zero,xmm4[13],zero,zero,zero,xmm4[14],zero,zero,zero,xmm4[15],zero,zero,zero
-; GFNIAVX512VL-NEXT: vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero
-; GFNIAVX512VL-NEXT: vpsllvd %zmm4, %zmm0, %zmm0
-; GFNIAVX512VL-NEXT: vpandn %xmm3, %xmm2, %xmm2
-; GFNIAVX512VL-NEXT: vpmovzxbd {{.*#+}} zmm2 = xmm2[0],zero,zero,zero,xmm2[1],zero,zero,zero,xmm2[2],zero,zero,zero,xmm2[3],zero,zero,zero,xmm2[4],zero,zero,zero,xmm2[5],zero,zero,zero,xmm2[6],zero,zero,zero,xmm2[7],zero,zero,zero,xmm2[8],zero,zero,zero,xmm2[9],zero,zero,zero,xmm2[10],zero,zero,zero,xmm2[11],zero,zero,zero,xmm2[12],zero,zero,zero,xmm2[13],zero,zero,zero,xmm2[14],zero,zero,zero,xmm2[15],zero,zero,zero
-; GFNIAVX512VL-NEXT: vpsrlw $1, %xmm1, %xmm1
-; GFNIAVX512VL-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm1, %xmm1
+; GFNIAVX512VL-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm1, %xmm1
; GFNIAVX512VL-NEXT: vpmovzxbd {{.*#+}} zmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero,xmm1[2],zero,zero,zero,xmm1[3],zero,zero,zero,xmm1[4],zero,zero,zero,xmm1[5],zero,zero,zero,xmm1[6],zero,zero,zero,xmm1[7],zero,zero,zero,xmm1[8],zero,zero,zero,xmm1[9],zero,zero,zero,xmm1[10],zero,zero,zero,xmm1[11],zero,zero,zero,xmm1[12],zero,zero,zero,xmm1[13],zero,zero,zero,xmm1[14],zero,zero,zero,xmm1[15],zero,zero,zero
-; GFNIAVX512VL-NEXT: vpsrlvd %zmm2, %zmm1, %zmm1
+; GFNIAVX512VL-NEXT: vpsrlvd %zmm4, %zmm1, %zmm1
+; GFNIAVX512VL-NEXT: vpand %xmm3, %xmm2, %xmm2
+; GFNIAVX512VL-NEXT: vpmovzxbd {{.*#+}} zmm2 = xmm2[0],zero,zero,zero,xmm2[1],zero,zero,zero,xmm2[2],zero,zero,zero,xmm2[3],zero,zero,zero,xmm2[4],zero,zero,zero,xmm2[5],zero,zero,zero,xmm2[6],zero,zero,zero,xmm2[7],zero,zero,zero,xmm2[8],zero,zero,zero,xmm2[9],zero,zero,zero,xmm2[10],zero,zero,zero,xmm2[11],zero,zero,zero,xmm2[12],zero,zero,zero,xmm2[13],zero,zero,zero,xmm2[14],zero,zero,zero,xmm2[15],zero,zero,zero
+; GFNIAVX512VL-NEXT: vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero
+; GFNIAVX512VL-NEXT: vpsllvd %zmm2, %zmm0, %zmm0
; GFNIAVX512VL-NEXT: vpord %zmm1, %zmm0, %zmm0
; GFNIAVX512VL-NEXT: vpmovdb %zmm0, %xmm0
; GFNIAVX512VL-NEXT: vzeroupper
@@ -151,17 +150,14 @@ define <16 x i8> @var_fshr_v16i8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %amt) nou
; GFNISSE-NEXT: movdqa %xmm0, %xmm4
; GFNISSE-NEXT: paddb %xmm0, %xmm4
; GFNISSE-NEXT: movdqa %xmm1, %xmm6
-; GFNISSE-NEXT: psrlw $4, %xmm6
-; GFNISSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm6
+; GFNISSE-NEXT: gf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm6
; GFNISSE-NEXT: pblendvb %xmm0, %xmm6, %xmm1
; GFNISSE-NEXT: movdqa %xmm1, %xmm6
-; GFNISSE-NEXT: psrlw $2, %xmm6
-; GFNISSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm6
+; GFNISSE-NEXT: gf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm6
; GFNISSE-NEXT: movdqa %xmm4, %xmm0
; GFNISSE-NEXT: pblendvb %xmm0, %xmm6, %xmm1
; GFNISSE-NEXT: movdqa %xmm1, %xmm6
-; GFNISSE-NEXT: psrlw $1, %xmm6
-; GFNISSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm6
+; GFNISSE-NEXT: gf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm6
; GFNISSE-NEXT: paddb %xmm4, %xmm4
; GFNISSE-NEXT: movdqa %xmm4, %xmm0
; GFNISSE-NEXT: pblendvb %xmm0, %xmm6, %xmm1
@@ -171,13 +167,11 @@ define <16 x i8> @var_fshr_v16i8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %amt) nou
; GFNISSE-NEXT: paddb %xmm3, %xmm4
; GFNISSE-NEXT: paddb %xmm2, %xmm2
; GFNISSE-NEXT: movdqa %xmm2, %xmm5
-; GFNISSE-NEXT: psllw $4, %xmm5
-; GFNISSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm5
+; GFNISSE-NEXT: gf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm5
; GFNISSE-NEXT: movdqa %xmm3, %xmm0
; GFNISSE-NEXT: pblendvb %xmm0, %xmm5, %xmm2
; GFNISSE-NEXT: movdqa %xmm2, %xmm3
-; GFNISSE-NEXT: psllw $2, %xmm3
-; GFNISSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
+; GFNISSE-NEXT: gf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
; GFNISSE-NEXT: movdqa %xmm4, %xmm0
; GFNISSE-NEXT: pblendvb %xmm0, %xmm3, %xmm2
; GFNISSE-NEXT: movdqa %xmm2, %xmm3
@@ -195,25 +189,20 @@ define <16 x i8> @var_fshr_v16i8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %amt) nou
; GFNIAVX1-NEXT: vpand %xmm3, %xmm2, %xmm4
; GFNIAVX1-NEXT: vpsllw $5, %xmm4, %xmm4
; GFNIAVX1-NEXT: vpaddb %xmm4, %xmm4, %xmm5
-; GFNIAVX1-NEXT: vpsrlw $4, %xmm1, %xmm6
-; GFNIAVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm6, %xmm6
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm6
; GFNIAVX1-NEXT: vpblendvb %xmm4, %xmm6, %xmm1, %xmm1
-; GFNIAVX1-NEXT: vpsrlw $2, %xmm1, %xmm4
-; GFNIAVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4, %xmm4
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm4
; GFNIAVX1-NEXT: vpblendvb %xmm5, %xmm4, %xmm1, %xmm1
-; GFNIAVX1-NEXT: vpsrlw $1, %xmm1, %xmm4
-; GFNIAVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4, %xmm4
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm4
; GFNIAVX1-NEXT: vpaddb %xmm5, %xmm5, %xmm5
; GFNIAVX1-NEXT: vpblendvb %xmm5, %xmm4, %xmm1, %xmm1
; GFNIAVX1-NEXT: vpandn %xmm3, %xmm2, %xmm2
; GFNIAVX1-NEXT: vpsllw $5, %xmm2, %xmm2
; GFNIAVX1-NEXT: vpaddb %xmm2, %xmm2, %xmm3
; GFNIAVX1-NEXT: vpaddb %xmm0, %xmm0, %xmm0
-; GFNIAVX1-NEXT: vpsllw $4, %xmm0, %xmm4
-; GFNIAVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4, %xmm4
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm4
; GFNIAVX1-NEXT: vpblendvb %xmm2, %xmm4, %xmm0, %xmm0
-; GFNIAVX1-NEXT: vpsllw $2, %xmm0, %xmm2
-; GFNIAVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm2
; GFNIAVX1-NEXT: vpblendvb %xmm3, %xmm2, %xmm0, %xmm0
; GFNIAVX1-NEXT: vpaddb %xmm0, %xmm0, %xmm2
; GFNIAVX1-NEXT: vpaddb %xmm3, %xmm3, %xmm3
@@ -227,25 +216,20 @@ define <16 x i8> @var_fshr_v16i8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %amt) nou
; GFNIAVX2-NEXT: vpand %xmm3, %xmm2, %xmm4
; GFNIAVX2-NEXT: vpsllw $5, %xmm4, %xmm4
; GFNIAVX2-NEXT: vpaddb %xmm4, %xmm4, %xmm5
-; GFNIAVX2-NEXT: vpsrlw $4, %xmm1, %xmm6
-; GFNIAVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm6, %xmm6
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm6
; GFNIAVX2-NEXT: vpblendvb %xmm4, %xmm6, %xmm1, %xmm1
-; GFNIAVX2-NEXT: vpsrlw $2, %xmm1, %xmm4
-; GFNIAVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4, %xmm4
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm4
; GFNIAVX2-NEXT: vpblendvb %xmm5, %xmm4, %xmm1, %xmm1
-; GFNIAVX2-NEXT: vpsrlw $1, %xmm1, %xmm4
-; GFNIAVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4, %xmm4
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm4
; GFNIAVX2-NEXT: vpaddb %xmm5, %xmm5, %xmm5
; GFNIAVX2-NEXT: vpblendvb %xmm5, %xmm4, %xmm1, %xmm1
; GFNIAVX2-NEXT: vpandn %xmm3, %xmm2, %xmm2
; GFNIAVX2-NEXT: vpsllw $5, %xmm2, %xmm2
; GFNIAVX2-NEXT: vpaddb %xmm2, %xmm2, %xmm3
; GFNIAVX2-NEXT: vpaddb %xmm0, %xmm0, %xmm0
-; GFNIAVX2-NEXT: vpsllw $4, %xmm0, %xmm4
-; GFNIAVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4, %xmm4
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm4
; GFNIAVX2-NEXT: vpblendvb %xmm2, %xmm4, %xmm0, %xmm0
-; GFNIAVX2-NEXT: vpsllw $2, %xmm0, %xmm2
-; GFNIAVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm2
; GFNIAVX2-NEXT: vpblendvb %xmm3, %xmm2, %xmm0, %xmm0
; GFNIAVX2-NEXT: vpaddb %xmm0, %xmm0, %xmm2
; GFNIAVX2-NEXT: vpaddb %xmm3, %xmm3, %xmm3
@@ -492,19 +476,15 @@ define <16 x i8> @constant_fshr_v16i8(<16 x i8> %a, <16 x i8> %b) nounwind {
define <16 x i8> @splatconstant_fshl_v16i8(<16 x i8> %a, <16 x i8> %b) nounwind {
; GFNISSE-LABEL: splatconstant_fshl_v16i8:
; GFNISSE: # %bb.0:
-; GFNISSE-NEXT: psrlw $5, %xmm1
-; GFNISSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
-; GFNISSE-NEXT: psllw $3, %xmm0
-; GFNISSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; GFNISSE-NEXT: gf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; GFNISSE-NEXT: gf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; GFNISSE-NEXT: por %xmm1, %xmm0
; GFNISSE-NEXT: retq
;
; GFNIAVX1OR2-LABEL: splatconstant_fshl_v16i8:
; GFNIAVX1OR2: # %bb.0:
-; GFNIAVX1OR2-NEXT: vpsrlw $5, %xmm1, %xmm1
-; GFNIAVX1OR2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
-; GFNIAVX1OR2-NEXT: vpsllw $3, %xmm0, %xmm0
-; GFNIAVX1OR2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; GFNIAVX1OR2-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
+; GFNIAVX1OR2-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; GFNIAVX1OR2-NEXT: vpor %xmm1, %xmm0, %xmm0
; GFNIAVX1OR2-NEXT: retq
;
@@ -522,25 +502,23 @@ declare <16 x i8> @llvm.fshl.v16i8(<16 x i8>, <16 x i8>, <16 x i8>)
define <16 x i8> @splatconstant_fshr_v16i8(<16 x i8> %a, <16 x i8> %b) nounwind {
; GFNISSE-LABEL: splatconstant_fshr_v16i8:
; GFNISSE: # %bb.0:
+; GFNISSE-NEXT: gf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; GFNISSE-NEXT: paddb %xmm0, %xmm0
-; GFNISSE-NEXT: psrlw $7, %xmm1
-; GFNISSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; GFNISSE-NEXT: por %xmm1, %xmm0
; GFNISSE-NEXT: retq
;
; GFNIAVX1OR2-LABEL: splatconstant_fshr_v16i8:
; GFNIAVX1OR2: # %bb.0:
+; GFNIAVX1OR2-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; GFNIAVX1OR2-NEXT: vpaddb %xmm0, %xmm0, %xmm0
-; GFNIAVX1OR2-NEXT: vpsrlw $7, %xmm1, %xmm1
-; GFNIAVX1OR2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; GFNIAVX1OR2-NEXT: vpor %xmm1, %xmm0, %xmm0
; GFNIAVX1OR2-NEXT: retq
;
; GFNIAVX512-LABEL: splatconstant_fshr_v16i8:
; GFNIAVX512: # %bb.0:
-; GFNIAVX512-NEXT: vpsrlw $7, %xmm1, %xmm1
-; GFNIAVX512-NEXT: vpaddb %xmm0, %xmm0, %xmm0
-; GFNIAVX512-NEXT: vpternlogd $248, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm1, %xmm0
+; GFNIAVX512-NEXT: vpaddw %xmm0, %xmm0, %xmm2
+; GFNIAVX512-NEXT: vpsrlw $7, %xmm1, %xmm0
+; GFNIAVX512-NEXT: vpternlogd $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm2, %xmm0
; GFNIAVX512-NEXT: retq
%res = call <16 x i8> @llvm.fshr.v16i8(<16 x i8> %a, <16 x i8> %b, <16 x i8> <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>)
ret <16 x i8> %res
@@ -721,28 +699,22 @@ define <32 x i8> @var_fshl_v32i8(<32 x i8> %a, <32 x i8> %b, <32 x i8> %amt) nou
; GFNIAVX512VL-NEXT: vpbroadcastd {{.*#+}} ymm3 = [7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7]
; GFNIAVX512VL-NEXT: vpandn %ymm3, %ymm2, %ymm4
; GFNIAVX512VL-NEXT: vpsllw $5, %ymm4, %ymm4
-; GFNIAVX512VL-NEXT: vpsrlw $1, %ymm1, %ymm1
-; GFNIAVX512VL-NEXT: vpbroadcastd {{.*#+}} ymm5 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127]
-; GFNIAVX512VL-NEXT: vpand %ymm5, %ymm1, %ymm1
-; GFNIAVX512VL-NEXT: vpsrlw $4, %ymm1, %ymm6
-; GFNIAVX512VL-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm6, %ymm6
+; GFNIAVX512VL-NEXT: vpbroadcastq {{.*#+}} ymm5 = [145249953336295424,145249953336295424,145249953336295424,145249953336295424]
+; GFNIAVX512VL-NEXT: vgf2p8affineqb $0, %ymm5, %ymm1, %ymm1
+; GFNIAVX512VL-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm1, %ymm6
; GFNIAVX512VL-NEXT: vpblendvb %ymm4, %ymm6, %ymm1, %ymm1
-; GFNIAVX512VL-NEXT: vpsrlw $2, %ymm1, %ymm6
-; GFNIAVX512VL-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm6, %ymm6
+; GFNIAVX512VL-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm1, %ymm6
; GFNIAVX512VL-NEXT: vpaddb %ymm4, %ymm4, %ymm4
; GFNIAVX512VL-NEXT: vpblendvb %ymm4, %ymm6, %ymm1, %ymm1
-; GFNIAVX512VL-NEXT: vpsrlw $1, %ymm1, %ymm6
-; GFNIAVX512VL-NEXT: vpand %ymm5, %ymm6, %ymm5
+; GFNIAVX512VL-NEXT: vgf2p8affineqb $0, %ymm5, %ymm1, %ymm5
; GFNIAVX512VL-NEXT: vpaddb %ymm4, %ymm4, %ymm4
; GFNIAVX512VL-NEXT: vpblendvb %ymm4, %ymm5, %ymm1, %ymm1
; GFNIAVX512VL-NEXT: vpand %ymm3, %ymm2, %ymm2
; GFNIAVX512VL-NEXT: vpsllw $5, %ymm2, %ymm2
; GFNIAVX512VL-NEXT: vpaddb %ymm2, %ymm2, %ymm3
-; GFNIAVX512VL-NEXT: vpsllw $4, %ymm0, %ymm4
-; GFNIAVX512VL-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm4, %ymm4
+; GFNIAVX512VL-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %ymm4
; GFNIAVX512VL-NEXT: vpblendvb %ymm2, %ymm4, %ymm0, %ymm0
-; GFNIAVX512VL-NEXT: vpsllw $2, %ymm0, %ymm2
-; GFNIAVX512VL-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm2, %ymm2
+; GFNIAVX512VL-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %ymm2
; GFNIAVX512VL-NEXT: vpblendvb %ymm3, %ymm2, %ymm0, %ymm0
; GFNIAVX512VL-NEXT: vpaddb %ymm0, %ymm0, %ymm2
; GFNIAVX512VL-NEXT: vpaddb %ymm3, %ymm3, %ymm3
@@ -771,40 +743,35 @@ define <32 x i8> @var_fshr_v32i8(<32 x i8> %a, <32 x i8> %b, <32 x i8> %amt) nou
; GFNISSE: # %bb.0:
; GFNISSE-NEXT: movdqa %xmm4, %xmm6
; GFNISSE-NEXT: movdqa %xmm0, %xmm4
+; GFNISSE-NEXT: movdqa {{.*#+}} xmm8 = [1161999622361579520,1161999622361579520]
; GFNISSE-NEXT: movdqa %xmm2, %xmm9
-; GFNISSE-NEXT: psrlw $4, %xmm9
-; GFNISSE-NEXT: movdqa {{.*#+}} xmm8 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
-; GFNISSE-NEXT: pand %xmm8, %xmm9
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm8, %xmm9
; GFNISSE-NEXT: movdqa {{.*#+}} xmm7 = [7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7]
; GFNISSE-NEXT: movdqa %xmm6, %xmm0
; GFNISSE-NEXT: pand %xmm7, %xmm0
; GFNISSE-NEXT: psllw $5, %xmm0
; GFNISSE-NEXT: pblendvb %xmm0, %xmm9, %xmm2
+; GFNISSE-NEXT: movdqa {{.*#+}} xmm9 = [290499906672525312,290499906672525312]
; GFNISSE-NEXT: movdqa %xmm2, %xmm10
-; GFNISSE-NEXT: psrlw $2, %xmm10
-; GFNISSE-NEXT: movdqa {{.*#+}} xmm9 = [63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63]
-; GFNISSE-NEXT: pand %xmm9, %xmm10
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm9, %xmm10
; GFNISSE-NEXT: paddb %xmm0, %xmm0
; GFNISSE-NEXT: pblendvb %xmm0, %xmm10, %xmm2
+; GFNISSE-NEXT: movdqa {{.*#+}} xmm10 = [145249953336295424,145249953336295424]
; GFNISSE-NEXT: movdqa %xmm2, %xmm11
-; GFNISSE-NEXT: psrlw $1, %xmm11
-; GFNISSE-NEXT: movdqa {{.*#+}} xmm10 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127]
-; GFNISSE-NEXT: pand %xmm10, %xmm11
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm10, %xmm11
; GFNISSE-NEXT: paddb %xmm0, %xmm0
; GFNISSE-NEXT: pblendvb %xmm0, %xmm11, %xmm2
; GFNISSE-NEXT: paddb %xmm4, %xmm4
+; GFNISSE-NEXT: pmovsxdq {{.*#+}} xmm11 = [16909320,16909320]
; GFNISSE-NEXT: movdqa %xmm4, %xmm12
-; GFNISSE-NEXT: psllw $4, %xmm12
-; GFNISSE-NEXT: movdqa {{.*#+}} xmm11 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240]
-; GFNISSE-NEXT: pand %xmm11, %xmm12
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm11, %xmm12
; GFNISSE-NEXT: pandn %xmm7, %xmm6
; GFNISSE-NEXT: psllw $5, %xmm6
; GFNISSE-NEXT: movdqa %xmm6, %xmm0
; GFNISSE-NEXT: pblendvb %xmm0, %xmm12, %xmm4
+; GFNISSE-NEXT: movdqa {{.*#+}} xmm12 = [1108169199648,1108169199648]
; GFNISSE-NEXT: movdqa %xmm4, %xmm13
-; GFNISSE-NEXT: psllw $2, %xmm13
-; GFNISSE-NEXT: movdqa {{.*#+}} xmm12 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252]
-; GFNISSE-NEXT: pand %xmm12, %xmm13
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm12, %xmm13
; GFNISSE-NEXT: paddb %xmm6, %xmm6
; GFNISSE-NEXT: movdqa %xmm6, %xmm0
; GFNISSE-NEXT: pblendvb %xmm0, %xmm13, %xmm4
@@ -815,33 +782,28 @@ define <32 x i8> @var_fshr_v32i8(<32 x i8> %a, <32 x i8> %b, <32 x i8> %amt) nou
; GFNISSE-NEXT: pblendvb %xmm0, %xmm13, %xmm4
; GFNISSE-NEXT: por %xmm2, %xmm4
; GFNISSE-NEXT: movdqa %xmm3, %xmm2
-; GFNISSE-NEXT: psrlw $4, %xmm2
-; GFNISSE-NEXT: pand %xmm8, %xmm2
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm8, %xmm2
; GFNISSE-NEXT: movdqa %xmm5, %xmm0
; GFNISSE-NEXT: pand %xmm7, %xmm0
; GFNISSE-NEXT: psllw $5, %xmm0
; GFNISSE-NEXT: pblendvb %xmm0, %xmm2, %xmm3
; GFNISSE-NEXT: movdqa %xmm3, %xmm2
-; GFNISSE-NEXT: psrlw $2, %xmm2
-; GFNISSE-NEXT: pand %xmm9, %xmm2
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm9, %xmm2
; GFNISSE-NEXT: paddb %xmm0, %xmm0
; GFNISSE-NEXT: pblendvb %xmm0, %xmm2, %xmm3
; GFNISSE-NEXT: movdqa %xmm3, %xmm2
-; GFNISSE-NEXT: psrlw $1, %xmm2
-; GFNISSE-NEXT: pand %xmm10, %xmm2
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm10, %xmm2
; GFNISSE-NEXT: paddb %xmm0, %xmm0
; GFNISSE-NEXT: pblendvb %xmm0, %xmm2, %xmm3
; GFNISSE-NEXT: paddb %xmm1, %xmm1
; GFNISSE-NEXT: movdqa %xmm1, %xmm2
-; GFNISSE-NEXT: psllw $4, %xmm2
-; GFNISSE-NEXT: pand %xmm11, %xmm2
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm11, %xmm2
; GFNISSE-NEXT: pandn %xmm7, %xmm5
; GFNISSE-NEXT: psllw $5, %xmm5
; GFNISSE-NEXT: movdqa %xmm5, %xmm0
; GFNISSE-NEXT: pblendvb %xmm0, %xmm2, %xmm1
; GFNISSE-NEXT: movdqa %xmm1, %xmm2
-; GFNISSE-NEXT: psllw $2, %xmm2
-; GFNISSE-NEXT: pand %xmm12, %xmm2
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm12, %xmm2
; GFNISSE-NEXT: paddb %xmm5, %xmm5
; GFNISSE-NEXT: movdqa %xmm5, %xmm0
; GFNISSE-NEXT: pblendvb %xmm0, %xmm2, %xmm1
@@ -856,100 +818,95 @@ define <32 x i8> @var_fshr_v32i8(<32 x i8> %a, <32 x i8> %b, <32 x i8> %amt) nou
;
; GFNIAVX1-LABEL: var_fshr_v32i8:
; GFNIAVX1: # %bb.0:
-; GFNIAVX1-NEXT: vextractf128 $1, %ymm1, %xmm5
-; GFNIAVX1-NEXT: vpsrlw $4, %xmm5, %xmm3
-; GFNIAVX1-NEXT: vbroadcastss {{.*#+}} xmm4 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
-; GFNIAVX1-NEXT: vpand %xmm4, %xmm3, %xmm6
+; GFNIAVX1-NEXT: vextractf128 $1, %ymm1, %xmm4
+; GFNIAVX1-NEXT: vmovddup {{.*#+}} xmm5 = [1161999622361579520,1161999622361579520]
+; GFNIAVX1-NEXT: # xmm5 = mem[0,0]
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm5, %xmm4, %xmm6
; GFNIAVX1-NEXT: vbroadcastss {{.*#+}} ymm3 = [7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7]
; GFNIAVX1-NEXT: vandps %ymm3, %ymm2, %ymm2
; GFNIAVX1-NEXT: vextractf128 $1, %ymm2, %xmm7
; GFNIAVX1-NEXT: vpsllw $5, %xmm7, %xmm8
-; GFNIAVX1-NEXT: vpblendvb %xmm8, %xmm6, %xmm5, %xmm6
-; GFNIAVX1-NEXT: vpsrlw $2, %xmm6, %xmm9
-; GFNIAVX1-NEXT: vbroadcastss {{.*#+}} xmm5 = [63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63]
-; GFNIAVX1-NEXT: vpand %xmm5, %xmm9, %xmm9
+; GFNIAVX1-NEXT: vpblendvb %xmm8, %xmm6, %xmm4, %xmm4
+; GFNIAVX1-NEXT: vmovddup {{.*#+}} xmm6 = [290499906672525312,290499906672525312]
+; GFNIAVX1-NEXT: # xmm6 = mem[0,0]
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm6, %xmm4, %xmm9
; GFNIAVX1-NEXT: vpaddb %xmm8, %xmm8, %xmm8
-; GFNIAVX1-NEXT: vpblendvb %xmm8, %xmm9, %xmm6, %xmm9
-; GFNIAVX1-NEXT: vpsrlw $1, %xmm9, %xmm10
-; GFNIAVX1-NEXT: vbroadcastss {{.*#+}} xmm6 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127]
-; GFNIAVX1-NEXT: vpand %xmm6, %xmm10, %xmm10
+; GFNIAVX1-NEXT: vpblendvb %xmm8, %xmm9, %xmm4, %xmm4
+; GFNIAVX1-NEXT: vmovddup {{.*#+}} xmm9 = [145249953336295424,145249953336295424]
+; GFNIAVX1-NEXT: # xmm9 = mem[0,0]
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm9, %xmm4, %xmm10
; GFNIAVX1-NEXT: vpaddb %xmm8, %xmm8, %xmm8
-; GFNIAVX1-NEXT: vpblendvb %xmm8, %xmm10, %xmm9, %xmm8
-; GFNIAVX1-NEXT: vextractf128 $1, %ymm0, %xmm9
-; GFNIAVX1-NEXT: vpaddb %xmm9, %xmm9, %xmm9
-; GFNIAVX1-NEXT: vpsllw $4, %xmm9, %xmm10
-; GFNIAVX1-NEXT: vbroadcastss {{.*#+}} xmm11 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240]
-; GFNIAVX1-NEXT: vpand %xmm11, %xmm10, %xmm10
+; GFNIAVX1-NEXT: vpblendvb %xmm8, %xmm10, %xmm4, %xmm4
+; GFNIAVX1-NEXT: vextractf128 $1, %ymm0, %xmm8
+; GFNIAVX1-NEXT: vpaddb %xmm8, %xmm8, %xmm8
+; GFNIAVX1-NEXT: vmovddup {{.*#+}} xmm10 = [16909320,16909320]
+; GFNIAVX1-NEXT: # xmm10 = mem[0,0]
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm10, %xmm8, %xmm11
; GFNIAVX1-NEXT: vpxor %xmm3, %xmm7, %xmm7
; GFNIAVX1-NEXT: vpsllw $5, %xmm7, %xmm7
-; GFNIAVX1-NEXT: vpblendvb %xmm7, %xmm10, %xmm9, %xmm9
-; GFNIAVX1-NEXT: vpsllw $2, %xmm9, %xmm10
-; GFNIAVX1-NEXT: vbroadcastss {{.*#+}} xmm12 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252]
-; GFNIAVX1-NEXT: vpand %xmm12, %xmm10, %xmm10
+; GFNIAVX1-NEXT: vpblendvb %xmm7, %xmm11, %xmm8, %xmm8
+; GFNIAVX1-NEXT: vmovddup {{.*#+}} xmm11 = [1108169199648,1108169199648]
+; GFNIAVX1-NEXT: # xmm11 = mem[0,0]
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm11, %xmm8, %xmm12
; GFNIAVX1-NEXT: vpaddb %xmm7, %xmm7, %xmm7
-; GFNIAVX1-NEXT: vpblendvb %xmm7, %xmm10, %xmm9, %xmm9
-; GFNIAVX1-NEXT: vpaddb %xmm9, %xmm9, %xmm10
+; GFNIAVX1-NEXT: vpblendvb %xmm7, %xmm12, %xmm8, %xmm8
+; GFNIAVX1-NEXT: vpaddb %xmm8, %xmm8, %xmm12
; GFNIAVX1-NEXT: vpaddb %xmm7, %xmm7, %xmm7
-; GFNIAVX1-NEXT: vpblendvb %xmm7, %xmm10, %xmm9, %xmm7
-; GFNIAVX1-NEXT: vpor %xmm7, %xmm8, %xmm7
-; GFNIAVX1-NEXT: vpsrlw $4, %xmm1, %xmm8
-; GFNIAVX1-NEXT: vpand %xmm4, %xmm8, %xmm4
-; GFNIAVX1-NEXT: vpsllw $5, %xmm2, %xmm8
-; GFNIAVX1-NEXT: vpblendvb %xmm8, %xmm4, %xmm1, %xmm1
-; GFNIAVX1-NEXT: vpsrlw $2, %xmm1, %xmm4
-; GFNIAVX1-NEXT: vpand %xmm5, %xmm4, %xmm4
-; GFNIAVX1-NEXT: vpaddb %xmm8, %xmm8, %xmm5
-; GFNIAVX1-NEXT: vpblendvb %xmm5, %xmm4, %xmm1, %xmm1
-; GFNIAVX1-NEXT: vpsrlw $1, %xmm1, %xmm4
-; GFNIAVX1-NEXT: vpand %xmm6, %xmm4, %xmm4
-; GFNIAVX1-NEXT: vpaddb %xmm5, %xmm5, %xmm5
-; GFNIAVX1-NEXT: vpblendvb %xmm5, %xmm4, %xmm1, %xmm1
+; GFNIAVX1-NEXT: vpblendvb %xmm7, %xmm12, %xmm8, %xmm7
+; GFNIAVX1-NEXT: vpor %xmm4, %xmm7, %xmm4
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm5, %xmm1, %xmm5
+; GFNIAVX1-NEXT: vpsllw $5, %xmm2, %xmm7
+; GFNIAVX1-NEXT: vpblendvb %xmm7, %xmm5, %xmm1, %xmm1
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm6, %xmm1, %xmm5
+; GFNIAVX1-NEXT: vpaddb %xmm7, %xmm7, %xmm6
+; GFNIAVX1-NEXT: vpblendvb %xmm6, %xmm5, %xmm1, %xmm1
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm9, %xmm1, %xmm5
+; GFNIAVX1-NEXT: vpaddb %xmm6, %xmm6, %xmm6
+; GFNIAVX1-NEXT: vpblendvb %xmm6, %xmm5, %xmm1, %xmm1
; GFNIAVX1-NEXT: vpaddb %xmm0, %xmm0, %xmm0
-; GFNIAVX1-NEXT: vpsllw $4, %xmm0, %xmm4
-; GFNIAVX1-NEXT: vpand %xmm4, %xmm11, %xmm4
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm10, %xmm0, %xmm5
; GFNIAVX1-NEXT: vpxor %xmm3, %xmm2, %xmm2
; GFNIAVX1-NEXT: vpsllw $5, %xmm2, %xmm2
-; GFNIAVX1-NEXT: vpblendvb %xmm2, %xmm4, %xmm0, %xmm0
-; GFNIAVX1-NEXT: vpsllw $2, %xmm0, %xmm3
-; GFNIAVX1-NEXT: vpand %xmm3, %xmm12, %xmm3
+; GFNIAVX1-NEXT: vpblendvb %xmm2, %xmm5, %xmm0, %xmm0
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm11, %xmm0, %xmm3
; GFNIAVX1-NEXT: vpaddb %xmm2, %xmm2, %xmm2
; GFNIAVX1-NEXT: vpblendvb %xmm2, %xmm3, %xmm0, %xmm0
; GFNIAVX1-NEXT: vpaddb %xmm0, %xmm0, %xmm3
; GFNIAVX1-NEXT: vpaddb %xmm2, %xmm2, %xmm2
; GFNIAVX1-NEXT: vpblendvb %xmm2, %xmm3, %xmm0, %xmm0
; GFNIAVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
-; GFNIAVX1-NEXT: vinsertf128 $1, %xmm7, %ymm0, %ymm0
+; GFNIAVX1-NEXT: vinsertf128 $1, %xmm4, %ymm0, %ymm0
; GFNIAVX1-NEXT: retq
;
; GFNIAVX2-LABEL: var_fshr_v32i8:
; GFNIAVX2: # %bb.0:
-; GFNIAVX2-NEXT: vpbroadcastb {{.*#+}} ymm3 = [7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7]
-; GFNIAVX2-NEXT: vpand %ymm3, %ymm2, %ymm4
-; GFNIAVX2-NEXT: vpsllw $5, %ymm4, %ymm4
-; GFNIAVX2-NEXT: vpaddb %ymm4, %ymm4, %ymm5
-; GFNIAVX2-NEXT: vpsrlw $4, %ymm1, %ymm6
-; GFNIAVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm6, %ymm6
-; GFNIAVX2-NEXT: vpblendvb %ymm4, %ymm6, %ymm1, %ymm1
-; GFNIAVX2-NEXT: vpsrlw $2, %ymm1, %ymm4
-; GFNIAVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm4, %ymm4
-; GFNIAVX2-NEXT: vpblendvb %ymm5, %ymm4, %ymm1, %ymm1
-; GFNIAVX2-NEXT: vpsrlw $1, %ymm1, %ymm4
-; GFNIAVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm4, %ymm4
+; GFNIAVX2-NEXT: vpbroadcastq {{.*#+}} ymm3 = [1161999622361579520,1161999622361579520,1161999622361579520,1161999622361579520]
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, %ymm3, %ymm1, %ymm3
+; GFNIAVX2-NEXT: vpbroadcastb {{.*#+}} ymm4 = [7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7]
+; GFNIAVX2-NEXT: vpand %ymm4, %ymm2, %ymm5
+; GFNIAVX2-NEXT: vpsllw $5, %ymm5, %ymm5
+; GFNIAVX2-NEXT: vpblendvb %ymm5, %ymm3, %ymm1, %ymm1
+; GFNIAVX2-NEXT: vpbroadcastq {{.*#+}} ymm3 = [290499906672525312,290499906672525312,290499906672525312,290499906672525312]
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, %ymm3, %ymm1, %ymm3
; GFNIAVX2-NEXT: vpaddb %ymm5, %ymm5, %ymm5
-; GFNIAVX2-NEXT: vpblendvb %ymm5, %ymm4, %ymm1, %ymm1
-; GFNIAVX2-NEXT: vpandn %ymm3, %ymm2, %ymm2
-; GFNIAVX2-NEXT: vpsllw $5, %ymm2, %ymm2
-; GFNIAVX2-NEXT: vpaddb %ymm2, %ymm2, %ymm3
+; GFNIAVX2-NEXT: vpblendvb %ymm5, %ymm3, %ymm1, %ymm1
+; GFNIAVX2-NEXT: vpbroadcastq {{.*#+}} ymm3 = [145249953336295424,145249953336295424,145249953336295424,145249953336295424]
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, %ymm3, %ymm1, %ymm3
+; GFNIAVX2-NEXT: vpaddb %ymm5, %ymm5, %ymm5
+; GFNIAVX2-NEXT: vpblendvb %ymm5, %ymm3, %ymm1, %ymm1
; GFNIAVX2-NEXT: vpaddb %ymm0, %ymm0, %ymm0
-; GFNIAVX2-NEXT: vpsllw $4, %ymm0, %ymm4
-; GFNIAVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm4, %ymm4
-; GFNIAVX2-NEXT: vpblendvb %ymm2, %ymm4, %ymm0, %ymm0
-; GFNIAVX2-NEXT: vpsllw $2, %ymm0, %ymm2
-; GFNIAVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
-; GFNIAVX2-NEXT: vpblendvb %ymm3, %ymm2, %ymm0, %ymm0
-; GFNIAVX2-NEXT: vpaddb %ymm0, %ymm0, %ymm2
-; GFNIAVX2-NEXT: vpaddb %ymm3, %ymm3, %ymm3
-; GFNIAVX2-NEXT: vpblendvb %ymm3, %ymm2, %ymm0, %ymm0
+; GFNIAVX2-NEXT: vpbroadcastq {{.*#+}} ymm3 = [16909320,16909320,16909320,16909320]
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, %ymm3, %ymm0, %ymm3
+; GFNIAVX2-NEXT: vpandn %ymm4, %ymm2, %ymm2
+; GFNIAVX2-NEXT: vpsllw $5, %ymm2, %ymm2
+; GFNIAVX2-NEXT: vpblendvb %ymm2, %ymm3, %ymm0, %ymm0
+; GFNIAVX2-NEXT: vpbroadcastq {{.*#+}} ymm3 = [1108169199648,1108169199648,1108169199648,1108169199648]
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, %ymm3, %ymm0, %ymm3
+; GFNIAVX2-NEXT: vpaddb %ymm2, %ymm2, %ymm2
+; GFNIAVX2-NEXT: vpblendvb %ymm2, %ymm3, %ymm0, %ymm0
+; GFNIAVX2-NEXT: vpaddb %ymm0, %ymm0, %ymm3
+; GFNIAVX2-NEXT: vpaddb %ymm2, %ymm2, %ymm2
+; GFNIAVX2-NEXT: vpblendvb %ymm2, %ymm3, %ymm0, %ymm0
; GFNIAVX2-NEXT: vpor %ymm1, %ymm0, %ymm0
; GFNIAVX2-NEXT: retq
;
@@ -959,25 +916,20 @@ define <32 x i8> @var_fshr_v32i8(<32 x i8> %a, <32 x i8> %b, <32 x i8> %amt) nou
; GFNIAVX512VL-NEXT: vpand %ymm3, %ymm2, %ymm4
; GFNIAVX512VL-NEXT: vpsllw $5, %ymm4, %ymm4
; GFNIAVX512VL-NEXT: vpaddb %ymm4, %ymm4, %ymm5
-; GFNIAVX512VL-NEXT: vpsrlw $4, %ymm1, %ymm6
-; GFNIAVX512VL-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm6, %ymm6
+; GFNIAVX512VL-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm1, %ymm6
; GFNIAVX512VL-NEXT: vpblendvb %ymm4, %ymm6, %ymm1, %ymm1
-; GFNIAVX512VL-NEXT: vpsrlw $2, %ymm1, %ymm4
-; GFNIAVX512VL-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm4, %ymm4
+; GFNIAVX512VL-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm1, %ymm4
; GFNIAVX512VL-NEXT: vpblendvb %ymm5, %ymm4, %ymm1, %ymm1
-; GFNIAVX512VL-NEXT: vpsrlw $1, %ymm1, %ymm4
-; GFNIAVX512VL-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm4, %ymm4
+; GFNIAVX512VL-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm1, %ymm4
; GFNIAVX512VL-NEXT: vpaddb %ymm5, %ymm5, %ymm5
; GFNIAVX512VL-NEXT: vpblendvb %ymm5, %ymm4, %ymm1, %ymm1
; GFNIAVX512VL-NEXT: vpandn %ymm3, %ymm2, %ymm2
; GFNIAVX512VL-NEXT: vpsllw $5, %ymm2, %ymm2
; GFNIAVX512VL-NEXT: vpaddb %ymm2, %ymm2, %ymm3
; GFNIAVX512VL-NEXT: vpaddb %ymm0, %ymm0, %ymm0
-; GFNIAVX512VL-NEXT: vpsllw $4, %ymm0, %ymm4
-; GFNIAVX512VL-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm4, %ymm4
+; GFNIAVX512VL-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %ymm4
; GFNIAVX512VL-NEXT: vpblendvb %ymm2, %ymm4, %ymm0, %ymm0
-; GFNIAVX512VL-NEXT: vpsllw $2, %ymm0, %ymm2
-; GFNIAVX512VL-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm2, %ymm2
+; GFNIAVX512VL-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %ymm2
; GFNIAVX512VL-NEXT: vpblendvb %ymm3, %ymm2, %ymm0, %ymm0
; GFNIAVX512VL-NEXT: vpaddb %ymm0, %ymm0, %ymm2
; GFNIAVX512VL-NEXT: vpaddb %ymm3, %ymm3, %ymm3
@@ -1336,45 +1288,29 @@ define <32 x i8> @constant_fshr_v32i8(<32 x i8> %a, <32 x i8> %b) nounwind {
define <32 x i8> @splatconstant_fshl_v32i8(<32 x i8> %a, <32 x i8> %b) nounwind {
; GFNISSE-LABEL: splatconstant_fshl_v32i8:
; GFNISSE: # %bb.0:
-; GFNISSE-NEXT: psrlw $4, %xmm2
-; GFNISSE-NEXT: movdqa {{.*#+}} xmm4 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240]
-; GFNISSE-NEXT: movdqa %xmm4, %xmm5
-; GFNISSE-NEXT: pandn %xmm2, %xmm5
-; GFNISSE-NEXT: psllw $4, %xmm0
-; GFNISSE-NEXT: pand %xmm4, %xmm0
-; GFNISSE-NEXT: por %xmm5, %xmm0
-; GFNISSE-NEXT: psrlw $4, %xmm3
-; GFNISSE-NEXT: psllw $4, %xmm1
-; GFNISSE-NEXT: pand %xmm4, %xmm1
-; GFNISSE-NEXT: pandn %xmm3, %xmm4
-; GFNISSE-NEXT: por %xmm4, %xmm1
+; GFNISSE-NEXT: movdqa {{.*#+}} xmm4 = [1161999622361579520,1161999622361579520]
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm4, %xmm2
+; GFNISSE-NEXT: pmovsxdq {{.*#+}} xmm5 = [16909320,16909320]
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm5, %xmm0
+; GFNISSE-NEXT: por %xmm2, %xmm0
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm4, %xmm3
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm5, %xmm1
+; GFNISSE-NEXT: por %xmm3, %xmm1
; GFNISSE-NEXT: retq
;
; GFNIAVX1-LABEL: splatconstant_fshl_v32i8:
; GFNIAVX1: # %bb.0:
-; GFNIAVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
-; GFNIAVX1-NEXT: vpsrlw $4, %xmm2, %xmm2
-; GFNIAVX1-NEXT: vbroadcastss {{.*#+}} xmm3 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
-; GFNIAVX1-NEXT: vpand %xmm3, %xmm2, %xmm2
-; GFNIAVX1-NEXT: vpsrlw $4, %xmm1, %xmm1
-; GFNIAVX1-NEXT: vpand %xmm3, %xmm1, %xmm1
-; GFNIAVX1-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1
-; GFNIAVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
-; GFNIAVX1-NEXT: vpsllw $4, %xmm2, %xmm2
-; GFNIAVX1-NEXT: vbroadcastss {{.*#+}} xmm3 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240]
-; GFNIAVX1-NEXT: vpand %xmm3, %xmm2, %xmm2
-; GFNIAVX1-NEXT: vpsllw $4, %xmm0, %xmm0
-; GFNIAVX1-NEXT: vpand %xmm3, %xmm0, %xmm0
-; GFNIAVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; GFNIAVX1-NEXT: vorps %ymm1, %ymm0, %ymm0
; GFNIAVX1-NEXT: retq
;
; GFNIAVX2-LABEL: splatconstant_fshl_v32i8:
; GFNIAVX2: # %bb.0:
-; GFNIAVX2-NEXT: vpsrlw $4, %ymm1, %ymm1
-; GFNIAVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
-; GFNIAVX2-NEXT: vpsllw $4, %ymm0, %ymm0
-; GFNIAVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
+; GFNIAVX2-NEXT: vpbroadcastq {{.*#+}} ymm2 = [1161999622361579520,1161999622361579520,1161999622361579520,1161999622361579520]
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, %ymm2, %ymm1, %ymm1
+; GFNIAVX2-NEXT: vpbroadcastq {{.*#+}} ymm2 = [16909320,16909320,16909320,16909320]
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, %ymm2, %ymm0, %ymm0
; GFNIAVX2-NEXT: vpor %ymm1, %ymm0, %ymm0
; GFNIAVX2-NEXT: retq
;
@@ -1392,45 +1328,29 @@ declare <32 x i8> @llvm.fshl.v32i8(<32 x i8>, <32 x i8>, <32 x i8>)
define <32 x i8> @splatconstant_fshr_v32i8(<32 x i8> %a, <32 x i8> %b) nounwind {
; GFNISSE-LABEL: splatconstant_fshr_v32i8:
; GFNISSE: # %bb.0:
-; GFNISSE-NEXT: psrlw $6, %xmm2
-; GFNISSE-NEXT: movdqa {{.*#+}} xmm4 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252]
-; GFNISSE-NEXT: movdqa %xmm4, %xmm5
-; GFNISSE-NEXT: pandn %xmm2, %xmm5
-; GFNISSE-NEXT: psllw $2, %xmm0
-; GFNISSE-NEXT: pand %xmm4, %xmm0
-; GFNISSE-NEXT: por %xmm5, %xmm0
-; GFNISSE-NEXT: psrlw $6, %xmm3
-; GFNISSE-NEXT: psllw $2, %xmm1
-; GFNISSE-NEXT: pand %xmm4, %xmm1
-; GFNISSE-NEXT: pandn %xmm3, %xmm4
-; GFNISSE-NEXT: por %xmm4, %xmm1
+; GFNISSE-NEXT: movdqa {{.*#+}} xmm4 = [4647714815446351872,4647714815446351872]
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm4, %xmm2
+; GFNISSE-NEXT: movdqa {{.*#+}} xmm5 = [1108169199648,1108169199648]
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm5, %xmm0
+; GFNISSE-NEXT: por %xmm2, %xmm0
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm4, %xmm3
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm5, %xmm1
+; GFNISSE-NEXT: por %xmm3, %xmm1
; GFNISSE-NEXT: retq
;
; GFNIAVX1-LABEL: splatconstant_fshr_v32i8:
; GFNIAVX1: # %bb.0:
-; GFNIAVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
-; GFNIAVX1-NEXT: vpsrlw $6, %xmm2, %xmm2
-; GFNIAVX1-NEXT: vbroadcastss {{.*#+}} xmm3 = [3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3]
-; GFNIAVX1-NEXT: vpand %xmm3, %xmm2, %xmm2
-; GFNIAVX1-NEXT: vpsrlw $6, %xmm1, %xmm1
-; GFNIAVX1-NEXT: vpand %xmm3, %xmm1, %xmm1
-; GFNIAVX1-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1
-; GFNIAVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
-; GFNIAVX1-NEXT: vpsllw $2, %xmm2, %xmm2
-; GFNIAVX1-NEXT: vbroadcastss {{.*#+}} xmm3 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252]
-; GFNIAVX1-NEXT: vpand %xmm3, %xmm2, %xmm2
-; GFNIAVX1-NEXT: vpsllw $2, %xmm0, %xmm0
-; GFNIAVX1-NEXT: vpand %xmm3, %xmm0, %xmm0
-; GFNIAVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; GFNIAVX1-NEXT: vorps %ymm1, %ymm0, %ymm0
; GFNIAVX1-NEXT: retq
;
; GFNIAVX2-LABEL: splatconstant_fshr_v32i8:
; GFNIAVX2: # %bb.0:
-; GFNIAVX2-NEXT: vpsrlw $6, %ymm1, %ymm1
-; GFNIAVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
-; GFNIAVX2-NEXT: vpsllw $2, %ymm0, %ymm0
-; GFNIAVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
+; GFNIAVX2-NEXT: vpbroadcastq {{.*#+}} ymm2 = [4647714815446351872,4647714815446351872,4647714815446351872,4647714815446351872]
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, %ymm2, %ymm1, %ymm1
+; GFNIAVX2-NEXT: vpbroadcastq {{.*#+}} ymm2 = [1108169199648,1108169199648,1108169199648,1108169199648]
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, %ymm2, %ymm0, %ymm0
; GFNIAVX2-NEXT: vpor %ymm1, %ymm0, %ymm0
; GFNIAVX2-NEXT: retq
;
@@ -1766,63 +1686,51 @@ define <64 x i8> @var_fshl_v64i8(<64 x i8> %a, <64 x i8> %b, <64 x i8> %amt) nou
; GFNIAVX512VL-LABEL: var_fshl_v64i8:
; GFNIAVX512VL: # %bb.0:
; GFNIAVX512VL-NEXT: vextracti64x4 $1, %zmm1, %ymm3
-; GFNIAVX512VL-NEXT: vpsrlw $1, %ymm3, %ymm3
-; GFNIAVX512VL-NEXT: vpbroadcastd {{.*#+}} ymm4 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127]
-; GFNIAVX512VL-NEXT: vpand %ymm4, %ymm3, %ymm5
-; GFNIAVX512VL-NEXT: vpsrlw $4, %ymm5, %ymm3
-; GFNIAVX512VL-NEXT: vpbroadcastd {{.*#+}} ymm6 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
-; GFNIAVX512VL-NEXT: vpand %ymm6, %ymm3, %ymm7
-; GFNIAVX512VL-NEXT: vpbroadcastd {{.*#+}} zmm8 = [7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7]
-; GFNIAVX512VL-NEXT: vpandq %zmm8, %zmm2, %zmm2
-; GFNIAVX512VL-NEXT: vextracti64x4 $1, %zmm2, %ymm3
-; GFNIAVX512VL-NEXT: vpxor %ymm3, %ymm8, %ymm9
+; GFNIAVX512VL-NEXT: vpbroadcastq {{.*#+}} ymm4 = [145249953336295424,145249953336295424,145249953336295424,145249953336295424]
+; GFNIAVX512VL-NEXT: vgf2p8affineqb $0, %ymm4, %ymm3, %ymm3
+; GFNIAVX512VL-NEXT: vpbroadcastq {{.*#+}} ymm5 = [1161999622361579520,1161999622361579520,1161999622361579520,1161999622361579520]
+; GFNIAVX512VL-NEXT: vgf2p8affineqb $0, %ymm5, %ymm3, %ymm6
+; GFNIAVX512VL-NEXT: vpbroadcastd {{.*#+}} zmm7 = [7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7]
+; GFNIAVX512VL-NEXT: vpandq %zmm7, %zmm2, %zmm2
+; GFNIAVX512VL-NEXT: vextracti64x4 $1, %zmm2, %ymm8
+; GFNIAVX512VL-NEXT: vpxor %ymm7, %ymm8, %ymm9
; GFNIAVX512VL-NEXT: vpsllw $5, %ymm9, %ymm9
-; GFNIAVX512VL-NEXT: vpblendvb %ymm9, %ymm7, %ymm5, %ymm5
-; GFNIAVX512VL-NEXT: vpsrlw $2, %ymm5, %ymm7
-; GFNIAVX512VL-NEXT: vpbroadcastd {{.*#+}} ymm10 = [63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63]
-; GFNIAVX512VL-NEXT: vpand %ymm7, %ymm10, %ymm7
+; GFNIAVX512VL-NEXT: vpblendvb %ymm9, %ymm6, %ymm3, %ymm3
+; GFNIAVX512VL-NEXT: vpbroadcastq {{.*#+}} ymm6 = [290499906672525312,290499906672525312,290499906672525312,290499906672525312]
+; GFNIAVX512VL-NEXT: vgf2p8affineqb $0, %ymm6, %ymm3, %ymm10
; GFNIAVX512VL-NEXT: vpaddb %ymm9, %ymm9, %ymm9
-; GFNIAVX512VL-NEXT: vpblendvb %ymm9, %ymm7, %ymm5, %ymm5
-; GFNIAVX512VL-NEXT: vpsrlw $1, %ymm5, %ymm7
-; GFNIAVX512VL-NEXT: vpand %ymm4, %ymm7, %ymm7
+; GFNIAVX512VL-NEXT: vpblendvb %ymm9, %ymm10, %ymm3, %ymm3
+; GFNIAVX512VL-NEXT: vgf2p8affineqb $0, %ymm4, %ymm3, %ymm10
; GFNIAVX512VL-NEXT: vpaddb %ymm9, %ymm9, %ymm9
-; GFNIAVX512VL-NEXT: vpblendvb %ymm9, %ymm7, %ymm5, %ymm5
-; GFNIAVX512VL-NEXT: vpsrlw $1, %ymm1, %ymm1
-; GFNIAVX512VL-NEXT: vpand %ymm4, %ymm1, %ymm1
-; GFNIAVX512VL-NEXT: vpsrlw $4, %ymm1, %ymm7
-; GFNIAVX512VL-NEXT: vpand %ymm6, %ymm7, %ymm6
-; GFNIAVX512VL-NEXT: vpxor %ymm2, %ymm8, %ymm7
+; GFNIAVX512VL-NEXT: vpblendvb %ymm9, %ymm10, %ymm3, %ymm3
+; GFNIAVX512VL-NEXT: vgf2p8affineqb $0, %ymm4, %ymm1, %ymm1
+; GFNIAVX512VL-NEXT: vgf2p8affineqb $0, %ymm5, %ymm1, %ymm5
+; GFNIAVX512VL-NEXT: vpxor %ymm7, %ymm2, %ymm7
; GFNIAVX512VL-NEXT: vpsllw $5, %ymm7, %ymm7
-; GFNIAVX512VL-NEXT: vpblendvb %ymm7, %ymm6, %ymm1, %ymm1
-; GFNIAVX512VL-NEXT: vpsrlw $2, %ymm1, %ymm6
-; GFNIAVX512VL-NEXT: vpand %ymm6, %ymm10, %ymm6
-; GFNIAVX512VL-NEXT: vpaddb %ymm7, %ymm7, %ymm7
-; GFNIAVX512VL-NEXT: vpblendvb %ymm7, %ymm6, %ymm1, %ymm1
-; GFNIAVX512VL-NEXT: vpsrlw $1, %ymm1, %ymm6
-; GFNIAVX512VL-NEXT: vpand %ymm4, %ymm6, %ymm4
+; GFNIAVX512VL-NEXT: vpblendvb %ymm7, %ymm5, %ymm1, %ymm1
+; GFNIAVX512VL-NEXT: vgf2p8affineqb $0, %ymm6, %ymm1, %ymm5
; GFNIAVX512VL-NEXT: vpaddb %ymm7, %ymm7, %ymm6
-; GFNIAVX512VL-NEXT: vpblendvb %ymm6, %ymm4, %ymm1, %ymm1
-; GFNIAVX512VL-NEXT: vinserti64x4 $1, %ymm5, %zmm1, %zmm1
-; GFNIAVX512VL-NEXT: vextracti64x4 $1, %zmm0, %ymm4
-; GFNIAVX512VL-NEXT: vpsllw $4, %ymm4, %ymm5
-; GFNIAVX512VL-NEXT: vpbroadcastd {{.*#+}} ymm6 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240]
-; GFNIAVX512VL-NEXT: vpand %ymm6, %ymm5, %ymm5
-; GFNIAVX512VL-NEXT: vpsllw $5, %ymm3, %ymm3
-; GFNIAVX512VL-NEXT: vpblendvb %ymm3, %ymm5, %ymm4, %ymm4
-; GFNIAVX512VL-NEXT: vpsllw $2, %ymm4, %ymm5
-; GFNIAVX512VL-NEXT: vpbroadcastd {{.*#+}} ymm7 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252]
-; GFNIAVX512VL-NEXT: vpand %ymm7, %ymm5, %ymm5
-; GFNIAVX512VL-NEXT: vpaddb %ymm3, %ymm3, %ymm3
-; GFNIAVX512VL-NEXT: vpblendvb %ymm3, %ymm5, %ymm4, %ymm4
-; GFNIAVX512VL-NEXT: vpaddb %ymm4, %ymm4, %ymm5
-; GFNIAVX512VL-NEXT: vpaddb %ymm3, %ymm3, %ymm3
-; GFNIAVX512VL-NEXT: vpblendvb %ymm3, %ymm5, %ymm4, %ymm3
-; GFNIAVX512VL-NEXT: vpsllw $4, %ymm0, %ymm4
-; GFNIAVX512VL-NEXT: vpand %ymm6, %ymm4, %ymm4
+; GFNIAVX512VL-NEXT: vpblendvb %ymm6, %ymm5, %ymm1, %ymm1
+; GFNIAVX512VL-NEXT: vgf2p8affineqb $0, %ymm4, %ymm1, %ymm4
+; GFNIAVX512VL-NEXT: vpaddb %ymm6, %ymm6, %ymm5
+; GFNIAVX512VL-NEXT: vpblendvb %ymm5, %ymm4, %ymm1, %ymm1
+; GFNIAVX512VL-NEXT: vinserti64x4 $1, %ymm3, %zmm1, %zmm1
+; GFNIAVX512VL-NEXT: vextracti64x4 $1, %zmm0, %ymm3
+; GFNIAVX512VL-NEXT: vpbroadcastq {{.*#+}} ymm4 = [16909320,16909320,16909320,16909320]
+; GFNIAVX512VL-NEXT: vgf2p8affineqb $0, %ymm4, %ymm3, %ymm5
+; GFNIAVX512VL-NEXT: vpsllw $5, %ymm8, %ymm6
+; GFNIAVX512VL-NEXT: vpblendvb %ymm6, %ymm5, %ymm3, %ymm3
+; GFNIAVX512VL-NEXT: vpbroadcastq {{.*#+}} ymm5 = [1108169199648,1108169199648,1108169199648,1108169199648]
+; GFNIAVX512VL-NEXT: vgf2p8affineqb $0, %ymm5, %ymm3, %ymm7
+; GFNIAVX512VL-NEXT: vpaddb %ymm6, %ymm6, %ymm6
+; GFNIAVX512VL-NEXT: vpblendvb %ymm6, %ymm7, %ymm3, %ymm3
+; GFNIAVX512VL-NEXT: vpaddb %ymm3, %ymm3, %ymm7
+; GFNIAVX512VL-NEXT: vpaddb %ymm6, %ymm6, %ymm6
+; GFNIAVX512VL-NEXT: vpblendvb %ymm6, %ymm7, %ymm3, %ymm3
+; GFNIAVX512VL-NEXT: vgf2p8affineqb $0, %ymm4, %ymm0, %ymm4
; GFNIAVX512VL-NEXT: vpsllw $5, %ymm2, %ymm2
; GFNIAVX512VL-NEXT: vpblendvb %ymm2, %ymm4, %ymm0, %ymm0
-; GFNIAVX512VL-NEXT: vpsllw $2, %ymm0, %ymm4
-; GFNIAVX512VL-NEXT: vpand %ymm7, %ymm4, %ymm4
+; GFNIAVX512VL-NEXT: vgf2p8affineqb $0, %ymm5, %ymm0, %ymm4
; GFNIAVX512VL-NEXT: vpaddb %ymm2, %ymm2, %ymm2
; GFNIAVX512VL-NEXT: vpblendvb %ymm2, %ymm4, %ymm0, %ymm0
; GFNIAVX512VL-NEXT: vpaddb %ymm0, %ymm0, %ymm4
@@ -1863,35 +1771,30 @@ define <64 x i8> @var_fshr_v64i8(<64 x i8> %a, <64 x i8> %b, <64 x i8> %amt) nou
; GFNISSE-NEXT: movdqa %xmm0, %xmm1
; GFNISSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm9
; GFNISSE-NEXT: movdqa %xmm5, %xmm12
-; GFNISSE-NEXT: psrlw $4, %xmm12
-; GFNISSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm12
+; GFNISSE-NEXT: gf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm12
; GFNISSE-NEXT: movdqa {{.*#+}} xmm11 = [7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7]
; GFNISSE-NEXT: movdqa %xmm9, %xmm0
; GFNISSE-NEXT: pand %xmm11, %xmm0
; GFNISSE-NEXT: psllw $5, %xmm0
; GFNISSE-NEXT: pblendvb %xmm0, %xmm12, %xmm5
; GFNISSE-NEXT: movdqa %xmm5, %xmm13
-; GFNISSE-NEXT: psrlw $2, %xmm13
-; GFNISSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm13
+; GFNISSE-NEXT: gf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm13
; GFNISSE-NEXT: paddb %xmm0, %xmm0
; GFNISSE-NEXT: pblendvb %xmm0, %xmm13, %xmm5
; GFNISSE-NEXT: movdqa %xmm5, %xmm14
-; GFNISSE-NEXT: psrlw $1, %xmm14
-; GFNISSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm14
+; GFNISSE-NEXT: gf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm14
; GFNISSE-NEXT: paddb %xmm0, %xmm0
; GFNISSE-NEXT: pblendvb %xmm0, %xmm14, %xmm5
; GFNISSE-NEXT: paddb %xmm1, %xmm1
; GFNISSE-NEXT: movdqa %xmm1, %xmm15
-; GFNISSE-NEXT: psllw $4, %xmm15
-; GFNISSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm15
+; GFNISSE-NEXT: gf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm15
; GFNISSE-NEXT: movdqa %xmm11, %xmm12
; GFNISSE-NEXT: pandn %xmm11, %xmm9
; GFNISSE-NEXT: psllw $5, %xmm9
; GFNISSE-NEXT: movdqa %xmm9, %xmm0
; GFNISSE-NEXT: pblendvb %xmm0, %xmm15, %xmm1
; GFNISSE-NEXT: movdqa %xmm1, %xmm8
-; GFNISSE-NEXT: psllw $2, %xmm8
-; GFNISSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm8
+; GFNISSE-NEXT: gf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm8
; GFNISSE-NEXT: paddb %xmm9, %xmm9
; GFNISSE-NEXT: movdqa %xmm9, %xmm0
; GFNISSE-NEXT: pblendvb %xmm0, %xmm8, %xmm1
@@ -1902,38 +1805,33 @@ define <64 x i8> @var_fshr_v64i8(<64 x i8> %a, <64 x i8> %b, <64 x i8> %amt) nou
; GFNISSE-NEXT: pblendvb %xmm0, %xmm8, %xmm1
; GFNISSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm9
; GFNISSE-NEXT: movdqa %xmm6, %xmm8
-; GFNISSE-NEXT: psrlw $4, %xmm8
-; GFNISSE-NEXT: movdqa {{.*#+}} xmm11 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
-; GFNISSE-NEXT: pand %xmm11, %xmm8
+; GFNISSE-NEXT: movdqa {{.*#+}} xmm11 = [1161999622361579520,1161999622361579520]
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm11, %xmm8
; GFNISSE-NEXT: movdqa %xmm9, %xmm0
; GFNISSE-NEXT: pand %xmm12, %xmm0
; GFNISSE-NEXT: psllw $5, %xmm0
; GFNISSE-NEXT: pblendvb %xmm0, %xmm8, %xmm6
; GFNISSE-NEXT: movdqa %xmm6, %xmm8
-; GFNISSE-NEXT: psrlw $2, %xmm8
-; GFNISSE-NEXT: movdqa {{.*#+}} xmm13 = [63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63]
-; GFNISSE-NEXT: pand %xmm13, %xmm8
+; GFNISSE-NEXT: movdqa {{.*#+}} xmm13 = [290499906672525312,290499906672525312]
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm13, %xmm8
; GFNISSE-NEXT: paddb %xmm0, %xmm0
; GFNISSE-NEXT: pblendvb %xmm0, %xmm8, %xmm6
; GFNISSE-NEXT: movdqa %xmm6, %xmm8
-; GFNISSE-NEXT: psrlw $1, %xmm8
-; GFNISSE-NEXT: movdqa {{.*#+}} xmm14 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127]
-; GFNISSE-NEXT: pand %xmm14, %xmm8
+; GFNISSE-NEXT: movdqa {{.*#+}} xmm14 = [145249953336295424,145249953336295424]
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm14, %xmm8
; GFNISSE-NEXT: paddb %xmm0, %xmm0
; GFNISSE-NEXT: pblendvb %xmm0, %xmm8, %xmm6
; GFNISSE-NEXT: paddb %xmm2, %xmm2
; GFNISSE-NEXT: movdqa %xmm2, %xmm8
-; GFNISSE-NEXT: psllw $4, %xmm8
-; GFNISSE-NEXT: movdqa {{.*#+}} xmm15 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240]
-; GFNISSE-NEXT: pand %xmm15, %xmm8
+; GFNISSE-NEXT: pmovsxdq {{.*#+}} xmm15 = [16909320,16909320]
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm15, %xmm8
; GFNISSE-NEXT: pandn %xmm12, %xmm9
; GFNISSE-NEXT: psllw $5, %xmm9
; GFNISSE-NEXT: movdqa %xmm9, %xmm0
; GFNISSE-NEXT: pblendvb %xmm0, %xmm8, %xmm2
; GFNISSE-NEXT: movdqa %xmm2, %xmm8
-; GFNISSE-NEXT: psllw $2, %xmm8
-; GFNISSE-NEXT: movdqa {{.*#+}} xmm0 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252]
-; GFNISSE-NEXT: pand %xmm0, %xmm8
+; GFNISSE-NEXT: movdqa {{.*#+}} xmm0 = [1108169199648,1108169199648]
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm0, %xmm8
; GFNISSE-NEXT: paddb %xmm9, %xmm9
; GFNISSE-NEXT: movdqa %xmm9, %xmm0
; GFNISSE-NEXT: pblendvb %xmm0, %xmm8, %xmm2
@@ -1944,33 +1842,28 @@ define <64 x i8> @var_fshr_v64i8(<64 x i8> %a, <64 x i8> %b, <64 x i8> %amt) nou
; GFNISSE-NEXT: pblendvb %xmm0, %xmm8, %xmm2
; GFNISSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm9
; GFNISSE-NEXT: movdqa %xmm7, %xmm8
-; GFNISSE-NEXT: psrlw $4, %xmm8
-; GFNISSE-NEXT: pand %xmm11, %xmm8
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm11, %xmm8
; GFNISSE-NEXT: movdqa %xmm9, %xmm0
; GFNISSE-NEXT: pand %xmm12, %xmm0
; GFNISSE-NEXT: psllw $5, %xmm0
; GFNISSE-NEXT: pblendvb %xmm0, %xmm8, %xmm7
; GFNISSE-NEXT: movdqa %xmm7, %xmm8
-; GFNISSE-NEXT: psrlw $2, %xmm8
-; GFNISSE-NEXT: pand %xmm13, %xmm8
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm13, %xmm8
; GFNISSE-NEXT: paddb %xmm0, %xmm0
; GFNISSE-NEXT: pblendvb %xmm0, %xmm8, %xmm7
; GFNISSE-NEXT: movdqa %xmm7, %xmm8
-; GFNISSE-NEXT: psrlw $1, %xmm8
-; GFNISSE-NEXT: pand %xmm14, %xmm8
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm14, %xmm8
; GFNISSE-NEXT: paddb %xmm0, %xmm0
; GFNISSE-NEXT: pblendvb %xmm0, %xmm8, %xmm7
; GFNISSE-NEXT: paddb %xmm3, %xmm3
; GFNISSE-NEXT: movdqa %xmm3, %xmm8
-; GFNISSE-NEXT: psllw $4, %xmm8
-; GFNISSE-NEXT: pand %xmm15, %xmm8
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm15, %xmm8
; GFNISSE-NEXT: pandn %xmm12, %xmm9
; GFNISSE-NEXT: psllw $5, %xmm9
; GFNISSE-NEXT: movdqa %xmm9, %xmm0
; GFNISSE-NEXT: pblendvb %xmm0, %xmm8, %xmm3
; GFNISSE-NEXT: movdqa %xmm3, %xmm8
-; GFNISSE-NEXT: psllw $2, %xmm8
-; GFNISSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm8
+; GFNISSE-NEXT: gf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm8
; GFNISSE-NEXT: paddb %xmm9, %xmm9
; GFNISSE-NEXT: movdqa %xmm9, %xmm0
; GFNISSE-NEXT: pblendvb %xmm0, %xmm8, %xmm3
@@ -1981,33 +1874,28 @@ define <64 x i8> @var_fshr_v64i8(<64 x i8> %a, <64 x i8> %b, <64 x i8> %amt) nou
; GFNISSE-NEXT: pblendvb %xmm0, %xmm8, %xmm3
; GFNISSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm9
; GFNISSE-NEXT: movdqa %xmm10, %xmm8
-; GFNISSE-NEXT: psrlw $4, %xmm8
-; GFNISSE-NEXT: pand %xmm11, %xmm8
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm11, %xmm8
; GFNISSE-NEXT: movdqa %xmm9, %xmm0
; GFNISSE-NEXT: pand %xmm12, %xmm0
; GFNISSE-NEXT: psllw $5, %xmm0
; GFNISSE-NEXT: pblendvb %xmm0, %xmm8, %xmm10
; GFNISSE-NEXT: movdqa %xmm10, %xmm8
-; GFNISSE-NEXT: psrlw $2, %xmm8
-; GFNISSE-NEXT: pand %xmm13, %xmm8
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm13, %xmm8
; GFNISSE-NEXT: paddb %xmm0, %xmm0
; GFNISSE-NEXT: pblendvb %xmm0, %xmm8, %xmm10
; GFNISSE-NEXT: movdqa %xmm10, %xmm8
-; GFNISSE-NEXT: psrlw $1, %xmm8
-; GFNISSE-NEXT: pand %xmm14, %xmm8
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm14, %xmm8
; GFNISSE-NEXT: paddb %xmm0, %xmm0
; GFNISSE-NEXT: pblendvb %xmm0, %xmm8, %xmm10
; GFNISSE-NEXT: paddb %xmm4, %xmm4
; GFNISSE-NEXT: movdqa %xmm4, %xmm8
-; GFNISSE-NEXT: psllw $4, %xmm8
-; GFNISSE-NEXT: pand %xmm15, %xmm8
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm15, %xmm8
; GFNISSE-NEXT: pandn %xmm12, %xmm9
; GFNISSE-NEXT: psllw $5, %xmm9
; GFNISSE-NEXT: movdqa %xmm9, %xmm0
; GFNISSE-NEXT: pblendvb %xmm0, %xmm8, %xmm4
; GFNISSE-NEXT: movdqa %xmm4, %xmm8
-; GFNISSE-NEXT: psllw $2, %xmm8
-; GFNISSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm8
+; GFNISSE-NEXT: gf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm8
; GFNISSE-NEXT: paddb %xmm9, %xmm9
; GFNISSE-NEXT: movdqa %xmm9, %xmm0
; GFNISSE-NEXT: pblendvb %xmm0, %xmm8, %xmm4
@@ -2029,61 +1917,56 @@ define <64 x i8> @var_fshr_v64i8(<64 x i8> %a, <64 x i8> %b, <64 x i8> %amt) nou
; GFNIAVX1-LABEL: var_fshr_v64i8:
; GFNIAVX1: # %bb.0:
; GFNIAVX1-NEXT: vextractf128 $1, %ymm2, %xmm8
-; GFNIAVX1-NEXT: vpsrlw $4, %xmm8, %xmm6
-; GFNIAVX1-NEXT: vbroadcastss {{.*#+}} xmm7 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
-; GFNIAVX1-NEXT: vpand %xmm7, %xmm6, %xmm9
+; GFNIAVX1-NEXT: vmovddup {{.*#+}} xmm7 = [1161999622361579520,1161999622361579520]
+; GFNIAVX1-NEXT: # xmm7 = mem[0,0]
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm7, %xmm8, %xmm9
; GFNIAVX1-NEXT: vbroadcastss {{.*#+}} ymm6 = [7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7]
; GFNIAVX1-NEXT: vandps %ymm6, %ymm4, %ymm11
; GFNIAVX1-NEXT: vextractf128 $1, %ymm11, %xmm10
; GFNIAVX1-NEXT: vpsllw $5, %xmm10, %xmm12
; GFNIAVX1-NEXT: vpblendvb %xmm12, %xmm9, %xmm8, %xmm8
-; GFNIAVX1-NEXT: vpsrlw $2, %xmm8, %xmm9
-; GFNIAVX1-NEXT: vbroadcastss {{.*#+}} xmm4 = [63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63]
-; GFNIAVX1-NEXT: vpand %xmm4, %xmm9, %xmm9
+; GFNIAVX1-NEXT: vmovddup {{.*#+}} xmm4 = [290499906672525312,290499906672525312]
+; GFNIAVX1-NEXT: # xmm4 = mem[0,0]
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm4, %xmm8, %xmm9
; GFNIAVX1-NEXT: vpaddb %xmm12, %xmm12, %xmm12
; GFNIAVX1-NEXT: vpblendvb %xmm12, %xmm9, %xmm8, %xmm9
-; GFNIAVX1-NEXT: vpsrlw $1, %xmm9, %xmm13
-; GFNIAVX1-NEXT: vbroadcastss {{.*#+}} xmm8 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127]
-; GFNIAVX1-NEXT: vpand %xmm8, %xmm13, %xmm13
+; GFNIAVX1-NEXT: vmovddup {{.*#+}} xmm8 = [145249953336295424,145249953336295424]
+; GFNIAVX1-NEXT: # xmm8 = mem[0,0]
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm8, %xmm9, %xmm13
; GFNIAVX1-NEXT: vpaddb %xmm12, %xmm12, %xmm12
; GFNIAVX1-NEXT: vpblendvb %xmm12, %xmm13, %xmm9, %xmm12
; GFNIAVX1-NEXT: vextractf128 $1, %ymm0, %xmm9
; GFNIAVX1-NEXT: vpaddb %xmm9, %xmm9, %xmm13
-; GFNIAVX1-NEXT: vpsllw $4, %xmm13, %xmm14
-; GFNIAVX1-NEXT: vbroadcastss {{.*#+}} xmm9 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240]
-; GFNIAVX1-NEXT: vpand %xmm9, %xmm14, %xmm14
+; GFNIAVX1-NEXT: vmovddup {{.*#+}} xmm9 = [16909320,16909320]
+; GFNIAVX1-NEXT: # xmm9 = mem[0,0]
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm9, %xmm13, %xmm14
; GFNIAVX1-NEXT: vpxor %xmm6, %xmm10, %xmm10
; GFNIAVX1-NEXT: vpsllw $5, %xmm10, %xmm15
; GFNIAVX1-NEXT: vpblendvb %xmm15, %xmm14, %xmm13, %xmm13
-; GFNIAVX1-NEXT: vpsllw $2, %xmm13, %xmm14
-; GFNIAVX1-NEXT: vbroadcastss {{.*#+}} xmm10 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252]
-; GFNIAVX1-NEXT: vpand %xmm10, %xmm14, %xmm14
+; GFNIAVX1-NEXT: vmovddup {{.*#+}} xmm10 = [1108169199648,1108169199648]
+; GFNIAVX1-NEXT: # xmm10 = mem[0,0]
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm10, %xmm13, %xmm14
; GFNIAVX1-NEXT: vpaddb %xmm15, %xmm15, %xmm15
; GFNIAVX1-NEXT: vpblendvb %xmm15, %xmm14, %xmm13, %xmm13
; GFNIAVX1-NEXT: vpaddb %xmm13, %xmm13, %xmm14
; GFNIAVX1-NEXT: vpaddb %xmm15, %xmm15, %xmm15
; GFNIAVX1-NEXT: vpblendvb %xmm15, %xmm14, %xmm13, %xmm13
; GFNIAVX1-NEXT: vpor %xmm12, %xmm13, %xmm12
-; GFNIAVX1-NEXT: vpsrlw $4, %xmm2, %xmm13
-; GFNIAVX1-NEXT: vpand %xmm7, %xmm13, %xmm13
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm7, %xmm2, %xmm13
; GFNIAVX1-NEXT: vpsllw $5, %xmm11, %xmm14
; GFNIAVX1-NEXT: vpblendvb %xmm14, %xmm13, %xmm2, %xmm2
-; GFNIAVX1-NEXT: vpsrlw $2, %xmm2, %xmm13
-; GFNIAVX1-NEXT: vpand %xmm4, %xmm13, %xmm13
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm4, %xmm2, %xmm13
; GFNIAVX1-NEXT: vpaddb %xmm14, %xmm14, %xmm14
; GFNIAVX1-NEXT: vpblendvb %xmm14, %xmm13, %xmm2, %xmm2
-; GFNIAVX1-NEXT: vpsrlw $1, %xmm2, %xmm13
-; GFNIAVX1-NEXT: vpand %xmm8, %xmm13, %xmm13
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm8, %xmm2, %xmm13
; GFNIAVX1-NEXT: vpaddb %xmm14, %xmm14, %xmm14
; GFNIAVX1-NEXT: vpblendvb %xmm14, %xmm13, %xmm2, %xmm2
; GFNIAVX1-NEXT: vpaddb %xmm0, %xmm0, %xmm0
-; GFNIAVX1-NEXT: vpsllw $4, %xmm0, %xmm13
-; GFNIAVX1-NEXT: vpand %xmm9, %xmm13, %xmm13
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm9, %xmm0, %xmm13
; GFNIAVX1-NEXT: vpxor %xmm6, %xmm11, %xmm11
; GFNIAVX1-NEXT: vpsllw $5, %xmm11, %xmm11
; GFNIAVX1-NEXT: vpblendvb %xmm11, %xmm13, %xmm0, %xmm0
-; GFNIAVX1-NEXT: vpsllw $2, %xmm0, %xmm13
-; GFNIAVX1-NEXT: vpand %xmm10, %xmm13, %xmm13
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm10, %xmm0, %xmm13
; GFNIAVX1-NEXT: vpaddb %xmm11, %xmm11, %xmm11
; GFNIAVX1-NEXT: vpblendvb %xmm11, %xmm13, %xmm0, %xmm0
; GFNIAVX1-NEXT: vpaddb %xmm0, %xmm0, %xmm13
@@ -2092,55 +1975,45 @@ define <64 x i8> @var_fshr_v64i8(<64 x i8> %a, <64 x i8> %b, <64 x i8> %amt) nou
; GFNIAVX1-NEXT: vpor %xmm2, %xmm0, %xmm0
; GFNIAVX1-NEXT: vinsertf128 $1, %xmm12, %ymm0, %ymm0
; GFNIAVX1-NEXT: vextractf128 $1, %ymm3, %xmm11
-; GFNIAVX1-NEXT: vpsrlw $4, %xmm11, %xmm2
-; GFNIAVX1-NEXT: vpand %xmm7, %xmm2, %xmm12
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm7, %xmm11, %xmm12
; GFNIAVX1-NEXT: vandps %ymm6, %ymm5, %ymm2
; GFNIAVX1-NEXT: vextractf128 $1, %ymm2, %xmm5
; GFNIAVX1-NEXT: vpsllw $5, %xmm5, %xmm13
; GFNIAVX1-NEXT: vpblendvb %xmm13, %xmm12, %xmm11, %xmm11
-; GFNIAVX1-NEXT: vpsrlw $2, %xmm11, %xmm12
-; GFNIAVX1-NEXT: vpand %xmm4, %xmm12, %xmm12
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm4, %xmm11, %xmm12
; GFNIAVX1-NEXT: vpaddb %xmm13, %xmm13, %xmm13
; GFNIAVX1-NEXT: vpblendvb %xmm13, %xmm12, %xmm11, %xmm11
-; GFNIAVX1-NEXT: vpsrlw $1, %xmm11, %xmm12
-; GFNIAVX1-NEXT: vpand %xmm8, %xmm12, %xmm12
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm8, %xmm11, %xmm12
; GFNIAVX1-NEXT: vpaddb %xmm13, %xmm13, %xmm13
; GFNIAVX1-NEXT: vpblendvb %xmm13, %xmm12, %xmm11, %xmm11
; GFNIAVX1-NEXT: vextractf128 $1, %ymm1, %xmm12
; GFNIAVX1-NEXT: vpaddb %xmm12, %xmm12, %xmm12
-; GFNIAVX1-NEXT: vpsllw $4, %xmm12, %xmm13
-; GFNIAVX1-NEXT: vpand %xmm9, %xmm13, %xmm13
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm9, %xmm12, %xmm13
; GFNIAVX1-NEXT: vpxor %xmm6, %xmm5, %xmm5
; GFNIAVX1-NEXT: vpsllw $5, %xmm5, %xmm5
; GFNIAVX1-NEXT: vpblendvb %xmm5, %xmm13, %xmm12, %xmm12
-; GFNIAVX1-NEXT: vpsllw $2, %xmm12, %xmm13
-; GFNIAVX1-NEXT: vpand %xmm10, %xmm13, %xmm13
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm10, %xmm12, %xmm13
; GFNIAVX1-NEXT: vpaddb %xmm5, %xmm5, %xmm5
; GFNIAVX1-NEXT: vpblendvb %xmm5, %xmm13, %xmm12, %xmm12
; GFNIAVX1-NEXT: vpaddb %xmm12, %xmm12, %xmm13
; GFNIAVX1-NEXT: vpaddb %xmm5, %xmm5, %xmm5
; GFNIAVX1-NEXT: vpblendvb %xmm5, %xmm13, %xmm12, %xmm5
; GFNIAVX1-NEXT: vpor %xmm5, %xmm11, %xmm5
-; GFNIAVX1-NEXT: vpsrlw $4, %xmm3, %xmm11
-; GFNIAVX1-NEXT: vpand %xmm7, %xmm11, %xmm7
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm7, %xmm3, %xmm7
; GFNIAVX1-NEXT: vpsllw $5, %xmm2, %xmm11
; GFNIAVX1-NEXT: vpblendvb %xmm11, %xmm7, %xmm3, %xmm3
-; GFNIAVX1-NEXT: vpsrlw $2, %xmm3, %xmm7
-; GFNIAVX1-NEXT: vpand %xmm4, %xmm7, %xmm4
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm4, %xmm3, %xmm4
; GFNIAVX1-NEXT: vpaddb %xmm11, %xmm11, %xmm7
; GFNIAVX1-NEXT: vpblendvb %xmm7, %xmm4, %xmm3, %xmm3
-; GFNIAVX1-NEXT: vpsrlw $1, %xmm3, %xmm4
-; GFNIAVX1-NEXT: vpand %xmm4, %xmm8, %xmm4
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm8, %xmm3, %xmm4
; GFNIAVX1-NEXT: vpaddb %xmm7, %xmm7, %xmm7
; GFNIAVX1-NEXT: vpblendvb %xmm7, %xmm4, %xmm3, %xmm3
; GFNIAVX1-NEXT: vpaddb %xmm1, %xmm1, %xmm1
-; GFNIAVX1-NEXT: vpsllw $4, %xmm1, %xmm4
-; GFNIAVX1-NEXT: vpand %xmm4, %xmm9, %xmm4
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm9, %xmm1, %xmm4
; GFNIAVX1-NEXT: vpxor %xmm6, %xmm2, %xmm2
; GFNIAVX1-NEXT: vpsllw $5, %xmm2, %xmm2
; GFNIAVX1-NEXT: vpblendvb %xmm2, %xmm4, %xmm1, %xmm1
-; GFNIAVX1-NEXT: vpsllw $2, %xmm1, %xmm4
-; GFNIAVX1-NEXT: vpand %xmm4, %xmm10, %xmm4
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm10, %xmm1, %xmm4
; GFNIAVX1-NEXT: vpaddb %xmm2, %xmm2, %xmm2
; GFNIAVX1-NEXT: vpblendvb %xmm2, %xmm4, %xmm1, %xmm1
; GFNIAVX1-NEXT: vpaddb %xmm1, %xmm1, %xmm4
@@ -2152,60 +2025,50 @@ define <64 x i8> @var_fshr_v64i8(<64 x i8> %a, <64 x i8> %b, <64 x i8> %amt) nou
;
; GFNIAVX2-LABEL: var_fshr_v64i8:
; GFNIAVX2: # %bb.0:
-; GFNIAVX2-NEXT: vpsrlw $4, %ymm2, %ymm6
-; GFNIAVX2-NEXT: vpbroadcastb {{.*#+}} ymm7 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
-; GFNIAVX2-NEXT: vpand %ymm7, %ymm6, %ymm8
+; GFNIAVX2-NEXT: vpbroadcastq {{.*#+}} ymm7 = [1161999622361579520,1161999622361579520,1161999622361579520,1161999622361579520]
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, %ymm7, %ymm2, %ymm8
; GFNIAVX2-NEXT: vpbroadcastb {{.*#+}} ymm6 = [7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7]
; GFNIAVX2-NEXT: vpand %ymm6, %ymm4, %ymm9
; GFNIAVX2-NEXT: vpsllw $5, %ymm9, %ymm9
; GFNIAVX2-NEXT: vpblendvb %ymm9, %ymm8, %ymm2, %ymm2
-; GFNIAVX2-NEXT: vpsrlw $2, %ymm2, %ymm8
-; GFNIAVX2-NEXT: vpbroadcastb {{.*#+}} ymm10 = [63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63]
-; GFNIAVX2-NEXT: vpand %ymm10, %ymm8, %ymm8
+; GFNIAVX2-NEXT: vpbroadcastq {{.*#+}} ymm8 = [290499906672525312,290499906672525312,290499906672525312,290499906672525312]
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, %ymm8, %ymm2, %ymm10
; GFNIAVX2-NEXT: vpaddb %ymm9, %ymm9, %ymm9
-; GFNIAVX2-NEXT: vpblendvb %ymm9, %ymm8, %ymm2, %ymm2
-; GFNIAVX2-NEXT: vpsrlw $1, %ymm2, %ymm8
-; GFNIAVX2-NEXT: vpbroadcastb {{.*#+}} ymm11 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127]
-; GFNIAVX2-NEXT: vpand %ymm11, %ymm8, %ymm8
+; GFNIAVX2-NEXT: vpblendvb %ymm9, %ymm10, %ymm2, %ymm2
+; GFNIAVX2-NEXT: vpbroadcastq {{.*#+}} ymm10 = [145249953336295424,145249953336295424,145249953336295424,145249953336295424]
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, %ymm10, %ymm2, %ymm11
; GFNIAVX2-NEXT: vpaddb %ymm9, %ymm9, %ymm9
-; GFNIAVX2-NEXT: vpblendvb %ymm9, %ymm8, %ymm2, %ymm2
+; GFNIAVX2-NEXT: vpblendvb %ymm9, %ymm11, %ymm2, %ymm2
; GFNIAVX2-NEXT: vpaddb %ymm0, %ymm0, %ymm0
-; GFNIAVX2-NEXT: vpsllw $4, %ymm0, %ymm8
-; GFNIAVX2-NEXT: vpbroadcastb {{.*#+}} ymm9 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240]
-; GFNIAVX2-NEXT: vpand %ymm9, %ymm8, %ymm8
+; GFNIAVX2-NEXT: vpbroadcastq {{.*#+}} ymm9 = [16909320,16909320,16909320,16909320]
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, %ymm9, %ymm0, %ymm11
; GFNIAVX2-NEXT: vpandn %ymm6, %ymm4, %ymm4
; GFNIAVX2-NEXT: vpsllw $5, %ymm4, %ymm4
-; GFNIAVX2-NEXT: vpblendvb %ymm4, %ymm8, %ymm0, %ymm0
-; GFNIAVX2-NEXT: vpsllw $2, %ymm0, %ymm8
-; GFNIAVX2-NEXT: vpbroadcastb {{.*#+}} ymm12 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252]
-; GFNIAVX2-NEXT: vpand %ymm12, %ymm8, %ymm8
+; GFNIAVX2-NEXT: vpblendvb %ymm4, %ymm11, %ymm0, %ymm0
+; GFNIAVX2-NEXT: vpbroadcastq {{.*#+}} ymm11 = [1108169199648,1108169199648,1108169199648,1108169199648]
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, %ymm11, %ymm0, %ymm12
; GFNIAVX2-NEXT: vpaddb %ymm4, %ymm4, %ymm4
-; GFNIAVX2-NEXT: vpblendvb %ymm4, %ymm8, %ymm0, %ymm0
-; GFNIAVX2-NEXT: vpaddb %ymm0, %ymm0, %ymm8
+; GFNIAVX2-NEXT: vpblendvb %ymm4, %ymm12, %ymm0, %ymm0
+; GFNIAVX2-NEXT: vpaddb %ymm0, %ymm0, %ymm12
; GFNIAVX2-NEXT: vpaddb %ymm4, %ymm4, %ymm4
-; GFNIAVX2-NEXT: vpblendvb %ymm4, %ymm8, %ymm0, %ymm0
+; GFNIAVX2-NEXT: vpblendvb %ymm4, %ymm12, %ymm0, %ymm0
; GFNIAVX2-NEXT: vpor %ymm2, %ymm0, %ymm0
-; GFNIAVX2-NEXT: vpsrlw $4, %ymm3, %ymm2
-; GFNIAVX2-NEXT: vpand %ymm7, %ymm2, %ymm2
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, %ymm7, %ymm3, %ymm2
; GFNIAVX2-NEXT: vpand %ymm6, %ymm5, %ymm4
; GFNIAVX2-NEXT: vpsllw $5, %ymm4, %ymm4
; GFNIAVX2-NEXT: vpblendvb %ymm4, %ymm2, %ymm3, %ymm2
-; GFNIAVX2-NEXT: vpsrlw $2, %ymm2, %ymm3
-; GFNIAVX2-NEXT: vpand %ymm3, %ymm10, %ymm3
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, %ymm8, %ymm2, %ymm3
; GFNIAVX2-NEXT: vpaddb %ymm4, %ymm4, %ymm4
; GFNIAVX2-NEXT: vpblendvb %ymm4, %ymm3, %ymm2, %ymm2
-; GFNIAVX2-NEXT: vpsrlw $1, %ymm2, %ymm3
-; GFNIAVX2-NEXT: vpand %ymm3, %ymm11, %ymm3
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, %ymm10, %ymm2, %ymm3
; GFNIAVX2-NEXT: vpaddb %ymm4, %ymm4, %ymm4
; GFNIAVX2-NEXT: vpblendvb %ymm4, %ymm3, %ymm2, %ymm2
; GFNIAVX2-NEXT: vpaddb %ymm1, %ymm1, %ymm1
-; GFNIAVX2-NEXT: vpsllw $4, %ymm1, %ymm3
-; GFNIAVX2-NEXT: vpand %ymm3, %ymm9, %ymm3
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, %ymm9, %ymm1, %ymm3
; GFNIAVX2-NEXT: vpandn %ymm6, %ymm5, %ymm4
; GFNIAVX2-NEXT: vpsllw $5, %ymm4, %ymm4
; GFNIAVX2-NEXT: vpblendvb %ymm4, %ymm3, %ymm1, %ymm1
-; GFNIAVX2-NEXT: vpsllw $2, %ymm1, %ymm3
-; GFNIAVX2-NEXT: vpand %ymm3, %ymm12, %ymm3
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, %ymm11, %ymm1, %ymm3
; GFNIAVX2-NEXT: vpaddb %ymm4, %ymm4, %ymm4
; GFNIAVX2-NEXT: vpblendvb %ymm4, %ymm3, %ymm1, %ymm1
; GFNIAVX2-NEXT: vpaddb %ymm1, %ymm1, %ymm3
@@ -2216,62 +2079,52 @@ define <64 x i8> @var_fshr_v64i8(<64 x i8> %a, <64 x i8> %b, <64 x i8> %amt) nou
;
; GFNIAVX512VL-LABEL: var_fshr_v64i8:
; GFNIAVX512VL: # %bb.0:
-; GFNIAVX512VL-NEXT: vextracti64x4 $1, %zmm1, %ymm4
-; GFNIAVX512VL-NEXT: vpsrlw $4, %ymm4, %ymm3
-; GFNIAVX512VL-NEXT: vpbroadcastd {{.*#+}} ymm5 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
-; GFNIAVX512VL-NEXT: vpand %ymm5, %ymm3, %ymm6
-; GFNIAVX512VL-NEXT: vpbroadcastd {{.*#+}} zmm7 = [7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7]
-; GFNIAVX512VL-NEXT: vpandq %zmm7, %zmm2, %zmm2
-; GFNIAVX512VL-NEXT: vextracti64x4 $1, %zmm2, %ymm3
-; GFNIAVX512VL-NEXT: vpsllw $5, %ymm3, %ymm8
-; GFNIAVX512VL-NEXT: vpblendvb %ymm8, %ymm6, %ymm4, %ymm4
-; GFNIAVX512VL-NEXT: vpsrlw $2, %ymm4, %ymm6
-; GFNIAVX512VL-NEXT: vpbroadcastd {{.*#+}} ymm9 = [63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63]
-; GFNIAVX512VL-NEXT: vpand %ymm6, %ymm9, %ymm6
+; GFNIAVX512VL-NEXT: vextracti64x4 $1, %zmm1, %ymm3
+; GFNIAVX512VL-NEXT: vpbroadcastq {{.*#+}} ymm4 = [1161999622361579520,1161999622361579520,1161999622361579520,1161999622361579520]
+; GFNIAVX512VL-NEXT: vgf2p8affineqb $0, %ymm4, %ymm3, %ymm5
+; GFNIAVX512VL-NEXT: vpbroadcastd {{.*#+}} zmm6 = [7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7]
+; GFNIAVX512VL-NEXT: vpandq %zmm6, %zmm2, %zmm2
+; GFNIAVX512VL-NEXT: vextracti64x4 $1, %zmm2, %ymm7
+; GFNIAVX512VL-NEXT: vpsllw $5, %ymm7, %ymm8
+; GFNIAVX512VL-NEXT: vpblendvb %ymm8, %ymm5, %ymm3, %ymm3
+; GFNIAVX512VL-NEXT: vpbroadcastq {{.*#+}} ymm5 = [290499906672525312,290499906672525312,290499906672525312,290499906672525312]
+; GFNIAVX512VL-NEXT: vgf2p8affineqb $0, %ymm5, %ymm3, %ymm9
; GFNIAVX512VL-NEXT: vpaddb %ymm8, %ymm8, %ymm8
-; GFNIAVX512VL-NEXT: vpblendvb %ymm8, %ymm6, %ymm4, %ymm4
-; GFNIAVX512VL-NEXT: vpsrlw $1, %ymm4, %ymm6
-; GFNIAVX512VL-NEXT: vpbroadcastd {{.*#+}} ymm10 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127]
-; GFNIAVX512VL-NEXT: vpand %ymm6, %ymm10, %ymm6
+; GFNIAVX512VL-NEXT: vpblendvb %ymm8, %ymm9, %ymm3, %ymm3
+; GFNIAVX512VL-NEXT: vpbroadcastq {{.*#+}} ymm9 = [145249953336295424,145249953336295424,145249953336295424,145249953336295424]
+; GFNIAVX512VL-NEXT: vgf2p8affineqb $0, %ymm9, %ymm3, %ymm10
; GFNIAVX512VL-NEXT: vpaddb %ymm8, %ymm8, %ymm8
-; GFNIAVX512VL-NEXT: vpblendvb %ymm8, %ymm6, %ymm4, %ymm4
-; GFNIAVX512VL-NEXT: vpsrlw $4, %ymm1, %ymm6
-; GFNIAVX512VL-NEXT: vpand %ymm5, %ymm6, %ymm5
-; GFNIAVX512VL-NEXT: vpsllw $5, %ymm2, %ymm6
-; GFNIAVX512VL-NEXT: vpblendvb %ymm6, %ymm5, %ymm1, %ymm1
-; GFNIAVX512VL-NEXT: vpsrlw $2, %ymm1, %ymm5
-; GFNIAVX512VL-NEXT: vpand %ymm5, %ymm9, %ymm5
-; GFNIAVX512VL-NEXT: vpaddb %ymm6, %ymm6, %ymm6
-; GFNIAVX512VL-NEXT: vpblendvb %ymm6, %ymm5, %ymm1, %ymm1
-; GFNIAVX512VL-NEXT: vpsrlw $1, %ymm1, %ymm5
-; GFNIAVX512VL-NEXT: vpand %ymm5, %ymm10, %ymm5
-; GFNIAVX512VL-NEXT: vpaddb %ymm6, %ymm6, %ymm6
-; GFNIAVX512VL-NEXT: vpblendvb %ymm6, %ymm5, %ymm1, %ymm1
-; GFNIAVX512VL-NEXT: vinserti64x4 $1, %ymm4, %zmm1, %zmm1
-; GFNIAVX512VL-NEXT: vextracti64x4 $1, %zmm0, %ymm4
-; GFNIAVX512VL-NEXT: vpaddb %ymm4, %ymm4, %ymm4
-; GFNIAVX512VL-NEXT: vpsllw $4, %ymm4, %ymm5
-; GFNIAVX512VL-NEXT: vpbroadcastd {{.*#+}} ymm6 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240]
-; GFNIAVX512VL-NEXT: vpand %ymm6, %ymm5, %ymm5
-; GFNIAVX512VL-NEXT: vpxor %ymm7, %ymm3, %ymm3
-; GFNIAVX512VL-NEXT: vpsllw $5, %ymm3, %ymm3
-; GFNIAVX512VL-NEXT: vpblendvb %ymm3, %ymm5, %ymm4, %ymm4
-; GFNIAVX512VL-NEXT: vpsllw $2, %ymm4, %ymm5
-; GFNIAVX512VL-NEXT: vpbroadcastd {{.*#+}} ymm8 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252]
-; GFNIAVX512VL-NEXT: vpand %ymm5, %ymm8, %ymm5
-; GFNIAVX512VL-NEXT: vpaddb %ymm3, %ymm3, %ymm3
-; GFNIAVX512VL-NEXT: vpblendvb %ymm3, %ymm5, %ymm4, %ymm4
-; GFNIAVX512VL-NEXT: vpaddb %ymm4, %ymm4, %ymm5
+; GFNIAVX512VL-NEXT: vpblendvb %ymm8, %ymm10, %ymm3, %ymm3
+; GFNIAVX512VL-NEXT: vgf2p8affineqb $0, %ymm4, %ymm1, %ymm4
+; GFNIAVX512VL-NEXT: vpsllw $5, %ymm2, %ymm8
+; GFNIAVX512VL-NEXT: vpblendvb %ymm8, %ymm4, %ymm1, %ymm1
+; GFNIAVX512VL-NEXT: vgf2p8affineqb $0, %ymm5, %ymm1, %ymm4
+; GFNIAVX512VL-NEXT: vpaddb %ymm8, %ymm8, %ymm5
+; GFNIAVX512VL-NEXT: vpblendvb %ymm5, %ymm4, %ymm1, %ymm1
+; GFNIAVX512VL-NEXT: vgf2p8affineqb $0, %ymm9, %ymm1, %ymm4
+; GFNIAVX512VL-NEXT: vpaddb %ymm5, %ymm5, %ymm5
+; GFNIAVX512VL-NEXT: vpblendvb %ymm5, %ymm4, %ymm1, %ymm1
+; GFNIAVX512VL-NEXT: vinserti64x4 $1, %ymm3, %zmm1, %zmm1
+; GFNIAVX512VL-NEXT: vextracti64x4 $1, %zmm0, %ymm3
; GFNIAVX512VL-NEXT: vpaddb %ymm3, %ymm3, %ymm3
-; GFNIAVX512VL-NEXT: vpblendvb %ymm3, %ymm5, %ymm4, %ymm3
+; GFNIAVX512VL-NEXT: vpbroadcastq {{.*#+}} ymm4 = [16909320,16909320,16909320,16909320]
+; GFNIAVX512VL-NEXT: vgf2p8affineqb $0, %ymm4, %ymm3, %ymm5
+; GFNIAVX512VL-NEXT: vpxor %ymm6, %ymm7, %ymm7
+; GFNIAVX512VL-NEXT: vpsllw $5, %ymm7, %ymm7
+; GFNIAVX512VL-NEXT: vpblendvb %ymm7, %ymm5, %ymm3, %ymm3
+; GFNIAVX512VL-NEXT: vpbroadcastq {{.*#+}} ymm5 = [1108169199648,1108169199648,1108169199648,1108169199648]
+; GFNIAVX512VL-NEXT: vgf2p8affineqb $0, %ymm5, %ymm3, %ymm8
+; GFNIAVX512VL-NEXT: vpaddb %ymm7, %ymm7, %ymm7
+; GFNIAVX512VL-NEXT: vpblendvb %ymm7, %ymm8, %ymm3, %ymm3
+; GFNIAVX512VL-NEXT: vpaddb %ymm3, %ymm3, %ymm8
+; GFNIAVX512VL-NEXT: vpaddb %ymm7, %ymm7, %ymm7
+; GFNIAVX512VL-NEXT: vpblendvb %ymm7, %ymm8, %ymm3, %ymm3
; GFNIAVX512VL-NEXT: vpaddb %ymm0, %ymm0, %ymm0
-; GFNIAVX512VL-NEXT: vpsllw $4, %ymm0, %ymm4
-; GFNIAVX512VL-NEXT: vpand %ymm6, %ymm4, %ymm4
-; GFNIAVX512VL-NEXT: vpxor %ymm7, %ymm2, %ymm2
+; GFNIAVX512VL-NEXT: vgf2p8affineqb $0, %ymm4, %ymm0, %ymm4
+; GFNIAVX512VL-NEXT: vpxor %ymm6, %ymm2, %ymm2
; GFNIAVX512VL-NEXT: vpsllw $5, %ymm2, %ymm2
; GFNIAVX512VL-NEXT: vpblendvb %ymm2, %ymm4, %ymm0, %ymm0
-; GFNIAVX512VL-NEXT: vpsllw $2, %ymm0, %ymm4
-; GFNIAVX512VL-NEXT: vpand %ymm4, %ymm8, %ymm4
+; GFNIAVX512VL-NEXT: vgf2p8affineqb $0, %ymm5, %ymm0, %ymm4
; GFNIAVX512VL-NEXT: vpaddb %ymm2, %ymm2, %ymm2
; GFNIAVX512VL-NEXT: vpblendvb %ymm2, %ymm4, %ymm0, %ymm0
; GFNIAVX512VL-NEXT: vpaddb %ymm0, %ymm0, %ymm4
@@ -2874,45 +2727,31 @@ define <64 x i8> @constant_fshr_v64i8(<64 x i8> %a, <64 x i8> %b) nounwind {
define <64 x i8> @splatconstant_fshl_v64i8(<64 x i8> %a, <64 x i8> %b) nounwind {
; GFNISSE-LABEL: splatconstant_fshl_v64i8:
; GFNISSE: # %bb.0:
-; GFNISSE-NEXT: psrlw $7, %xmm4
-; GFNISSE-NEXT: movdqa {{.*#+}} xmm8 = [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1]
-; GFNISSE-NEXT: pand %xmm8, %xmm4
+; GFNISSE-NEXT: movdqa {{.*#+}} xmm8 = [9223372036854775808,9223372036854775808]
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm8, %xmm4
; GFNISSE-NEXT: paddb %xmm0, %xmm0
; GFNISSE-NEXT: por %xmm4, %xmm0
-; GFNISSE-NEXT: psrlw $7, %xmm5
-; GFNISSE-NEXT: pand %xmm8, %xmm5
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm8, %xmm5
; GFNISSE-NEXT: paddb %xmm1, %xmm1
; GFNISSE-NEXT: por %xmm5, %xmm1
-; GFNISSE-NEXT: psrlw $7, %xmm6
-; GFNISSE-NEXT: pand %xmm8, %xmm6
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm8, %xmm6
; GFNISSE-NEXT: paddb %xmm2, %xmm2
; GFNISSE-NEXT: por %xmm6, %xmm2
-; GFNISSE-NEXT: psrlw $7, %xmm7
-; GFNISSE-NEXT: pand %xmm7, %xmm8
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm8, %xmm7
; GFNISSE-NEXT: paddb %xmm3, %xmm3
-; GFNISSE-NEXT: por %xmm8, %xmm3
+; GFNISSE-NEXT: por %xmm7, %xmm3
; GFNISSE-NEXT: retq
;
; GFNIAVX1-LABEL: splatconstant_fshl_v64i8:
; GFNIAVX1: # %bb.0:
-; GFNIAVX1-NEXT: vextractf128 $1, %ymm2, %xmm4
-; GFNIAVX1-NEXT: vpsrlw $7, %xmm4, %xmm4
-; GFNIAVX1-NEXT: vbroadcastss {{.*#+}} xmm5 = [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1]
-; GFNIAVX1-NEXT: vpand %xmm5, %xmm4, %xmm4
-; GFNIAVX1-NEXT: vpsrlw $7, %xmm2, %xmm2
-; GFNIAVX1-NEXT: vpand %xmm5, %xmm2, %xmm2
-; GFNIAVX1-NEXT: vinsertf128 $1, %xmm4, %ymm2, %ymm2
-; GFNIAVX1-NEXT: vpaddb %xmm0, %xmm0, %xmm4
+; GFNIAVX1-NEXT: vbroadcastsd {{.*#+}} ymm4 = [0,0,0,0,0,0,0,128,0,0,0,0,0,0,0,128,0,0,0,0,0,0,0,128,0,0,0,0,0,0,0,128]
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %ymm4, %ymm2, %ymm2
+; GFNIAVX1-NEXT: vpaddb %xmm0, %xmm0, %xmm5
; GFNIAVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
; GFNIAVX1-NEXT: vpaddb %xmm0, %xmm0, %xmm0
-; GFNIAVX1-NEXT: vinsertf128 $1, %xmm0, %ymm4, %ymm0
+; GFNIAVX1-NEXT: vinsertf128 $1, %xmm0, %ymm5, %ymm0
; GFNIAVX1-NEXT: vorps %ymm2, %ymm0, %ymm0
-; GFNIAVX1-NEXT: vextractf128 $1, %ymm3, %xmm2
-; GFNIAVX1-NEXT: vpsrlw $7, %xmm2, %xmm2
-; GFNIAVX1-NEXT: vpand %xmm5, %xmm2, %xmm2
-; GFNIAVX1-NEXT: vpsrlw $7, %xmm3, %xmm3
-; GFNIAVX1-NEXT: vpand %xmm5, %xmm3, %xmm3
-; GFNIAVX1-NEXT: vinsertf128 $1, %xmm2, %ymm3, %ymm2
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %ymm4, %ymm3, %ymm2
; GFNIAVX1-NEXT: vpaddb %xmm1, %xmm1, %xmm3
; GFNIAVX1-NEXT: vextractf128 $1, %ymm1, %xmm1
; GFNIAVX1-NEXT: vpaddb %xmm1, %xmm1, %xmm1
@@ -2922,35 +2761,30 @@ define <64 x i8> @splatconstant_fshl_v64i8(<64 x i8> %a, <64 x i8> %b) nounwind
;
; GFNIAVX2-LABEL: splatconstant_fshl_v64i8:
; GFNIAVX2: # %bb.0:
-; GFNIAVX2-NEXT: vpsrlw $7, %ymm2, %ymm2
-; GFNIAVX2-NEXT: vpbroadcastb {{.*#+}} ymm4 = [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1]
-; GFNIAVX2-NEXT: vpand %ymm4, %ymm2, %ymm2
+; GFNIAVX2-NEXT: vpbroadcastq {{.*#+}} ymm4 = [9223372036854775808,9223372036854775808,9223372036854775808,9223372036854775808]
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, %ymm4, %ymm2, %ymm2
; GFNIAVX2-NEXT: vpaddb %ymm0, %ymm0, %ymm0
; GFNIAVX2-NEXT: vpor %ymm2, %ymm0, %ymm0
-; GFNIAVX2-NEXT: vpsrlw $7, %ymm3, %ymm2
-; GFNIAVX2-NEXT: vpand %ymm4, %ymm2, %ymm2
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, %ymm4, %ymm3, %ymm2
; GFNIAVX2-NEXT: vpaddb %ymm1, %ymm1, %ymm1
; GFNIAVX2-NEXT: vpor %ymm2, %ymm1, %ymm1
; GFNIAVX2-NEXT: retq
;
; GFNIAVX512VL-LABEL: splatconstant_fshl_v64i8:
; GFNIAVX512VL: # %bb.0:
-; GFNIAVX512VL-NEXT: vpsrlw $7, %ymm1, %ymm2
-; GFNIAVX512VL-NEXT: vextracti64x4 $1, %zmm1, %ymm1
-; GFNIAVX512VL-NEXT: vpsrlw $7, %ymm1, %ymm1
-; GFNIAVX512VL-NEXT: vinserti64x4 $1, %ymm1, %zmm2, %zmm1
; GFNIAVX512VL-NEXT: vpaddb %ymm0, %ymm0, %ymm2
; GFNIAVX512VL-NEXT: vextracti64x4 $1, %zmm0, %ymm0
; GFNIAVX512VL-NEXT: vpaddb %ymm0, %ymm0, %ymm0
; GFNIAVX512VL-NEXT: vinserti64x4 $1, %ymm0, %zmm2, %zmm0
-; GFNIAVX512VL-NEXT: vpternlogd $248, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm1, %zmm0
+; GFNIAVX512VL-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm1, %zmm1
+; GFNIAVX512VL-NEXT: vporq %zmm1, %zmm0, %zmm0
; GFNIAVX512VL-NEXT: retq
;
; GFNIAVX512BW-LABEL: splatconstant_fshl_v64i8:
; GFNIAVX512BW: # %bb.0:
-; GFNIAVX512BW-NEXT: vpsrlw $7, %zmm1, %zmm1
-; GFNIAVX512BW-NEXT: vpaddb %zmm0, %zmm0, %zmm0
-; GFNIAVX512BW-NEXT: vpternlogd $248, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm1, %zmm0
+; GFNIAVX512BW-NEXT: vpaddw %zmm0, %zmm0, %zmm2
+; GFNIAVX512BW-NEXT: vpsrlw $7, %zmm1, %zmm0
+; GFNIAVX512BW-NEXT: vpternlogd $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm2, %zmm0
; GFNIAVX512BW-NEXT: retq
%res = call <64 x i8> @llvm.fshl.v64i8(<64 x i8> %a, <64 x i8> %b, <64 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>)
ret <64 x i8> %res
@@ -2960,90 +2794,51 @@ declare <64 x i8> @llvm.fshl.v64i8(<64 x i8>, <64 x i8>, <64 x i8>)
define <64 x i8> @splatconstant_fshr_v64i8(<64 x i8> %a, <64 x i8> %b) nounwind {
; GFNISSE-LABEL: splatconstant_fshr_v64i8:
; GFNISSE: # %bb.0:
-; GFNISSE-NEXT: psrlw $2, %xmm4
-; GFNISSE-NEXT: movdqa {{.*#+}} xmm8 = [192,192,192,192,192,192,192,192,192,192,192,192,192,192,192,192]
-; GFNISSE-NEXT: movdqa %xmm8, %xmm9
-; GFNISSE-NEXT: pandn %xmm4, %xmm9
-; GFNISSE-NEXT: psllw $6, %xmm0
-; GFNISSE-NEXT: pand %xmm8, %xmm0
-; GFNISSE-NEXT: por %xmm9, %xmm0
-; GFNISSE-NEXT: psrlw $2, %xmm5
-; GFNISSE-NEXT: movdqa %xmm8, %xmm4
-; GFNISSE-NEXT: pandn %xmm5, %xmm4
-; GFNISSE-NEXT: psllw $6, %xmm1
-; GFNISSE-NEXT: pand %xmm8, %xmm1
-; GFNISSE-NEXT: por %xmm4, %xmm1
-; GFNISSE-NEXT: psrlw $2, %xmm6
-; GFNISSE-NEXT: movdqa %xmm8, %xmm4
-; GFNISSE-NEXT: pandn %xmm6, %xmm4
-; GFNISSE-NEXT: psllw $6, %xmm2
-; GFNISSE-NEXT: pand %xmm8, %xmm2
-; GFNISSE-NEXT: por %xmm4, %xmm2
-; GFNISSE-NEXT: psrlw $2, %xmm7
-; GFNISSE-NEXT: psllw $6, %xmm3
-; GFNISSE-NEXT: pand %xmm8, %xmm3
-; GFNISSE-NEXT: pandn %xmm7, %xmm8
-; GFNISSE-NEXT: por %xmm8, %xmm3
+; GFNISSE-NEXT: movdqa {{.*#+}} xmm8 = [290499906672525312,290499906672525312]
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm8, %xmm4
+; GFNISSE-NEXT: pmovsxwq {{.*#+}} xmm9 = [258,258]
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm9, %xmm0
+; GFNISSE-NEXT: por %xmm4, %xmm0
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm8, %xmm5
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm9, %xmm1
+; GFNISSE-NEXT: por %xmm5, %xmm1
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm8, %xmm6
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm9, %xmm2
+; GFNISSE-NEXT: por %xmm6, %xmm2
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm8, %xmm7
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm9, %xmm3
+; GFNISSE-NEXT: por %xmm7, %xmm3
; GFNISSE-NEXT: retq
;
; GFNIAVX1-LABEL: splatconstant_fshr_v64i8:
; GFNIAVX1: # %bb.0:
-; GFNIAVX1-NEXT: vextractf128 $1, %ymm2, %xmm4
-; GFNIAVX1-NEXT: vpsrlw $2, %xmm4, %xmm4
-; GFNIAVX1-NEXT: vbroadcastss {{.*#+}} xmm5 = [63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63]
-; GFNIAVX1-NEXT: vpand %xmm5, %xmm4, %xmm4
-; GFNIAVX1-NEXT: vpsrlw $2, %xmm2, %xmm2
-; GFNIAVX1-NEXT: vpand %xmm5, %xmm2, %xmm2
-; GFNIAVX1-NEXT: vinsertf128 $1, %xmm4, %ymm2, %ymm2
-; GFNIAVX1-NEXT: vextractf128 $1, %ymm0, %xmm4
-; GFNIAVX1-NEXT: vpsllw $6, %xmm4, %xmm4
-; GFNIAVX1-NEXT: vbroadcastss {{.*#+}} xmm6 = [192,192,192,192,192,192,192,192,192,192,192,192,192,192,192,192]
-; GFNIAVX1-NEXT: vpand %xmm6, %xmm4, %xmm4
-; GFNIAVX1-NEXT: vpsllw $6, %xmm0, %xmm0
-; GFNIAVX1-NEXT: vpand %xmm6, %xmm0, %xmm0
-; GFNIAVX1-NEXT: vinsertf128 $1, %xmm4, %ymm0, %ymm0
+; GFNIAVX1-NEXT: vbroadcastsd {{.*#+}} ymm4 = [0,0,128,64,32,16,8,4,0,0,128,64,32,16,8,4,0,0,128,64,32,16,8,4,0,0,128,64,32,16,8,4]
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %ymm4, %ymm2, %ymm2
+; GFNIAVX1-NEXT: vbroadcastsd {{.*#+}} ymm5 = [2,1,0,0,0,0,0,0,2,1,0,0,0,0,0,0,2,1,0,0,0,0,0,0,2,1,0,0,0,0,0,0]
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %ymm5, %ymm0, %ymm0
; GFNIAVX1-NEXT: vorps %ymm2, %ymm0, %ymm0
-; GFNIAVX1-NEXT: vextractf128 $1, %ymm3, %xmm2
-; GFNIAVX1-NEXT: vpsrlw $2, %xmm2, %xmm2
-; GFNIAVX1-NEXT: vpand %xmm5, %xmm2, %xmm2
-; GFNIAVX1-NEXT: vpsrlw $2, %xmm3, %xmm3
-; GFNIAVX1-NEXT: vpand %xmm5, %xmm3, %xmm3
-; GFNIAVX1-NEXT: vinsertf128 $1, %xmm2, %ymm3, %ymm2
-; GFNIAVX1-NEXT: vextractf128 $1, %ymm1, %xmm3
-; GFNIAVX1-NEXT: vpsllw $6, %xmm3, %xmm3
-; GFNIAVX1-NEXT: vpand %xmm6, %xmm3, %xmm3
-; GFNIAVX1-NEXT: vpsllw $6, %xmm1, %xmm1
-; GFNIAVX1-NEXT: vpand %xmm6, %xmm1, %xmm1
-; GFNIAVX1-NEXT: vinsertf128 $1, %xmm3, %ymm1, %ymm1
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %ymm4, %ymm3, %ymm2
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %ymm5, %ymm1, %ymm1
; GFNIAVX1-NEXT: vorps %ymm2, %ymm1, %ymm1
; GFNIAVX1-NEXT: retq
;
; GFNIAVX2-LABEL: splatconstant_fshr_v64i8:
; GFNIAVX2: # %bb.0:
-; GFNIAVX2-NEXT: vpsrlw $2, %ymm2, %ymm2
-; GFNIAVX2-NEXT: vpbroadcastb {{.*#+}} ymm4 = [192,192,192,192,192,192,192,192,192,192,192,192,192,192,192,192,192,192,192,192,192,192,192,192,192,192,192,192,192,192,192,192]
-; GFNIAVX2-NEXT: vpandn %ymm2, %ymm4, %ymm2
-; GFNIAVX2-NEXT: vpsllw $6, %ymm0, %ymm0
-; GFNIAVX2-NEXT: vpand %ymm4, %ymm0, %ymm0
+; GFNIAVX2-NEXT: vpbroadcastq {{.*#+}} ymm4 = [290499906672525312,290499906672525312,290499906672525312,290499906672525312]
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, %ymm4, %ymm2, %ymm2
+; GFNIAVX2-NEXT: vpbroadcastq {{.*#+}} ymm5 = [258,258,258,258]
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, %ymm5, %ymm0, %ymm0
; GFNIAVX2-NEXT: vpor %ymm2, %ymm0, %ymm0
-; GFNIAVX2-NEXT: vpsrlw $2, %ymm3, %ymm2
-; GFNIAVX2-NEXT: vpandn %ymm2, %ymm4, %ymm2
-; GFNIAVX2-NEXT: vpsllw $6, %ymm1, %ymm1
-; GFNIAVX2-NEXT: vpand %ymm4, %ymm1, %ymm1
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, %ymm4, %ymm3, %ymm2
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, %ymm5, %ymm1, %ymm1
; GFNIAVX2-NEXT: vpor %ymm2, %ymm1, %ymm1
; GFNIAVX2-NEXT: retq
;
; GFNIAVX512VL-LABEL: splatconstant_fshr_v64i8:
; GFNIAVX512VL: # %bb.0:
-; GFNIAVX512VL-NEXT: vpsllw $6, %ymm0, %ymm2
-; GFNIAVX512VL-NEXT: vextracti64x4 $1, %zmm0, %ymm0
-; GFNIAVX512VL-NEXT: vpsllw $6, %ymm0, %ymm0
-; GFNIAVX512VL-NEXT: vinserti64x4 $1, %ymm0, %zmm2, %zmm2
-; GFNIAVX512VL-NEXT: vpsrlw $2, %ymm1, %ymm0
-; GFNIAVX512VL-NEXT: vextracti64x4 $1, %zmm1, %ymm1
-; GFNIAVX512VL-NEXT: vpsrlw $2, %ymm1, %ymm1
-; GFNIAVX512VL-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; GFNIAVX512VL-NEXT: vpternlogd $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm2, %zmm0
+; GFNIAVX512VL-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm1, %zmm1
+; GFNIAVX512VL-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0
+; GFNIAVX512VL-NEXT: vporq %zmm1, %zmm0, %zmm0
; GFNIAVX512VL-NEXT: retq
;
; GFNIAVX512BW-LABEL: splatconstant_fshr_v64i8:
diff --git a/llvm/test/CodeGen/X86/gfni-rotates.ll b/llvm/test/CodeGen/X86/gfni-rotates.ll
index 96aff5b2af3155..9ddadca380fed6 100644
--- a/llvm/test/CodeGen/X86/gfni-rotates.ll
+++ b/llvm/test/CodeGen/X86/gfni-rotates.ll
@@ -14,28 +14,23 @@ define <16 x i8> @var_rotl_v16i8(<16 x i8> %a, <16 x i8> %amt) nounwind {
; GFNISSE: # %bb.0:
; GFNISSE-NEXT: movdqa %xmm1, %xmm2
; GFNISSE-NEXT: movdqa %xmm0, %xmm1
-; GFNISSE-NEXT: psrlw $4, %xmm0
-; GFNISSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; GFNISSE-NEXT: gf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; GFNISSE-NEXT: movdqa %xmm1, %xmm3
-; GFNISSE-NEXT: psllw $4, %xmm3
-; GFNISSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
+; GFNISSE-NEXT: gf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
; GFNISSE-NEXT: por %xmm0, %xmm3
; GFNISSE-NEXT: psllw $5, %xmm2
; GFNISSE-NEXT: movdqa %xmm2, %xmm0
; GFNISSE-NEXT: pblendvb %xmm0, %xmm3, %xmm1
; GFNISSE-NEXT: movdqa %xmm1, %xmm0
-; GFNISSE-NEXT: psrlw $6, %xmm0
-; GFNISSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; GFNISSE-NEXT: gf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; GFNISSE-NEXT: movdqa %xmm1, %xmm3
-; GFNISSE-NEXT: psllw $2, %xmm3
-; GFNISSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
+; GFNISSE-NEXT: gf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
; GFNISSE-NEXT: por %xmm0, %xmm3
; GFNISSE-NEXT: paddb %xmm2, %xmm2
; GFNISSE-NEXT: movdqa %xmm2, %xmm0
; GFNISSE-NEXT: pblendvb %xmm0, %xmm3, %xmm1
; GFNISSE-NEXT: movdqa %xmm1, %xmm0
-; GFNISSE-NEXT: psrlw $7, %xmm0
-; GFNISSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; GFNISSE-NEXT: gf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; GFNISSE-NEXT: movdqa %xmm1, %xmm3
; GFNISSE-NEXT: paddb %xmm1, %xmm3
; GFNISSE-NEXT: por %xmm0, %xmm3
@@ -47,22 +42,17 @@ define <16 x i8> @var_rotl_v16i8(<16 x i8> %a, <16 x i8> %amt) nounwind {
;
; GFNIAVX1OR2-LABEL: var_rotl_v16i8:
; GFNIAVX1OR2: # %bb.0:
-; GFNIAVX1OR2-NEXT: vpsrlw $4, %xmm0, %xmm2
-; GFNIAVX1OR2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
-; GFNIAVX1OR2-NEXT: vpsllw $4, %xmm0, %xmm3
-; GFNIAVX1OR2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3, %xmm3
+; GFNIAVX1OR2-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm2
+; GFNIAVX1OR2-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm3
; GFNIAVX1OR2-NEXT: vpor %xmm2, %xmm3, %xmm2
; GFNIAVX1OR2-NEXT: vpsllw $5, %xmm1, %xmm1
; GFNIAVX1OR2-NEXT: vpblendvb %xmm1, %xmm2, %xmm0, %xmm0
-; GFNIAVX1OR2-NEXT: vpsrlw $6, %xmm0, %xmm2
-; GFNIAVX1OR2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
-; GFNIAVX1OR2-NEXT: vpsllw $2, %xmm0, %xmm3
-; GFNIAVX1OR2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3, %xmm3
+; GFNIAVX1OR2-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm2
+; GFNIAVX1OR2-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm3
; GFNIAVX1OR2-NEXT: vpor %xmm2, %xmm3, %xmm2
; GFNIAVX1OR2-NEXT: vpaddb %xmm1, %xmm1, %xmm1
; GFNIAVX1OR2-NEXT: vpblendvb %xmm1, %xmm2, %xmm0, %xmm0
-; GFNIAVX1OR2-NEXT: vpsrlw $7, %xmm0, %xmm2
-; GFNIAVX1OR2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
+; GFNIAVX1OR2-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm2
; GFNIAVX1OR2-NEXT: vpaddb %xmm0, %xmm0, %xmm3
; GFNIAVX1OR2-NEXT: vpor %xmm2, %xmm3, %xmm2
; GFNIAVX1OR2-NEXT: vpaddb %xmm1, %xmm1, %xmm1
@@ -103,28 +93,23 @@ define <16 x i8> @var_rotr_v16i8(<16 x i8> %a, <16 x i8> %amt) nounwind {
; GFNISSE-LABEL: var_rotr_v16i8:
; GFNISSE: # %bb.0:
; GFNISSE-NEXT: movdqa %xmm0, %xmm2
-; GFNISSE-NEXT: psrlw $4, %xmm0
-; GFNISSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; GFNISSE-NEXT: gf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; GFNISSE-NEXT: movdqa %xmm2, %xmm3
-; GFNISSE-NEXT: psllw $4, %xmm3
-; GFNISSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
+; GFNISSE-NEXT: gf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
; GFNISSE-NEXT: por %xmm0, %xmm3
; GFNISSE-NEXT: pxor %xmm0, %xmm0
; GFNISSE-NEXT: psubb %xmm1, %xmm0
; GFNISSE-NEXT: psllw $5, %xmm0
; GFNISSE-NEXT: pblendvb %xmm0, %xmm3, %xmm2
; GFNISSE-NEXT: movdqa %xmm2, %xmm1
-; GFNISSE-NEXT: psrlw $6, %xmm1
-; GFNISSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; GFNISSE-NEXT: gf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; GFNISSE-NEXT: movdqa %xmm2, %xmm3
-; GFNISSE-NEXT: psllw $2, %xmm3
-; GFNISSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
+; GFNISSE-NEXT: gf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
; GFNISSE-NEXT: por %xmm1, %xmm3
; GFNISSE-NEXT: paddb %xmm0, %xmm0
; GFNISSE-NEXT: pblendvb %xmm0, %xmm3, %xmm2
; GFNISSE-NEXT: movdqa %xmm2, %xmm1
-; GFNISSE-NEXT: psrlw $7, %xmm1
-; GFNISSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; GFNISSE-NEXT: gf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; GFNISSE-NEXT: movdqa %xmm2, %xmm3
; GFNISSE-NEXT: paddb %xmm2, %xmm3
; GFNISSE-NEXT: por %xmm1, %xmm3
@@ -135,24 +120,19 @@ define <16 x i8> @var_rotr_v16i8(<16 x i8> %a, <16 x i8> %amt) nounwind {
;
; GFNIAVX1OR2-LABEL: var_rotr_v16i8:
; GFNIAVX1OR2: # %bb.0:
-; GFNIAVX1OR2-NEXT: vpsrlw $4, %xmm0, %xmm2
-; GFNIAVX1OR2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
-; GFNIAVX1OR2-NEXT: vpsllw $4, %xmm0, %xmm3
-; GFNIAVX1OR2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3, %xmm3
+; GFNIAVX1OR2-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm2
+; GFNIAVX1OR2-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm3
; GFNIAVX1OR2-NEXT: vpor %xmm2, %xmm3, %xmm2
; GFNIAVX1OR2-NEXT: vpxor %xmm3, %xmm3, %xmm3
; GFNIAVX1OR2-NEXT: vpsubb %xmm1, %xmm3, %xmm1
; GFNIAVX1OR2-NEXT: vpsllw $5, %xmm1, %xmm1
; GFNIAVX1OR2-NEXT: vpblendvb %xmm1, %xmm2, %xmm0, %xmm0
-; GFNIAVX1OR2-NEXT: vpsrlw $6, %xmm0, %xmm2
-; GFNIAVX1OR2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
-; GFNIAVX1OR2-NEXT: vpsllw $2, %xmm0, %xmm3
-; GFNIAVX1OR2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3, %xmm3
+; GFNIAVX1OR2-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm2
+; GFNIAVX1OR2-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm3
; GFNIAVX1OR2-NEXT: vpor %xmm2, %xmm3, %xmm2
; GFNIAVX1OR2-NEXT: vpaddb %xmm1, %xmm1, %xmm1
; GFNIAVX1OR2-NEXT: vpblendvb %xmm1, %xmm2, %xmm0, %xmm0
-; GFNIAVX1OR2-NEXT: vpsrlw $7, %xmm0, %xmm2
-; GFNIAVX1OR2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
+; GFNIAVX1OR2-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm2
; GFNIAVX1OR2-NEXT: vpaddb %xmm0, %xmm0, %xmm3
; GFNIAVX1OR2-NEXT: vpor %xmm2, %xmm3, %xmm2
; GFNIAVX1OR2-NEXT: vpaddb %xmm1, %xmm1, %xmm1
@@ -389,28 +369,17 @@ define <16 x i8> @constant_rotr_v16i8(<16 x i8> %a) nounwind {
define <16 x i8> @splatconstant_rotl_v16i8(<16 x i8> %a) nounwind {
; GFNISSE-LABEL: splatconstant_rotl_v16i8:
; GFNISSE: # %bb.0:
-; GFNISSE-NEXT: movdqa %xmm0, %xmm1
-; GFNISSE-NEXT: psrlw $5, %xmm1
-; GFNISSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
-; GFNISSE-NEXT: psllw $3, %xmm0
-; GFNISSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
-; GFNISSE-NEXT: por %xmm1, %xmm0
+; GFNISSE-NEXT: gf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; GFNISSE-NEXT: retq
;
; GFNIAVX1OR2-LABEL: splatconstant_rotl_v16i8:
; GFNIAVX1OR2: # %bb.0:
-; GFNIAVX1OR2-NEXT: vpsrlw $5, %xmm0, %xmm1
-; GFNIAVX1OR2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
-; GFNIAVX1OR2-NEXT: vpsllw $3, %xmm0, %xmm0
-; GFNIAVX1OR2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
-; GFNIAVX1OR2-NEXT: vpor %xmm1, %xmm0, %xmm0
+; GFNIAVX1OR2-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; GFNIAVX1OR2-NEXT: retq
;
; GFNIAVX512-LABEL: splatconstant_rotl_v16i8:
; GFNIAVX512: # %bb.0:
-; GFNIAVX512-NEXT: vpsllw $3, %xmm0, %xmm1
-; GFNIAVX512-NEXT: vpsrlw $5, %xmm0, %xmm0
-; GFNIAVX512-NEXT: vpternlogd $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm1, %xmm0
+; GFNIAVX512-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0
; GFNIAVX512-NEXT: retq
%res = call <16 x i8> @llvm.fshl.v16i8(<16 x i8> %a, <16 x i8> %a, <16 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)
ret <16 x i8> %res
@@ -420,26 +389,17 @@ declare <16 x i8> @llvm.fshl.v16i8(<16 x i8>, <16 x i8>, <16 x i8>)
define <16 x i8> @splatconstant_rotr_v16i8(<16 x i8> %a) nounwind {
; GFNISSE-LABEL: splatconstant_rotr_v16i8:
; GFNISSE: # %bb.0:
-; GFNISSE-NEXT: movdqa %xmm0, %xmm1
-; GFNISSE-NEXT: paddb %xmm0, %xmm1
-; GFNISSE-NEXT: psrlw $7, %xmm0
-; GFNISSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
-; GFNISSE-NEXT: por %xmm1, %xmm0
+; GFNISSE-NEXT: gf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; GFNISSE-NEXT: retq
;
; GFNIAVX1OR2-LABEL: splatconstant_rotr_v16i8:
; GFNIAVX1OR2: # %bb.0:
-; GFNIAVX1OR2-NEXT: vpaddb %xmm0, %xmm0, %xmm1
-; GFNIAVX1OR2-NEXT: vpsrlw $7, %xmm0, %xmm0
-; GFNIAVX1OR2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
-; GFNIAVX1OR2-NEXT: vpor %xmm0, %xmm1, %xmm0
+; GFNIAVX1OR2-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; GFNIAVX1OR2-NEXT: retq
;
; GFNIAVX512-LABEL: splatconstant_rotr_v16i8:
; GFNIAVX512: # %bb.0:
-; GFNIAVX512-NEXT: vpsrlw $7, %xmm0, %xmm1
-; GFNIAVX512-NEXT: vpaddb %xmm0, %xmm0, %xmm0
-; GFNIAVX512-NEXT: vpternlogd $248, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm1, %xmm0
+; GFNIAVX512-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0
; GFNIAVX512-NEXT: retq
%res = call <16 x i8> @llvm.fshr.v16i8(<16 x i8> %a, <16 x i8> %a, <16 x i8> <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>)
ret <16 x i8> %res
@@ -455,62 +415,52 @@ define <32 x i8> @var_rotl_v32i8(<32 x i8> %a, <32 x i8> %amt) nounwind {
; GFNISSE: # %bb.0:
; GFNISSE-NEXT: movdqa %xmm2, %xmm4
; GFNISSE-NEXT: movdqa %xmm0, %xmm2
-; GFNISSE-NEXT: psrlw $4, %xmm0
-; GFNISSE-NEXT: movdqa {{.*#+}} xmm5 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240]
-; GFNISSE-NEXT: movdqa %xmm5, %xmm6
-; GFNISSE-NEXT: pandn %xmm0, %xmm6
+; GFNISSE-NEXT: movdqa {{.*#+}} xmm5 = [1161999622361579520,1161999622361579520]
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm5, %xmm0
+; GFNISSE-NEXT: pmovsxdq {{.*#+}} xmm6 = [16909320,16909320]
; GFNISSE-NEXT: movdqa %xmm2, %xmm7
-; GFNISSE-NEXT: psllw $4, %xmm7
-; GFNISSE-NEXT: pand %xmm5, %xmm7
-; GFNISSE-NEXT: por %xmm6, %xmm7
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm6, %xmm7
+; GFNISSE-NEXT: por %xmm0, %xmm7
; GFNISSE-NEXT: psllw $5, %xmm4
; GFNISSE-NEXT: movdqa %xmm4, %xmm0
; GFNISSE-NEXT: pblendvb %xmm0, %xmm7, %xmm2
+; GFNISSE-NEXT: movdqa {{.*#+}} xmm7 = [4647714815446351872,4647714815446351872]
; GFNISSE-NEXT: movdqa %xmm2, %xmm0
-; GFNISSE-NEXT: psrlw $6, %xmm0
-; GFNISSE-NEXT: movdqa {{.*#+}} xmm6 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252]
-; GFNISSE-NEXT: movdqa %xmm6, %xmm7
-; GFNISSE-NEXT: pandn %xmm0, %xmm7
-; GFNISSE-NEXT: movdqa %xmm2, %xmm8
-; GFNISSE-NEXT: psllw $2, %xmm8
-; GFNISSE-NEXT: pand %xmm6, %xmm8
-; GFNISSE-NEXT: por %xmm7, %xmm8
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm7, %xmm0
+; GFNISSE-NEXT: movdqa {{.*#+}} xmm8 = [1108169199648,1108169199648]
+; GFNISSE-NEXT: movdqa %xmm2, %xmm9
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm8, %xmm9
+; GFNISSE-NEXT: por %xmm0, %xmm9
; GFNISSE-NEXT: paddb %xmm4, %xmm4
; GFNISSE-NEXT: movdqa %xmm4, %xmm0
-; GFNISSE-NEXT: pblendvb %xmm0, %xmm8, %xmm2
+; GFNISSE-NEXT: pblendvb %xmm0, %xmm9, %xmm2
+; GFNISSE-NEXT: movdqa {{.*#+}} xmm9 = [9223372036854775808,9223372036854775808]
; GFNISSE-NEXT: movdqa %xmm2, %xmm0
-; GFNISSE-NEXT: psrlw $7, %xmm0
-; GFNISSE-NEXT: movdqa {{.*#+}} xmm7 = [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1]
-; GFNISSE-NEXT: pand %xmm7, %xmm0
-; GFNISSE-NEXT: movdqa %xmm2, %xmm8
-; GFNISSE-NEXT: paddb %xmm2, %xmm8
-; GFNISSE-NEXT: por %xmm0, %xmm8
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm9, %xmm0
+; GFNISSE-NEXT: movdqa %xmm2, %xmm10
+; GFNISSE-NEXT: paddb %xmm2, %xmm10
+; GFNISSE-NEXT: por %xmm0, %xmm10
; GFNISSE-NEXT: paddb %xmm4, %xmm4
; GFNISSE-NEXT: movdqa %xmm4, %xmm0
-; GFNISSE-NEXT: pblendvb %xmm0, %xmm8, %xmm2
+; GFNISSE-NEXT: pblendvb %xmm0, %xmm10, %xmm2
; GFNISSE-NEXT: movdqa %xmm1, %xmm0
-; GFNISSE-NEXT: psrlw $4, %xmm0
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm5, %xmm0
; GFNISSE-NEXT: movdqa %xmm1, %xmm4
-; GFNISSE-NEXT: psllw $4, %xmm4
-; GFNISSE-NEXT: pand %xmm5, %xmm4
-; GFNISSE-NEXT: pandn %xmm0, %xmm5
-; GFNISSE-NEXT: por %xmm4, %xmm5
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm6, %xmm4
+; GFNISSE-NEXT: por %xmm0, %xmm4
; GFNISSE-NEXT: psllw $5, %xmm3
; GFNISSE-NEXT: movdqa %xmm3, %xmm0
-; GFNISSE-NEXT: pblendvb %xmm0, %xmm5, %xmm1
+; GFNISSE-NEXT: pblendvb %xmm0, %xmm4, %xmm1
; GFNISSE-NEXT: movdqa %xmm1, %xmm0
-; GFNISSE-NEXT: psrlw $6, %xmm0
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm7, %xmm0
; GFNISSE-NEXT: movdqa %xmm1, %xmm4
-; GFNISSE-NEXT: psllw $2, %xmm4
-; GFNISSE-NEXT: pand %xmm6, %xmm4
-; GFNISSE-NEXT: pandn %xmm0, %xmm6
-; GFNISSE-NEXT: por %xmm4, %xmm6
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm8, %xmm4
+; GFNISSE-NEXT: por %xmm0, %xmm4
; GFNISSE-NEXT: paddb %xmm3, %xmm3
; GFNISSE-NEXT: movdqa %xmm3, %xmm0
-; GFNISSE-NEXT: pblendvb %xmm0, %xmm6, %xmm1
+; GFNISSE-NEXT: pblendvb %xmm0, %xmm4, %xmm1
; GFNISSE-NEXT: movdqa %xmm1, %xmm0
-; GFNISSE-NEXT: psrlw $7, %xmm0
-; GFNISSE-NEXT: pand %xmm7, %xmm0
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm9, %xmm0
; GFNISSE-NEXT: movdqa %xmm1, %xmm4
; GFNISSE-NEXT: paddb %xmm1, %xmm4
; GFNISSE-NEXT: por %xmm0, %xmm4
@@ -523,46 +473,43 @@ define <32 x i8> @var_rotl_v32i8(<32 x i8> %a, <32 x i8> %amt) nounwind {
; GFNIAVX1-LABEL: var_rotl_v32i8:
; GFNIAVX1: # %bb.0:
; GFNIAVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
-; GFNIAVX1-NEXT: vpsrlw $4, %xmm2, %xmm3
-; GFNIAVX1-NEXT: vbroadcastss {{.*#+}} xmm4 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240]
-; GFNIAVX1-NEXT: vpandn %xmm3, %xmm4, %xmm3
-; GFNIAVX1-NEXT: vpsllw $4, %xmm2, %xmm5
-; GFNIAVX1-NEXT: vpand %xmm4, %xmm5, %xmm5
+; GFNIAVX1-NEXT: vmovddup {{.*#+}} xmm3 = [1161999622361579520,1161999622361579520]
+; GFNIAVX1-NEXT: # xmm3 = mem[0,0]
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm3, %xmm2, %xmm4
+; GFNIAVX1-NEXT: vmovddup {{.*#+}} xmm5 = [16909320,16909320]
+; GFNIAVX1-NEXT: # xmm5 = mem[0,0]
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm5, %xmm2, %xmm6
+; GFNIAVX1-NEXT: vpor %xmm4, %xmm6, %xmm4
+; GFNIAVX1-NEXT: vextractf128 $1, %ymm1, %xmm6
+; GFNIAVX1-NEXT: vpsllw $5, %xmm6, %xmm6
+; GFNIAVX1-NEXT: vpblendvb %xmm6, %xmm4, %xmm2, %xmm2
+; GFNIAVX1-NEXT: vmovddup {{.*#+}} xmm4 = [4647714815446351872,4647714815446351872]
+; GFNIAVX1-NEXT: # xmm4 = mem[0,0]
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm4, %xmm2, %xmm7
+; GFNIAVX1-NEXT: vmovddup {{.*#+}} xmm8 = [1108169199648,1108169199648]
+; GFNIAVX1-NEXT: # xmm8 = mem[0,0]
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm8, %xmm2, %xmm9
+; GFNIAVX1-NEXT: vpor %xmm7, %xmm9, %xmm7
+; GFNIAVX1-NEXT: vpaddb %xmm6, %xmm6, %xmm6
+; GFNIAVX1-NEXT: vpblendvb %xmm6, %xmm7, %xmm2, %xmm2
+; GFNIAVX1-NEXT: vmovddup {{.*#+}} xmm7 = [9223372036854775808,9223372036854775808]
+; GFNIAVX1-NEXT: # xmm7 = mem[0,0]
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm7, %xmm2, %xmm9
+; GFNIAVX1-NEXT: vpaddb %xmm2, %xmm2, %xmm10
+; GFNIAVX1-NEXT: vpor %xmm9, %xmm10, %xmm9
+; GFNIAVX1-NEXT: vpaddb %xmm6, %xmm6, %xmm6
+; GFNIAVX1-NEXT: vpblendvb %xmm6, %xmm9, %xmm2, %xmm2
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm3, %xmm0, %xmm3
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm5, %xmm0, %xmm5
; GFNIAVX1-NEXT: vpor %xmm3, %xmm5, %xmm3
-; GFNIAVX1-NEXT: vextractf128 $1, %ymm1, %xmm5
-; GFNIAVX1-NEXT: vpsllw $5, %xmm5, %xmm5
-; GFNIAVX1-NEXT: vpblendvb %xmm5, %xmm3, %xmm2, %xmm2
-; GFNIAVX1-NEXT: vpsrlw $6, %xmm2, %xmm3
-; GFNIAVX1-NEXT: vbroadcastss {{.*#+}} xmm6 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252]
-; GFNIAVX1-NEXT: vpandn %xmm3, %xmm6, %xmm3
-; GFNIAVX1-NEXT: vpsllw $2, %xmm2, %xmm7
-; GFNIAVX1-NEXT: vpand %xmm6, %xmm7, %xmm7
-; GFNIAVX1-NEXT: vpor %xmm3, %xmm7, %xmm3
-; GFNIAVX1-NEXT: vpaddb %xmm5, %xmm5, %xmm5
-; GFNIAVX1-NEXT: vpblendvb %xmm5, %xmm3, %xmm2, %xmm2
-; GFNIAVX1-NEXT: vpsrlw $7, %xmm2, %xmm3
-; GFNIAVX1-NEXT: vbroadcastss {{.*#+}} xmm7 = [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1]
-; GFNIAVX1-NEXT: vpand %xmm7, %xmm3, %xmm3
-; GFNIAVX1-NEXT: vpaddb %xmm2, %xmm2, %xmm8
-; GFNIAVX1-NEXT: vpor %xmm3, %xmm8, %xmm3
-; GFNIAVX1-NEXT: vpaddb %xmm5, %xmm5, %xmm5
-; GFNIAVX1-NEXT: vpblendvb %xmm5, %xmm3, %xmm2, %xmm2
-; GFNIAVX1-NEXT: vpsrlw $4, %xmm0, %xmm3
-; GFNIAVX1-NEXT: vpandn %xmm3, %xmm4, %xmm3
-; GFNIAVX1-NEXT: vpsllw $4, %xmm0, %xmm5
-; GFNIAVX1-NEXT: vpand %xmm4, %xmm5, %xmm4
-; GFNIAVX1-NEXT: vpor %xmm3, %xmm4, %xmm3
; GFNIAVX1-NEXT: vpsllw $5, %xmm1, %xmm1
; GFNIAVX1-NEXT: vpblendvb %xmm1, %xmm3, %xmm0, %xmm0
-; GFNIAVX1-NEXT: vpsrlw $6, %xmm0, %xmm3
-; GFNIAVX1-NEXT: vpandn %xmm3, %xmm6, %xmm3
-; GFNIAVX1-NEXT: vpsllw $2, %xmm0, %xmm4
-; GFNIAVX1-NEXT: vpand %xmm6, %xmm4, %xmm4
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm4, %xmm0, %xmm3
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm8, %xmm0, %xmm4
; GFNIAVX1-NEXT: vpor %xmm3, %xmm4, %xmm3
; GFNIAVX1-NEXT: vpaddb %xmm1, %xmm1, %xmm1
; GFNIAVX1-NEXT: vpblendvb %xmm1, %xmm3, %xmm0, %xmm0
-; GFNIAVX1-NEXT: vpsrlw $7, %xmm0, %xmm3
-; GFNIAVX1-NEXT: vpand %xmm7, %xmm3, %xmm3
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm7, %xmm0, %xmm3
; GFNIAVX1-NEXT: vpaddb %xmm0, %xmm0, %xmm4
; GFNIAVX1-NEXT: vpor %xmm3, %xmm4, %xmm3
; GFNIAVX1-NEXT: vpaddb %xmm1, %xmm1, %xmm1
@@ -572,22 +519,22 @@ define <32 x i8> @var_rotl_v32i8(<32 x i8> %a, <32 x i8> %amt) nounwind {
;
; GFNIAVX2-LABEL: var_rotl_v32i8:
; GFNIAVX2: # %bb.0:
-; GFNIAVX2-NEXT: vpsrlw $4, %ymm0, %ymm2
-; GFNIAVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
-; GFNIAVX2-NEXT: vpsllw $4, %ymm0, %ymm3
-; GFNIAVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm3, %ymm3
+; GFNIAVX2-NEXT: vpbroadcastq {{.*#+}} ymm2 = [1161999622361579520,1161999622361579520,1161999622361579520,1161999622361579520]
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, %ymm2, %ymm0, %ymm2
+; GFNIAVX2-NEXT: vpbroadcastq {{.*#+}} ymm3 = [16909320,16909320,16909320,16909320]
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, %ymm3, %ymm0, %ymm3
; GFNIAVX2-NEXT: vpor %ymm2, %ymm3, %ymm2
; GFNIAVX2-NEXT: vpsllw $5, %ymm1, %ymm1
; GFNIAVX2-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
-; GFNIAVX2-NEXT: vpsrlw $6, %ymm0, %ymm2
-; GFNIAVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
-; GFNIAVX2-NEXT: vpsllw $2, %ymm0, %ymm3
-; GFNIAVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm3, %ymm3
+; GFNIAVX2-NEXT: vpbroadcastq {{.*#+}} ymm2 = [4647714815446351872,4647714815446351872,4647714815446351872,4647714815446351872]
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, %ymm2, %ymm0, %ymm2
+; GFNIAVX2-NEXT: vpbroadcastq {{.*#+}} ymm3 = [1108169199648,1108169199648,1108169199648,1108169199648]
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, %ymm3, %ymm0, %ymm3
; GFNIAVX2-NEXT: vpor %ymm2, %ymm3, %ymm2
; GFNIAVX2-NEXT: vpaddb %ymm1, %ymm1, %ymm1
; GFNIAVX2-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
-; GFNIAVX2-NEXT: vpsrlw $7, %ymm0, %ymm2
-; GFNIAVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
+; GFNIAVX2-NEXT: vpbroadcastq {{.*#+}} ymm2 = [9223372036854775808,9223372036854775808,9223372036854775808,9223372036854775808]
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, %ymm2, %ymm0, %ymm2
; GFNIAVX2-NEXT: vpaddb %ymm0, %ymm0, %ymm3
; GFNIAVX2-NEXT: vpor %ymm2, %ymm3, %ymm2
; GFNIAVX2-NEXT: vpaddb %ymm1, %ymm1, %ymm1
@@ -596,21 +543,21 @@ define <32 x i8> @var_rotl_v32i8(<32 x i8> %a, <32 x i8> %amt) nounwind {
;
; GFNIAVX512VL-LABEL: var_rotl_v32i8:
; GFNIAVX512VL: # %bb.0:
-; GFNIAVX512VL-NEXT: vpsllw $4, %ymm0, %ymm2
-; GFNIAVX512VL-NEXT: vpsrlw $4, %ymm0, %ymm3
-; GFNIAVX512VL-NEXT: vpternlogd $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm2, %ymm3
+; GFNIAVX512VL-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %ymm2
+; GFNIAVX512VL-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %ymm3
+; GFNIAVX512VL-NEXT: vpor %ymm2, %ymm3, %ymm2
; GFNIAVX512VL-NEXT: vpsllw $5, %ymm1, %ymm1
-; GFNIAVX512VL-NEXT: vpblendvb %ymm1, %ymm3, %ymm0, %ymm0
-; GFNIAVX512VL-NEXT: vpsllw $2, %ymm0, %ymm2
-; GFNIAVX512VL-NEXT: vpsrlw $6, %ymm0, %ymm3
-; GFNIAVX512VL-NEXT: vpternlogd $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm2, %ymm3
+; GFNIAVX512VL-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
+; GFNIAVX512VL-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %ymm2
+; GFNIAVX512VL-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %ymm3
+; GFNIAVX512VL-NEXT: vpor %ymm2, %ymm3, %ymm2
; GFNIAVX512VL-NEXT: vpaddb %ymm1, %ymm1, %ymm1
-; GFNIAVX512VL-NEXT: vpblendvb %ymm1, %ymm3, %ymm0, %ymm0
-; GFNIAVX512VL-NEXT: vpsrlw $7, %ymm0, %ymm2
+; GFNIAVX512VL-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
+; GFNIAVX512VL-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %ymm2
; GFNIAVX512VL-NEXT: vpaddb %ymm0, %ymm0, %ymm3
-; GFNIAVX512VL-NEXT: vpternlogd $248, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm2, %ymm3
+; GFNIAVX512VL-NEXT: vpor %ymm2, %ymm3, %ymm2
; GFNIAVX512VL-NEXT: vpaddb %ymm1, %ymm1, %ymm1
-; GFNIAVX512VL-NEXT: vpblendvb %ymm1, %ymm3, %ymm0, %ymm0
+; GFNIAVX512VL-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
; GFNIAVX512VL-NEXT: retq
;
; GFNIAVX512BW-LABEL: var_rotl_v32i8:
@@ -634,63 +581,53 @@ define <32 x i8> @var_rotr_v32i8(<32 x i8> %a, <32 x i8> %amt) nounwind {
; GFNISSE-LABEL: var_rotr_v32i8:
; GFNISSE: # %bb.0:
; GFNISSE-NEXT: movdqa %xmm0, %xmm5
-; GFNISSE-NEXT: psrlw $4, %xmm0
-; GFNISSE-NEXT: movdqa {{.*#+}} xmm6 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240]
-; GFNISSE-NEXT: movdqa %xmm6, %xmm4
-; GFNISSE-NEXT: pandn %xmm0, %xmm4
-; GFNISSE-NEXT: movdqa %xmm5, %xmm7
-; GFNISSE-NEXT: psllw $4, %xmm7
-; GFNISSE-NEXT: pand %xmm6, %xmm7
-; GFNISSE-NEXT: por %xmm4, %xmm7
+; GFNISSE-NEXT: movdqa {{.*#+}} xmm6 = [1161999622361579520,1161999622361579520]
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm6, %xmm0
+; GFNISSE-NEXT: pmovsxdq {{.*#+}} xmm7 = [16909320,16909320]
+; GFNISSE-NEXT: movdqa %xmm5, %xmm8
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm7, %xmm8
+; GFNISSE-NEXT: por %xmm0, %xmm8
; GFNISSE-NEXT: pxor %xmm4, %xmm4
; GFNISSE-NEXT: pxor %xmm0, %xmm0
; GFNISSE-NEXT: psubb %xmm2, %xmm0
; GFNISSE-NEXT: psllw $5, %xmm0
-; GFNISSE-NEXT: pblendvb %xmm0, %xmm7, %xmm5
-; GFNISSE-NEXT: movdqa %xmm5, %xmm7
-; GFNISSE-NEXT: psrlw $6, %xmm7
-; GFNISSE-NEXT: movdqa {{.*#+}} xmm2 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252]
-; GFNISSE-NEXT: movdqa %xmm2, %xmm8
-; GFNISSE-NEXT: pandn %xmm7, %xmm8
-; GFNISSE-NEXT: movdqa %xmm5, %xmm7
-; GFNISSE-NEXT: psllw $2, %xmm7
-; GFNISSE-NEXT: pand %xmm2, %xmm7
-; GFNISSE-NEXT: por %xmm8, %xmm7
-; GFNISSE-NEXT: paddb %xmm0, %xmm0
-; GFNISSE-NEXT: pblendvb %xmm0, %xmm7, %xmm5
-; GFNISSE-NEXT: movdqa %xmm5, %xmm8
-; GFNISSE-NEXT: psrlw $7, %xmm8
-; GFNISSE-NEXT: movdqa {{.*#+}} xmm7 = [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1]
-; GFNISSE-NEXT: pand %xmm7, %xmm8
+; GFNISSE-NEXT: pblendvb %xmm0, %xmm8, %xmm5
+; GFNISSE-NEXT: movdqa {{.*#+}} xmm2 = [4647714815446351872,4647714815446351872]
; GFNISSE-NEXT: movdqa %xmm5, %xmm9
-; GFNISSE-NEXT: paddb %xmm5, %xmm9
-; GFNISSE-NEXT: por %xmm8, %xmm9
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm2, %xmm9
+; GFNISSE-NEXT: movdqa {{.*#+}} xmm8 = [1108169199648,1108169199648]
+; GFNISSE-NEXT: movdqa %xmm5, %xmm10
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm8, %xmm10
+; GFNISSE-NEXT: por %xmm9, %xmm10
; GFNISSE-NEXT: paddb %xmm0, %xmm0
-; GFNISSE-NEXT: pblendvb %xmm0, %xmm9, %xmm5
+; GFNISSE-NEXT: pblendvb %xmm0, %xmm10, %xmm5
+; GFNISSE-NEXT: movdqa {{.*#+}} xmm9 = [9223372036854775808,9223372036854775808]
+; GFNISSE-NEXT: movdqa %xmm5, %xmm10
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm9, %xmm10
+; GFNISSE-NEXT: movdqa %xmm5, %xmm11
+; GFNISSE-NEXT: paddb %xmm5, %xmm11
+; GFNISSE-NEXT: por %xmm10, %xmm11
+; GFNISSE-NEXT: paddb %xmm0, %xmm0
+; GFNISSE-NEXT: pblendvb %xmm0, %xmm11, %xmm5
; GFNISSE-NEXT: movdqa %xmm1, %xmm0
-; GFNISSE-NEXT: psrlw $4, %xmm0
-; GFNISSE-NEXT: movdqa %xmm1, %xmm8
-; GFNISSE-NEXT: psllw $4, %xmm8
-; GFNISSE-NEXT: pand %xmm6, %xmm8
-; GFNISSE-NEXT: pandn %xmm0, %xmm6
-; GFNISSE-NEXT: por %xmm8, %xmm6
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm6, %xmm0
+; GFNISSE-NEXT: movdqa %xmm1, %xmm6
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm7, %xmm6
+; GFNISSE-NEXT: por %xmm0, %xmm6
; GFNISSE-NEXT: psubb %xmm3, %xmm4
; GFNISSE-NEXT: psllw $5, %xmm4
; GFNISSE-NEXT: movdqa %xmm4, %xmm0
; GFNISSE-NEXT: pblendvb %xmm0, %xmm6, %xmm1
; GFNISSE-NEXT: movdqa %xmm1, %xmm0
-; GFNISSE-NEXT: psrlw $6, %xmm0
-; GFNISSE-NEXT: movdqa %xmm1, %xmm3
-; GFNISSE-NEXT: psllw $2, %xmm3
-; GFNISSE-NEXT: pand %xmm2, %xmm3
-; GFNISSE-NEXT: pandn %xmm0, %xmm2
-; GFNISSE-NEXT: por %xmm3, %xmm2
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm2, %xmm0
+; GFNISSE-NEXT: movdqa %xmm1, %xmm2
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm8, %xmm2
+; GFNISSE-NEXT: por %xmm0, %xmm2
; GFNISSE-NEXT: paddb %xmm4, %xmm4
; GFNISSE-NEXT: movdqa %xmm4, %xmm0
; GFNISSE-NEXT: pblendvb %xmm0, %xmm2, %xmm1
; GFNISSE-NEXT: movdqa %xmm1, %xmm0
-; GFNISSE-NEXT: psrlw $7, %xmm0
-; GFNISSE-NEXT: pand %xmm7, %xmm0
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm9, %xmm0
; GFNISSE-NEXT: movdqa %xmm1, %xmm2
; GFNISSE-NEXT: paddb %xmm1, %xmm2
; GFNISSE-NEXT: por %xmm0, %xmm2
@@ -703,49 +640,46 @@ define <32 x i8> @var_rotr_v32i8(<32 x i8> %a, <32 x i8> %amt) nounwind {
; GFNIAVX1-LABEL: var_rotr_v32i8:
; GFNIAVX1: # %bb.0:
; GFNIAVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
-; GFNIAVX1-NEXT: vpsrlw $4, %xmm2, %xmm3
-; GFNIAVX1-NEXT: vbroadcastss {{.*#+}} xmm4 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240]
-; GFNIAVX1-NEXT: vpandn %xmm3, %xmm4, %xmm3
-; GFNIAVX1-NEXT: vpsllw $4, %xmm2, %xmm5
-; GFNIAVX1-NEXT: vpand %xmm4, %xmm5, %xmm5
+; GFNIAVX1-NEXT: vmovddup {{.*#+}} xmm3 = [1161999622361579520,1161999622361579520]
+; GFNIAVX1-NEXT: # xmm3 = mem[0,0]
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm3, %xmm2, %xmm4
+; GFNIAVX1-NEXT: vmovddup {{.*#+}} xmm5 = [16909320,16909320]
+; GFNIAVX1-NEXT: # xmm5 = mem[0,0]
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm5, %xmm2, %xmm6
+; GFNIAVX1-NEXT: vpor %xmm4, %xmm6, %xmm4
+; GFNIAVX1-NEXT: vextractf128 $1, %ymm1, %xmm6
+; GFNIAVX1-NEXT: vpxor %xmm7, %xmm7, %xmm7
+; GFNIAVX1-NEXT: vpsubb %xmm6, %xmm7, %xmm6
+; GFNIAVX1-NEXT: vpsllw $5, %xmm6, %xmm6
+; GFNIAVX1-NEXT: vpblendvb %xmm6, %xmm4, %xmm2, %xmm2
+; GFNIAVX1-NEXT: vmovddup {{.*#+}} xmm4 = [4647714815446351872,4647714815446351872]
+; GFNIAVX1-NEXT: # xmm4 = mem[0,0]
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm4, %xmm2, %xmm8
+; GFNIAVX1-NEXT: vmovddup {{.*#+}} xmm9 = [1108169199648,1108169199648]
+; GFNIAVX1-NEXT: # xmm9 = mem[0,0]
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm9, %xmm2, %xmm10
+; GFNIAVX1-NEXT: vpor %xmm8, %xmm10, %xmm8
+; GFNIAVX1-NEXT: vpaddb %xmm6, %xmm6, %xmm6
+; GFNIAVX1-NEXT: vpblendvb %xmm6, %xmm8, %xmm2, %xmm2
+; GFNIAVX1-NEXT: vmovddup {{.*#+}} xmm8 = [9223372036854775808,9223372036854775808]
+; GFNIAVX1-NEXT: # xmm8 = mem[0,0]
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm8, %xmm2, %xmm10
+; GFNIAVX1-NEXT: vpaddb %xmm2, %xmm2, %xmm11
+; GFNIAVX1-NEXT: vpor %xmm10, %xmm11, %xmm10
+; GFNIAVX1-NEXT: vpaddb %xmm6, %xmm6, %xmm6
+; GFNIAVX1-NEXT: vpblendvb %xmm6, %xmm10, %xmm2, %xmm2
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm3, %xmm0, %xmm3
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm5, %xmm0, %xmm5
; GFNIAVX1-NEXT: vpor %xmm3, %xmm5, %xmm3
-; GFNIAVX1-NEXT: vextractf128 $1, %ymm1, %xmm5
-; GFNIAVX1-NEXT: vpxor %xmm6, %xmm6, %xmm6
-; GFNIAVX1-NEXT: vpsubb %xmm5, %xmm6, %xmm5
-; GFNIAVX1-NEXT: vpsllw $5, %xmm5, %xmm5
-; GFNIAVX1-NEXT: vpblendvb %xmm5, %xmm3, %xmm2, %xmm2
-; GFNIAVX1-NEXT: vpsrlw $6, %xmm2, %xmm3
-; GFNIAVX1-NEXT: vbroadcastss {{.*#+}} xmm7 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252]
-; GFNIAVX1-NEXT: vpandn %xmm3, %xmm7, %xmm3
-; GFNIAVX1-NEXT: vpsllw $2, %xmm2, %xmm8
-; GFNIAVX1-NEXT: vpand %xmm7, %xmm8, %xmm8
-; GFNIAVX1-NEXT: vpor %xmm3, %xmm8, %xmm3
-; GFNIAVX1-NEXT: vpaddb %xmm5, %xmm5, %xmm5
-; GFNIAVX1-NEXT: vpblendvb %xmm5, %xmm3, %xmm2, %xmm2
-; GFNIAVX1-NEXT: vpsrlw $7, %xmm2, %xmm3
-; GFNIAVX1-NEXT: vbroadcastss {{.*#+}} xmm8 = [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1]
-; GFNIAVX1-NEXT: vpand %xmm3, %xmm8, %xmm3
-; GFNIAVX1-NEXT: vpaddb %xmm2, %xmm2, %xmm9
-; GFNIAVX1-NEXT: vpor %xmm3, %xmm9, %xmm3
-; GFNIAVX1-NEXT: vpaddb %xmm5, %xmm5, %xmm5
-; GFNIAVX1-NEXT: vpblendvb %xmm5, %xmm3, %xmm2, %xmm2
-; GFNIAVX1-NEXT: vpsrlw $4, %xmm0, %xmm3
-; GFNIAVX1-NEXT: vpandn %xmm3, %xmm4, %xmm3
-; GFNIAVX1-NEXT: vpsllw $4, %xmm0, %xmm5
-; GFNIAVX1-NEXT: vpand %xmm4, %xmm5, %xmm4
-; GFNIAVX1-NEXT: vpor %xmm3, %xmm4, %xmm3
-; GFNIAVX1-NEXT: vpsubb %xmm1, %xmm6, %xmm1
+; GFNIAVX1-NEXT: vpsubb %xmm1, %xmm7, %xmm1
; GFNIAVX1-NEXT: vpsllw $5, %xmm1, %xmm1
; GFNIAVX1-NEXT: vpblendvb %xmm1, %xmm3, %xmm0, %xmm0
-; GFNIAVX1-NEXT: vpsrlw $6, %xmm0, %xmm3
-; GFNIAVX1-NEXT: vpandn %xmm3, %xmm7, %xmm3
-; GFNIAVX1-NEXT: vpsllw $2, %xmm0, %xmm4
-; GFNIAVX1-NEXT: vpand %xmm7, %xmm4, %xmm4
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm4, %xmm0, %xmm3
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm9, %xmm0, %xmm4
; GFNIAVX1-NEXT: vpor %xmm3, %xmm4, %xmm3
; GFNIAVX1-NEXT: vpaddb %xmm1, %xmm1, %xmm1
; GFNIAVX1-NEXT: vpblendvb %xmm1, %xmm3, %xmm0, %xmm0
-; GFNIAVX1-NEXT: vpsrlw $7, %xmm0, %xmm3
-; GFNIAVX1-NEXT: vpand %xmm3, %xmm8, %xmm3
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm8, %xmm0, %xmm3
; GFNIAVX1-NEXT: vpaddb %xmm0, %xmm0, %xmm4
; GFNIAVX1-NEXT: vpor %xmm3, %xmm4, %xmm3
; GFNIAVX1-NEXT: vpaddb %xmm1, %xmm1, %xmm1
@@ -755,24 +689,24 @@ define <32 x i8> @var_rotr_v32i8(<32 x i8> %a, <32 x i8> %amt) nounwind {
;
; GFNIAVX2-LABEL: var_rotr_v32i8:
; GFNIAVX2: # %bb.0:
-; GFNIAVX2-NEXT: vpsrlw $4, %ymm0, %ymm2
-; GFNIAVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
-; GFNIAVX2-NEXT: vpsllw $4, %ymm0, %ymm3
-; GFNIAVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm3, %ymm3
+; GFNIAVX2-NEXT: vpbroadcastq {{.*#+}} ymm2 = [1161999622361579520,1161999622361579520,1161999622361579520,1161999622361579520]
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, %ymm2, %ymm0, %ymm2
+; GFNIAVX2-NEXT: vpbroadcastq {{.*#+}} ymm3 = [16909320,16909320,16909320,16909320]
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, %ymm3, %ymm0, %ymm3
; GFNIAVX2-NEXT: vpor %ymm2, %ymm3, %ymm2
; GFNIAVX2-NEXT: vpxor %xmm3, %xmm3, %xmm3
; GFNIAVX2-NEXT: vpsubb %ymm1, %ymm3, %ymm1
; GFNIAVX2-NEXT: vpsllw $5, %ymm1, %ymm1
; GFNIAVX2-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
-; GFNIAVX2-NEXT: vpsrlw $6, %ymm0, %ymm2
-; GFNIAVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
-; GFNIAVX2-NEXT: vpsllw $2, %ymm0, %ymm3
-; GFNIAVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm3, %ymm3
+; GFNIAVX2-NEXT: vpbroadcastq {{.*#+}} ymm2 = [4647714815446351872,4647714815446351872,4647714815446351872,4647714815446351872]
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, %ymm2, %ymm0, %ymm2
+; GFNIAVX2-NEXT: vpbroadcastq {{.*#+}} ymm3 = [1108169199648,1108169199648,1108169199648,1108169199648]
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, %ymm3, %ymm0, %ymm3
; GFNIAVX2-NEXT: vpor %ymm2, %ymm3, %ymm2
; GFNIAVX2-NEXT: vpaddb %ymm1, %ymm1, %ymm1
; GFNIAVX2-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
-; GFNIAVX2-NEXT: vpsrlw $7, %ymm0, %ymm2
-; GFNIAVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
+; GFNIAVX2-NEXT: vpbroadcastq {{.*#+}} ymm2 = [9223372036854775808,9223372036854775808,9223372036854775808,9223372036854775808]
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, %ymm2, %ymm0, %ymm2
; GFNIAVX2-NEXT: vpaddb %ymm0, %ymm0, %ymm3
; GFNIAVX2-NEXT: vpor %ymm2, %ymm3, %ymm2
; GFNIAVX2-NEXT: vpaddb %ymm1, %ymm1, %ymm1
@@ -781,21 +715,21 @@ define <32 x i8> @var_rotr_v32i8(<32 x i8> %a, <32 x i8> %amt) nounwind {
;
; GFNIAVX512VL-LABEL: var_rotr_v32i8:
; GFNIAVX512VL: # %bb.0:
-; GFNIAVX512VL-NEXT: vpsrlw $4, %ymm0, %ymm2
-; GFNIAVX512VL-NEXT: vpsllw $4, %ymm0, %ymm3
-; GFNIAVX512VL-NEXT: vpternlogd $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm2, %ymm3
+; GFNIAVX512VL-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %ymm2
+; GFNIAVX512VL-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %ymm3
+; GFNIAVX512VL-NEXT: vpor %ymm2, %ymm3, %ymm2
; GFNIAVX512VL-NEXT: vpsllw $5, %ymm1, %ymm1
-; GFNIAVX512VL-NEXT: vpblendvb %ymm1, %ymm3, %ymm0, %ymm0
-; GFNIAVX512VL-NEXT: vpsrlw $2, %ymm0, %ymm2
-; GFNIAVX512VL-NEXT: vpsllw $6, %ymm0, %ymm3
-; GFNIAVX512VL-NEXT: vpternlogd $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm2, %ymm3
+; GFNIAVX512VL-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
+; GFNIAVX512VL-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %ymm2
+; GFNIAVX512VL-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %ymm3
+; GFNIAVX512VL-NEXT: vpor %ymm2, %ymm3, %ymm2
; GFNIAVX512VL-NEXT: vpaddb %ymm1, %ymm1, %ymm1
-; GFNIAVX512VL-NEXT: vpblendvb %ymm1, %ymm3, %ymm0, %ymm0
-; GFNIAVX512VL-NEXT: vpsrlw $1, %ymm0, %ymm2
-; GFNIAVX512VL-NEXT: vpsllw $7, %ymm0, %ymm3
-; GFNIAVX512VL-NEXT: vpternlogd $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm2, %ymm3
+; GFNIAVX512VL-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
+; GFNIAVX512VL-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %ymm2
+; GFNIAVX512VL-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %ymm3
+; GFNIAVX512VL-NEXT: vpor %ymm2, %ymm3, %ymm2
; GFNIAVX512VL-NEXT: vpaddb %ymm1, %ymm1, %ymm1
-; GFNIAVX512VL-NEXT: vpblendvb %ymm1, %ymm3, %ymm0, %ymm0
+; GFNIAVX512VL-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
; GFNIAVX512VL-NEXT: retq
;
; GFNIAVX512BW-LABEL: var_rotr_v32i8:
@@ -1141,53 +1075,25 @@ define <32 x i8> @constant_rotr_v32i8(<32 x i8> %a) nounwind {
define <32 x i8> @splatconstant_rotl_v32i8(<32 x i8> %a) nounwind {
; GFNISSE-LABEL: splatconstant_rotl_v32i8:
; GFNISSE: # %bb.0:
-; GFNISSE-NEXT: movdqa %xmm0, %xmm2
-; GFNISSE-NEXT: psrlw $4, %xmm2
-; GFNISSE-NEXT: movdqa {{.*#+}} xmm3 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240]
-; GFNISSE-NEXT: movdqa %xmm3, %xmm4
-; GFNISSE-NEXT: pandn %xmm2, %xmm4
-; GFNISSE-NEXT: psllw $4, %xmm0
-; GFNISSE-NEXT: pand %xmm3, %xmm0
-; GFNISSE-NEXT: por %xmm4, %xmm0
-; GFNISSE-NEXT: movdqa %xmm1, %xmm2
-; GFNISSE-NEXT: psrlw $4, %xmm2
-; GFNISSE-NEXT: psllw $4, %xmm1
-; GFNISSE-NEXT: pand %xmm3, %xmm1
-; GFNISSE-NEXT: pandn %xmm2, %xmm3
-; GFNISSE-NEXT: por %xmm3, %xmm1
+; GFNISSE-NEXT: movdqa {{.*#+}} xmm2 = [1161999622378488840,1161999622378488840]
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm2, %xmm0
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm2, %xmm1
; GFNISSE-NEXT: retq
;
; GFNIAVX1-LABEL: splatconstant_rotl_v32i8:
; GFNIAVX1: # %bb.0:
-; GFNIAVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
-; GFNIAVX1-NEXT: vpsrlw $4, %xmm1, %xmm2
-; GFNIAVX1-NEXT: vbroadcastss {{.*#+}} xmm3 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240]
-; GFNIAVX1-NEXT: vpandn %xmm2, %xmm3, %xmm2
-; GFNIAVX1-NEXT: vpsllw $4, %xmm1, %xmm1
-; GFNIAVX1-NEXT: vpand %xmm3, %xmm1, %xmm1
-; GFNIAVX1-NEXT: vpor %xmm2, %xmm1, %xmm1
-; GFNIAVX1-NEXT: vpsrlw $4, %xmm0, %xmm2
-; GFNIAVX1-NEXT: vpandn %xmm2, %xmm3, %xmm2
-; GFNIAVX1-NEXT: vpsllw $4, %xmm0, %xmm0
-; GFNIAVX1-NEXT: vpand %xmm3, %xmm0, %xmm0
-; GFNIAVX1-NEXT: vpor %xmm2, %xmm0, %xmm0
-; GFNIAVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; GFNIAVX1-NEXT: retq
;
; GFNIAVX2-LABEL: splatconstant_rotl_v32i8:
; GFNIAVX2: # %bb.0:
-; GFNIAVX2-NEXT: vpsrlw $4, %ymm0, %ymm1
-; GFNIAVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
-; GFNIAVX2-NEXT: vpsllw $4, %ymm0, %ymm0
-; GFNIAVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
-; GFNIAVX2-NEXT: vpor %ymm1, %ymm0, %ymm0
+; GFNIAVX2-NEXT: vpbroadcastq {{.*#+}} ymm1 = [1161999622378488840,1161999622378488840,1161999622378488840,1161999622378488840]
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, %ymm1, %ymm0, %ymm0
; GFNIAVX2-NEXT: retq
;
; GFNIAVX512-LABEL: splatconstant_rotl_v32i8:
; GFNIAVX512: # %bb.0:
-; GFNIAVX512-NEXT: vpsllw $4, %ymm0, %ymm1
-; GFNIAVX512-NEXT: vpsrlw $4, %ymm0, %ymm0
-; GFNIAVX512-NEXT: vpternlogd $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm1, %ymm0
+; GFNIAVX512-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %ymm0
; GFNIAVX512-NEXT: retq
%res = call <32 x i8> @llvm.fshl.v32i8(<32 x i8> %a, <32 x i8> %a, <32 x i8> <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4>)
ret <32 x i8> %res
@@ -1197,53 +1103,25 @@ declare <32 x i8> @llvm.fshl.v32i8(<32 x i8>, <32 x i8>, <32 x i8>)
define <32 x i8> @splatconstant_rotr_v32i8(<32 x i8> %a) nounwind {
; GFNISSE-LABEL: splatconstant_rotr_v32i8:
; GFNISSE: # %bb.0:
-; GFNISSE-NEXT: movdqa %xmm0, %xmm2
-; GFNISSE-NEXT: psrlw $6, %xmm2
-; GFNISSE-NEXT: movdqa {{.*#+}} xmm3 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252]
-; GFNISSE-NEXT: movdqa %xmm3, %xmm4
-; GFNISSE-NEXT: pandn %xmm2, %xmm4
-; GFNISSE-NEXT: psllw $2, %xmm0
-; GFNISSE-NEXT: pand %xmm3, %xmm0
-; GFNISSE-NEXT: por %xmm4, %xmm0
-; GFNISSE-NEXT: movdqa %xmm1, %xmm2
-; GFNISSE-NEXT: psrlw $6, %xmm2
-; GFNISSE-NEXT: psllw $2, %xmm1
-; GFNISSE-NEXT: pand %xmm3, %xmm1
-; GFNISSE-NEXT: pandn %xmm2, %xmm3
-; GFNISSE-NEXT: por %xmm3, %xmm1
+; GFNISSE-NEXT: movdqa {{.*#+}} xmm2 = [4647715923615551520,4647715923615551520]
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm2, %xmm0
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm2, %xmm1
; GFNISSE-NEXT: retq
;
; GFNIAVX1-LABEL: splatconstant_rotr_v32i8:
; GFNIAVX1: # %bb.0:
-; GFNIAVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
-; GFNIAVX1-NEXT: vpsrlw $6, %xmm1, %xmm2
-; GFNIAVX1-NEXT: vbroadcastss {{.*#+}} xmm3 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252]
-; GFNIAVX1-NEXT: vpandn %xmm2, %xmm3, %xmm2
-; GFNIAVX1-NEXT: vpsllw $2, %xmm1, %xmm1
-; GFNIAVX1-NEXT: vpand %xmm3, %xmm1, %xmm1
-; GFNIAVX1-NEXT: vpor %xmm2, %xmm1, %xmm1
-; GFNIAVX1-NEXT: vpsrlw $6, %xmm0, %xmm2
-; GFNIAVX1-NEXT: vpandn %xmm2, %xmm3, %xmm2
-; GFNIAVX1-NEXT: vpsllw $2, %xmm0, %xmm0
-; GFNIAVX1-NEXT: vpand %xmm3, %xmm0, %xmm0
-; GFNIAVX1-NEXT: vpor %xmm2, %xmm0, %xmm0
-; GFNIAVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; GFNIAVX1-NEXT: retq
;
; GFNIAVX2-LABEL: splatconstant_rotr_v32i8:
; GFNIAVX2: # %bb.0:
-; GFNIAVX2-NEXT: vpsrlw $6, %ymm0, %ymm1
-; GFNIAVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
-; GFNIAVX2-NEXT: vpsllw $2, %ymm0, %ymm0
-; GFNIAVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
-; GFNIAVX2-NEXT: vpor %ymm1, %ymm0, %ymm0
+; GFNIAVX2-NEXT: vpbroadcastq {{.*#+}} ymm1 = [4647715923615551520,4647715923615551520,4647715923615551520,4647715923615551520]
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, %ymm1, %ymm0, %ymm0
; GFNIAVX2-NEXT: retq
;
; GFNIAVX512-LABEL: splatconstant_rotr_v32i8:
; GFNIAVX512: # %bb.0:
-; GFNIAVX512-NEXT: vpsllw $2, %ymm0, %ymm1
-; GFNIAVX512-NEXT: vpsrlw $6, %ymm0, %ymm0
-; GFNIAVX512-NEXT: vpternlogd $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm1, %ymm0
+; GFNIAVX512-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %ymm0
; GFNIAVX512-NEXT: retq
%res = call <32 x i8> @llvm.fshr.v32i8(<32 x i8> %a, <32 x i8> %a, <32 x i8> <i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6>)
ret <32 x i8> %res
@@ -1259,64 +1137,52 @@ define <64 x i8> @var_rotl_v64i8(<64 x i8> %a, <64 x i8> %amt) nounwind {
; GFNISSE: # %bb.0:
; GFNISSE-NEXT: movdqa %xmm4, %xmm8
; GFNISSE-NEXT: movdqa %xmm0, %xmm4
-; GFNISSE-NEXT: psrlw $4, %xmm0
-; GFNISSE-NEXT: movdqa {{.*#+}} xmm9 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240]
-; GFNISSE-NEXT: movdqa %xmm9, %xmm10
-; GFNISSE-NEXT: pandn %xmm0, %xmm10
+; GFNISSE-NEXT: movdqa {{.*#+}} xmm9 = [1161999622361579520,1161999622361579520]
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm9, %xmm0
+; GFNISSE-NEXT: pmovsxdq {{.*#+}} xmm10 = [16909320,16909320]
; GFNISSE-NEXT: movdqa %xmm4, %xmm11
-; GFNISSE-NEXT: psllw $4, %xmm11
-; GFNISSE-NEXT: pand %xmm9, %xmm11
-; GFNISSE-NEXT: por %xmm10, %xmm11
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm10, %xmm11
+; GFNISSE-NEXT: por %xmm0, %xmm11
; GFNISSE-NEXT: psllw $5, %xmm8
; GFNISSE-NEXT: movdqa %xmm8, %xmm0
; GFNISSE-NEXT: pblendvb %xmm0, %xmm11, %xmm4
+; GFNISSE-NEXT: movdqa {{.*#+}} xmm11 = [4647714815446351872,4647714815446351872]
; GFNISSE-NEXT: movdqa %xmm4, %xmm0
-; GFNISSE-NEXT: psrlw $6, %xmm0
-; GFNISSE-NEXT: movdqa {{.*#+}} xmm10 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252]
-; GFNISSE-NEXT: movdqa %xmm10, %xmm11
-; GFNISSE-NEXT: pandn %xmm0, %xmm11
-; GFNISSE-NEXT: movdqa %xmm4, %xmm12
-; GFNISSE-NEXT: psllw $2, %xmm12
-; GFNISSE-NEXT: pand %xmm10, %xmm12
-; GFNISSE-NEXT: por %xmm11, %xmm12
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm11, %xmm0
+; GFNISSE-NEXT: movdqa {{.*#+}} xmm12 = [1108169199648,1108169199648]
+; GFNISSE-NEXT: movdqa %xmm4, %xmm13
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm12, %xmm13
+; GFNISSE-NEXT: por %xmm0, %xmm13
; GFNISSE-NEXT: paddb %xmm8, %xmm8
; GFNISSE-NEXT: movdqa %xmm8, %xmm0
-; GFNISSE-NEXT: pblendvb %xmm0, %xmm12, %xmm4
+; GFNISSE-NEXT: pblendvb %xmm0, %xmm13, %xmm4
+; GFNISSE-NEXT: movdqa {{.*#+}} xmm13 = [9223372036854775808,9223372036854775808]
; GFNISSE-NEXT: movdqa %xmm4, %xmm0
-; GFNISSE-NEXT: psrlw $7, %xmm0
-; GFNISSE-NEXT: movdqa {{.*#+}} xmm11 = [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1]
-; GFNISSE-NEXT: pand %xmm11, %xmm0
-; GFNISSE-NEXT: movdqa %xmm4, %xmm12
-; GFNISSE-NEXT: paddb %xmm4, %xmm12
-; GFNISSE-NEXT: por %xmm0, %xmm12
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm13, %xmm0
+; GFNISSE-NEXT: movdqa %xmm4, %xmm14
+; GFNISSE-NEXT: paddb %xmm4, %xmm14
+; GFNISSE-NEXT: por %xmm0, %xmm14
; GFNISSE-NEXT: paddb %xmm8, %xmm8
; GFNISSE-NEXT: movdqa %xmm8, %xmm0
-; GFNISSE-NEXT: pblendvb %xmm0, %xmm12, %xmm4
+; GFNISSE-NEXT: pblendvb %xmm0, %xmm14, %xmm4
; GFNISSE-NEXT: movdqa %xmm1, %xmm0
-; GFNISSE-NEXT: psrlw $4, %xmm0
-; GFNISSE-NEXT: movdqa %xmm9, %xmm8
-; GFNISSE-NEXT: pandn %xmm0, %xmm8
-; GFNISSE-NEXT: movdqa %xmm1, %xmm12
-; GFNISSE-NEXT: psllw $4, %xmm12
-; GFNISSE-NEXT: pand %xmm9, %xmm12
-; GFNISSE-NEXT: por %xmm8, %xmm12
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm9, %xmm0
+; GFNISSE-NEXT: movdqa %xmm1, %xmm8
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm10, %xmm8
+; GFNISSE-NEXT: por %xmm0, %xmm8
; GFNISSE-NEXT: psllw $5, %xmm5
; GFNISSE-NEXT: movdqa %xmm5, %xmm0
-; GFNISSE-NEXT: pblendvb %xmm0, %xmm12, %xmm1
+; GFNISSE-NEXT: pblendvb %xmm0, %xmm8, %xmm1
; GFNISSE-NEXT: movdqa %xmm1, %xmm0
-; GFNISSE-NEXT: psrlw $6, %xmm0
-; GFNISSE-NEXT: movdqa %xmm10, %xmm8
-; GFNISSE-NEXT: pandn %xmm0, %xmm8
-; GFNISSE-NEXT: movdqa %xmm1, %xmm12
-; GFNISSE-NEXT: psllw $2, %xmm12
-; GFNISSE-NEXT: pand %xmm10, %xmm12
-; GFNISSE-NEXT: por %xmm8, %xmm12
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm11, %xmm0
+; GFNISSE-NEXT: movdqa %xmm1, %xmm8
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm12, %xmm8
+; GFNISSE-NEXT: por %xmm0, %xmm8
; GFNISSE-NEXT: paddb %xmm5, %xmm5
; GFNISSE-NEXT: movdqa %xmm5, %xmm0
-; GFNISSE-NEXT: pblendvb %xmm0, %xmm12, %xmm1
+; GFNISSE-NEXT: pblendvb %xmm0, %xmm8, %xmm1
; GFNISSE-NEXT: movdqa %xmm1, %xmm0
-; GFNISSE-NEXT: psrlw $7, %xmm0
-; GFNISSE-NEXT: pand %xmm11, %xmm0
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm13, %xmm0
; GFNISSE-NEXT: movdqa %xmm1, %xmm8
; GFNISSE-NEXT: paddb %xmm1, %xmm8
; GFNISSE-NEXT: por %xmm0, %xmm8
@@ -1324,30 +1190,23 @@ define <64 x i8> @var_rotl_v64i8(<64 x i8> %a, <64 x i8> %amt) nounwind {
; GFNISSE-NEXT: movdqa %xmm5, %xmm0
; GFNISSE-NEXT: pblendvb %xmm0, %xmm8, %xmm1
; GFNISSE-NEXT: movdqa %xmm2, %xmm0
-; GFNISSE-NEXT: psrlw $4, %xmm0
-; GFNISSE-NEXT: movdqa %xmm9, %xmm5
-; GFNISSE-NEXT: pandn %xmm0, %xmm5
-; GFNISSE-NEXT: movdqa %xmm2, %xmm8
-; GFNISSE-NEXT: psllw $4, %xmm8
-; GFNISSE-NEXT: pand %xmm9, %xmm8
-; GFNISSE-NEXT: por %xmm5, %xmm8
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm9, %xmm0
+; GFNISSE-NEXT: movdqa %xmm2, %xmm5
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm10, %xmm5
+; GFNISSE-NEXT: por %xmm0, %xmm5
; GFNISSE-NEXT: psllw $5, %xmm6
; GFNISSE-NEXT: movdqa %xmm6, %xmm0
-; GFNISSE-NEXT: pblendvb %xmm0, %xmm8, %xmm2
+; GFNISSE-NEXT: pblendvb %xmm0, %xmm5, %xmm2
; GFNISSE-NEXT: movdqa %xmm2, %xmm0
-; GFNISSE-NEXT: psrlw $6, %xmm0
-; GFNISSE-NEXT: movdqa %xmm10, %xmm5
-; GFNISSE-NEXT: pandn %xmm0, %xmm5
-; GFNISSE-NEXT: movdqa %xmm2, %xmm8
-; GFNISSE-NEXT: psllw $2, %xmm8
-; GFNISSE-NEXT: pand %xmm10, %xmm8
-; GFNISSE-NEXT: por %xmm5, %xmm8
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm11, %xmm0
+; GFNISSE-NEXT: movdqa %xmm2, %xmm5
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm12, %xmm5
+; GFNISSE-NEXT: por %xmm0, %xmm5
; GFNISSE-NEXT: paddb %xmm6, %xmm6
; GFNISSE-NEXT: movdqa %xmm6, %xmm0
-; GFNISSE-NEXT: pblendvb %xmm0, %xmm8, %xmm2
+; GFNISSE-NEXT: pblendvb %xmm0, %xmm5, %xmm2
; GFNISSE-NEXT: movdqa %xmm2, %xmm0
-; GFNISSE-NEXT: psrlw $7, %xmm0
-; GFNISSE-NEXT: pand %xmm11, %xmm0
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm13, %xmm0
; GFNISSE-NEXT: movdqa %xmm2, %xmm5
; GFNISSE-NEXT: paddb %xmm2, %xmm5
; GFNISSE-NEXT: por %xmm0, %xmm5
@@ -1355,28 +1214,23 @@ define <64 x i8> @var_rotl_v64i8(<64 x i8> %a, <64 x i8> %amt) nounwind {
; GFNISSE-NEXT: movdqa %xmm6, %xmm0
; GFNISSE-NEXT: pblendvb %xmm0, %xmm5, %xmm2
; GFNISSE-NEXT: movdqa %xmm3, %xmm0
-; GFNISSE-NEXT: psrlw $4, %xmm0
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm9, %xmm0
; GFNISSE-NEXT: movdqa %xmm3, %xmm5
-; GFNISSE-NEXT: psllw $4, %xmm5
-; GFNISSE-NEXT: pand %xmm9, %xmm5
-; GFNISSE-NEXT: pandn %xmm0, %xmm9
-; GFNISSE-NEXT: por %xmm5, %xmm9
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm10, %xmm5
+; GFNISSE-NEXT: por %xmm0, %xmm5
; GFNISSE-NEXT: psllw $5, %xmm7
; GFNISSE-NEXT: movdqa %xmm7, %xmm0
-; GFNISSE-NEXT: pblendvb %xmm0, %xmm9, %xmm3
+; GFNISSE-NEXT: pblendvb %xmm0, %xmm5, %xmm3
; GFNISSE-NEXT: movdqa %xmm3, %xmm0
-; GFNISSE-NEXT: psrlw $6, %xmm0
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm11, %xmm0
; GFNISSE-NEXT: movdqa %xmm3, %xmm5
-; GFNISSE-NEXT: psllw $2, %xmm5
-; GFNISSE-NEXT: pand %xmm10, %xmm5
-; GFNISSE-NEXT: pandn %xmm0, %xmm10
-; GFNISSE-NEXT: por %xmm5, %xmm10
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm12, %xmm5
+; GFNISSE-NEXT: por %xmm0, %xmm5
; GFNISSE-NEXT: paddb %xmm7, %xmm7
; GFNISSE-NEXT: movdqa %xmm7, %xmm0
-; GFNISSE-NEXT: pblendvb %xmm0, %xmm10, %xmm3
+; GFNISSE-NEXT: pblendvb %xmm0, %xmm5, %xmm3
; GFNISSE-NEXT: movdqa %xmm3, %xmm0
-; GFNISSE-NEXT: psrlw $7, %xmm0
-; GFNISSE-NEXT: pand %xmm11, %xmm0
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm13, %xmm0
; GFNISSE-NEXT: movdqa %xmm3, %xmm5
; GFNISSE-NEXT: paddb %xmm3, %xmm5
; GFNISSE-NEXT: por %xmm0, %xmm5
@@ -1388,90 +1242,77 @@ define <64 x i8> @var_rotl_v64i8(<64 x i8> %a, <64 x i8> %amt) nounwind {
;
; GFNIAVX1-LABEL: var_rotl_v64i8:
; GFNIAVX1: # %bb.0:
-; GFNIAVX1-NEXT: vextractf128 $1, %ymm0, %xmm5
-; GFNIAVX1-NEXT: vpsrlw $4, %xmm5, %xmm6
-; GFNIAVX1-NEXT: vbroadcastss {{.*#+}} xmm4 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240]
-; GFNIAVX1-NEXT: vpandn %xmm6, %xmm4, %xmm6
-; GFNIAVX1-NEXT: vpsllw $4, %xmm5, %xmm7
-; GFNIAVX1-NEXT: vpand %xmm4, %xmm7, %xmm7
-; GFNIAVX1-NEXT: vpor %xmm6, %xmm7, %xmm6
-; GFNIAVX1-NEXT: vextractf128 $1, %ymm2, %xmm7
-; GFNIAVX1-NEXT: vpsllw $5, %xmm7, %xmm7
-; GFNIAVX1-NEXT: vpblendvb %xmm7, %xmm6, %xmm5, %xmm6
-; GFNIAVX1-NEXT: vpsrlw $6, %xmm6, %xmm8
-; GFNIAVX1-NEXT: vbroadcastss {{.*#+}} xmm5 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252]
-; GFNIAVX1-NEXT: vpandn %xmm8, %xmm5, %xmm8
-; GFNIAVX1-NEXT: vpsllw $2, %xmm6, %xmm9
-; GFNIAVX1-NEXT: vpand %xmm5, %xmm9, %xmm9
-; GFNIAVX1-NEXT: vpor %xmm8, %xmm9, %xmm8
-; GFNIAVX1-NEXT: vpaddb %xmm7, %xmm7, %xmm7
-; GFNIAVX1-NEXT: vpblendvb %xmm7, %xmm8, %xmm6, %xmm8
-; GFNIAVX1-NEXT: vpsrlw $7, %xmm8, %xmm9
-; GFNIAVX1-NEXT: vbroadcastss {{.*#+}} xmm6 = [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1]
-; GFNIAVX1-NEXT: vpand %xmm6, %xmm9, %xmm9
-; GFNIAVX1-NEXT: vpaddb %xmm8, %xmm8, %xmm10
-; GFNIAVX1-NEXT: vpor %xmm9, %xmm10, %xmm9
-; GFNIAVX1-NEXT: vpaddb %xmm7, %xmm7, %xmm7
-; GFNIAVX1-NEXT: vpblendvb %xmm7, %xmm9, %xmm8, %xmm7
-; GFNIAVX1-NEXT: vpsrlw $4, %xmm0, %xmm8
-; GFNIAVX1-NEXT: vpandn %xmm8, %xmm4, %xmm8
-; GFNIAVX1-NEXT: vpsllw $4, %xmm0, %xmm9
-; GFNIAVX1-NEXT: vpand %xmm4, %xmm9, %xmm9
-; GFNIAVX1-NEXT: vpor %xmm8, %xmm9, %xmm8
+; GFNIAVX1-NEXT: vextractf128 $1, %ymm0, %xmm6
+; GFNIAVX1-NEXT: vmovddup {{.*#+}} xmm4 = [1161999622361579520,1161999622361579520]
+; GFNIAVX1-NEXT: # xmm4 = mem[0,0]
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm4, %xmm6, %xmm7
+; GFNIAVX1-NEXT: vmovddup {{.*#+}} xmm5 = [16909320,16909320]
+; GFNIAVX1-NEXT: # xmm5 = mem[0,0]
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm5, %xmm6, %xmm8
+; GFNIAVX1-NEXT: vpor %xmm7, %xmm8, %xmm7
+; GFNIAVX1-NEXT: vextractf128 $1, %ymm2, %xmm8
+; GFNIAVX1-NEXT: vpsllw $5, %xmm8, %xmm8
+; GFNIAVX1-NEXT: vpblendvb %xmm8, %xmm7, %xmm6, %xmm9
+; GFNIAVX1-NEXT: vmovddup {{.*#+}} xmm6 = [4647714815446351872,4647714815446351872]
+; GFNIAVX1-NEXT: # xmm6 = mem[0,0]
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm6, %xmm9, %xmm10
+; GFNIAVX1-NEXT: vmovddup {{.*#+}} xmm7 = [1108169199648,1108169199648]
+; GFNIAVX1-NEXT: # xmm7 = mem[0,0]
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm7, %xmm9, %xmm11
+; GFNIAVX1-NEXT: vpor %xmm10, %xmm11, %xmm10
+; GFNIAVX1-NEXT: vpaddb %xmm8, %xmm8, %xmm11
+; GFNIAVX1-NEXT: vpblendvb %xmm11, %xmm10, %xmm9, %xmm9
+; GFNIAVX1-NEXT: vmovddup {{.*#+}} xmm8 = [9223372036854775808,9223372036854775808]
+; GFNIAVX1-NEXT: # xmm8 = mem[0,0]
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm8, %xmm9, %xmm10
+; GFNIAVX1-NEXT: vpaddb %xmm9, %xmm9, %xmm12
+; GFNIAVX1-NEXT: vpor %xmm10, %xmm12, %xmm10
+; GFNIAVX1-NEXT: vpaddb %xmm11, %xmm11, %xmm11
+; GFNIAVX1-NEXT: vpblendvb %xmm11, %xmm10, %xmm9, %xmm9
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm4, %xmm0, %xmm10
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm5, %xmm0, %xmm11
+; GFNIAVX1-NEXT: vpor %xmm10, %xmm11, %xmm10
; GFNIAVX1-NEXT: vpsllw $5, %xmm2, %xmm2
-; GFNIAVX1-NEXT: vpblendvb %xmm2, %xmm8, %xmm0, %xmm0
-; GFNIAVX1-NEXT: vpsrlw $6, %xmm0, %xmm8
-; GFNIAVX1-NEXT: vpandn %xmm8, %xmm5, %xmm8
-; GFNIAVX1-NEXT: vpsllw $2, %xmm0, %xmm9
-; GFNIAVX1-NEXT: vpand %xmm5, %xmm9, %xmm9
-; GFNIAVX1-NEXT: vpor %xmm8, %xmm9, %xmm8
+; GFNIAVX1-NEXT: vpblendvb %xmm2, %xmm10, %xmm0, %xmm0
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm6, %xmm0, %xmm10
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm7, %xmm0, %xmm11
+; GFNIAVX1-NEXT: vpor %xmm10, %xmm11, %xmm10
; GFNIAVX1-NEXT: vpaddb %xmm2, %xmm2, %xmm2
-; GFNIAVX1-NEXT: vpblendvb %xmm2, %xmm8, %xmm0, %xmm0
-; GFNIAVX1-NEXT: vpsrlw $7, %xmm0, %xmm8
-; GFNIAVX1-NEXT: vpand %xmm6, %xmm8, %xmm8
-; GFNIAVX1-NEXT: vpaddb %xmm0, %xmm0, %xmm9
-; GFNIAVX1-NEXT: vpor %xmm8, %xmm9, %xmm8
+; GFNIAVX1-NEXT: vpblendvb %xmm2, %xmm10, %xmm0, %xmm0
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm8, %xmm0, %xmm10
+; GFNIAVX1-NEXT: vpaddb %xmm0, %xmm0, %xmm11
+; GFNIAVX1-NEXT: vpor %xmm10, %xmm11, %xmm10
; GFNIAVX1-NEXT: vpaddb %xmm2, %xmm2, %xmm2
-; GFNIAVX1-NEXT: vpblendvb %xmm2, %xmm8, %xmm0, %xmm0
-; GFNIAVX1-NEXT: vinsertf128 $1, %xmm7, %ymm0, %ymm0
+; GFNIAVX1-NEXT: vpblendvb %xmm2, %xmm10, %xmm0, %xmm0
+; GFNIAVX1-NEXT: vinsertf128 $1, %xmm9, %ymm0, %ymm0
; GFNIAVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
-; GFNIAVX1-NEXT: vpsrlw $4, %xmm2, %xmm7
-; GFNIAVX1-NEXT: vpandn %xmm7, %xmm4, %xmm7
-; GFNIAVX1-NEXT: vpsllw $4, %xmm2, %xmm8
-; GFNIAVX1-NEXT: vpand %xmm4, %xmm8, %xmm8
-; GFNIAVX1-NEXT: vpor %xmm7, %xmm8, %xmm7
-; GFNIAVX1-NEXT: vextractf128 $1, %ymm3, %xmm8
-; GFNIAVX1-NEXT: vpsllw $5, %xmm8, %xmm8
-; GFNIAVX1-NEXT: vpblendvb %xmm8, %xmm7, %xmm2, %xmm2
-; GFNIAVX1-NEXT: vpsrlw $6, %xmm2, %xmm7
-; GFNIAVX1-NEXT: vpandn %xmm7, %xmm5, %xmm7
-; GFNIAVX1-NEXT: vpsllw $2, %xmm2, %xmm9
-; GFNIAVX1-NEXT: vpand %xmm5, %xmm9, %xmm9
-; GFNIAVX1-NEXT: vpor %xmm7, %xmm9, %xmm7
-; GFNIAVX1-NEXT: vpaddb %xmm8, %xmm8, %xmm8
-; GFNIAVX1-NEXT: vpblendvb %xmm8, %xmm7, %xmm2, %xmm2
-; GFNIAVX1-NEXT: vpsrlw $7, %xmm2, %xmm7
-; GFNIAVX1-NEXT: vpand %xmm6, %xmm7, %xmm7
-; GFNIAVX1-NEXT: vpaddb %xmm2, %xmm2, %xmm9
-; GFNIAVX1-NEXT: vpor %xmm7, %xmm9, %xmm7
-; GFNIAVX1-NEXT: vpaddb %xmm8, %xmm8, %xmm8
-; GFNIAVX1-NEXT: vpblendvb %xmm8, %xmm7, %xmm2, %xmm2
-; GFNIAVX1-NEXT: vpsrlw $4, %xmm1, %xmm7
-; GFNIAVX1-NEXT: vpandn %xmm7, %xmm4, %xmm7
-; GFNIAVX1-NEXT: vpsllw $4, %xmm1, %xmm8
-; GFNIAVX1-NEXT: vpand %xmm4, %xmm8, %xmm4
-; GFNIAVX1-NEXT: vpor %xmm7, %xmm4, %xmm4
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm4, %xmm2, %xmm9
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm5, %xmm2, %xmm10
+; GFNIAVX1-NEXT: vpor %xmm9, %xmm10, %xmm9
+; GFNIAVX1-NEXT: vextractf128 $1, %ymm3, %xmm10
+; GFNIAVX1-NEXT: vpsllw $5, %xmm10, %xmm10
+; GFNIAVX1-NEXT: vpblendvb %xmm10, %xmm9, %xmm2, %xmm2
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm6, %xmm2, %xmm9
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm7, %xmm2, %xmm11
+; GFNIAVX1-NEXT: vpor %xmm9, %xmm11, %xmm9
+; GFNIAVX1-NEXT: vpaddb %xmm10, %xmm10, %xmm10
+; GFNIAVX1-NEXT: vpblendvb %xmm10, %xmm9, %xmm2, %xmm2
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm8, %xmm2, %xmm9
+; GFNIAVX1-NEXT: vpaddb %xmm2, %xmm2, %xmm11
+; GFNIAVX1-NEXT: vpor %xmm9, %xmm11, %xmm9
+; GFNIAVX1-NEXT: vpaddb %xmm10, %xmm10, %xmm10
+; GFNIAVX1-NEXT: vpblendvb %xmm10, %xmm9, %xmm2, %xmm2
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm4, %xmm1, %xmm4
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm5, %xmm1, %xmm5
+; GFNIAVX1-NEXT: vpor %xmm4, %xmm5, %xmm4
; GFNIAVX1-NEXT: vpsllw $5, %xmm3, %xmm3
; GFNIAVX1-NEXT: vpblendvb %xmm3, %xmm4, %xmm1, %xmm1
-; GFNIAVX1-NEXT: vpsrlw $6, %xmm1, %xmm4
-; GFNIAVX1-NEXT: vpandn %xmm4, %xmm5, %xmm4
-; GFNIAVX1-NEXT: vpsllw $2, %xmm1, %xmm7
-; GFNIAVX1-NEXT: vpand %xmm5, %xmm7, %xmm5
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm6, %xmm1, %xmm4
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm7, %xmm1, %xmm5
; GFNIAVX1-NEXT: vpor %xmm4, %xmm5, %xmm4
; GFNIAVX1-NEXT: vpaddb %xmm3, %xmm3, %xmm3
; GFNIAVX1-NEXT: vpblendvb %xmm3, %xmm4, %xmm1, %xmm1
-; GFNIAVX1-NEXT: vpsrlw $7, %xmm1, %xmm4
-; GFNIAVX1-NEXT: vpand %xmm6, %xmm4, %xmm4
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm8, %xmm1, %xmm4
; GFNIAVX1-NEXT: vpaddb %xmm1, %xmm1, %xmm5
; GFNIAVX1-NEXT: vpor %xmm4, %xmm5, %xmm4
; GFNIAVX1-NEXT: vpaddb %xmm3, %xmm3, %xmm3
@@ -1481,45 +1322,37 @@ define <64 x i8> @var_rotl_v64i8(<64 x i8> %a, <64 x i8> %amt) nounwind {
;
; GFNIAVX2-LABEL: var_rotl_v64i8:
; GFNIAVX2: # %bb.0:
-; GFNIAVX2-NEXT: vpsrlw $4, %ymm0, %ymm4
-; GFNIAVX2-NEXT: vpbroadcastb {{.*#+}} ymm5 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240]
-; GFNIAVX2-NEXT: vpandn %ymm4, %ymm5, %ymm4
-; GFNIAVX2-NEXT: vpsllw $4, %ymm0, %ymm6
-; GFNIAVX2-NEXT: vpand %ymm5, %ymm6, %ymm6
-; GFNIAVX2-NEXT: vpor %ymm4, %ymm6, %ymm4
+; GFNIAVX2-NEXT: vpbroadcastq {{.*#+}} ymm4 = [1161999622361579520,1161999622361579520,1161999622361579520,1161999622361579520]
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, %ymm4, %ymm0, %ymm5
+; GFNIAVX2-NEXT: vpbroadcastq {{.*#+}} ymm6 = [16909320,16909320,16909320,16909320]
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, %ymm6, %ymm0, %ymm7
+; GFNIAVX2-NEXT: vpor %ymm5, %ymm7, %ymm5
; GFNIAVX2-NEXT: vpsllw $5, %ymm2, %ymm2
-; GFNIAVX2-NEXT: vpblendvb %ymm2, %ymm4, %ymm0, %ymm0
-; GFNIAVX2-NEXT: vpsrlw $6, %ymm0, %ymm4
-; GFNIAVX2-NEXT: vpbroadcastb {{.*#+}} ymm6 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252]
-; GFNIAVX2-NEXT: vpandn %ymm4, %ymm6, %ymm4
-; GFNIAVX2-NEXT: vpsllw $2, %ymm0, %ymm7
-; GFNIAVX2-NEXT: vpand %ymm6, %ymm7, %ymm7
-; GFNIAVX2-NEXT: vpor %ymm4, %ymm7, %ymm4
+; GFNIAVX2-NEXT: vpblendvb %ymm2, %ymm5, %ymm0, %ymm0
+; GFNIAVX2-NEXT: vpbroadcastq {{.*#+}} ymm5 = [4647714815446351872,4647714815446351872,4647714815446351872,4647714815446351872]
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, %ymm5, %ymm0, %ymm7
+; GFNIAVX2-NEXT: vpbroadcastq {{.*#+}} ymm8 = [1108169199648,1108169199648,1108169199648,1108169199648]
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, %ymm8, %ymm0, %ymm9
+; GFNIAVX2-NEXT: vpor %ymm7, %ymm9, %ymm7
; GFNIAVX2-NEXT: vpaddb %ymm2, %ymm2, %ymm2
-; GFNIAVX2-NEXT: vpblendvb %ymm2, %ymm4, %ymm0, %ymm0
-; GFNIAVX2-NEXT: vpsrlw $7, %ymm0, %ymm4
-; GFNIAVX2-NEXT: vpbroadcastb {{.*#+}} ymm7 = [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1]
-; GFNIAVX2-NEXT: vpand %ymm7, %ymm4, %ymm4
-; GFNIAVX2-NEXT: vpaddb %ymm0, %ymm0, %ymm8
-; GFNIAVX2-NEXT: vpor %ymm4, %ymm8, %ymm4
+; GFNIAVX2-NEXT: vpblendvb %ymm2, %ymm7, %ymm0, %ymm0
+; GFNIAVX2-NEXT: vpbroadcastq {{.*#+}} ymm7 = [9223372036854775808,9223372036854775808,9223372036854775808,9223372036854775808]
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, %ymm7, %ymm0, %ymm9
+; GFNIAVX2-NEXT: vpaddb %ymm0, %ymm0, %ymm10
+; GFNIAVX2-NEXT: vpor %ymm9, %ymm10, %ymm9
; GFNIAVX2-NEXT: vpaddb %ymm2, %ymm2, %ymm2
-; GFNIAVX2-NEXT: vpblendvb %ymm2, %ymm4, %ymm0, %ymm0
-; GFNIAVX2-NEXT: vpsrlw $4, %ymm1, %ymm2
-; GFNIAVX2-NEXT: vpandn %ymm2, %ymm5, %ymm2
-; GFNIAVX2-NEXT: vpsllw $4, %ymm1, %ymm4
-; GFNIAVX2-NEXT: vpand %ymm5, %ymm4, %ymm4
+; GFNIAVX2-NEXT: vpblendvb %ymm2, %ymm9, %ymm0, %ymm0
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, %ymm4, %ymm1, %ymm2
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, %ymm6, %ymm1, %ymm4
; GFNIAVX2-NEXT: vpor %ymm2, %ymm4, %ymm2
; GFNIAVX2-NEXT: vpsllw $5, %ymm3, %ymm3
; GFNIAVX2-NEXT: vpblendvb %ymm3, %ymm2, %ymm1, %ymm1
-; GFNIAVX2-NEXT: vpsrlw $6, %ymm1, %ymm2
-; GFNIAVX2-NEXT: vpandn %ymm2, %ymm6, %ymm2
-; GFNIAVX2-NEXT: vpsllw $2, %ymm1, %ymm4
-; GFNIAVX2-NEXT: vpand %ymm6, %ymm4, %ymm4
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, %ymm5, %ymm1, %ymm2
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, %ymm8, %ymm1, %ymm4
; GFNIAVX2-NEXT: vpor %ymm2, %ymm4, %ymm2
; GFNIAVX2-NEXT: vpaddb %ymm3, %ymm3, %ymm3
; GFNIAVX2-NEXT: vpblendvb %ymm3, %ymm2, %ymm1, %ymm1
-; GFNIAVX2-NEXT: vpsrlw $7, %ymm1, %ymm2
-; GFNIAVX2-NEXT: vpand %ymm7, %ymm2, %ymm2
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, %ymm7, %ymm1, %ymm2
; GFNIAVX2-NEXT: vpaddb %ymm1, %ymm1, %ymm4
; GFNIAVX2-NEXT: vpor %ymm2, %ymm4, %ymm2
; GFNIAVX2-NEXT: vpaddb %ymm3, %ymm3, %ymm3
@@ -1529,40 +1362,42 @@ define <64 x i8> @var_rotl_v64i8(<64 x i8> %a, <64 x i8> %amt) nounwind {
; GFNIAVX512VL-LABEL: var_rotl_v64i8:
; GFNIAVX512VL: # %bb.0:
; GFNIAVX512VL-NEXT: vextracti64x4 $1, %zmm0, %ymm2
-; GFNIAVX512VL-NEXT: vpsrlw $4, %ymm2, %ymm3
-; GFNIAVX512VL-NEXT: vpsllw $4, %ymm2, %ymm4
-; GFNIAVX512VL-NEXT: vpbroadcastd {{.*#+}} ymm5 = [4042322160,4042322160,4042322160,4042322160,4042322160,4042322160,4042322160,4042322160]
-; GFNIAVX512VL-NEXT: vpternlogd $226, %ymm3, %ymm5, %ymm4
-; GFNIAVX512VL-NEXT: vextracti64x4 $1, %zmm1, %ymm3
-; GFNIAVX512VL-NEXT: vpsllw $5, %ymm3, %ymm3
-; GFNIAVX512VL-NEXT: vpblendvb %ymm3, %ymm4, %ymm2, %ymm2
-; GFNIAVX512VL-NEXT: vpsrlw $6, %ymm2, %ymm4
-; GFNIAVX512VL-NEXT: vpsllw $2, %ymm2, %ymm6
-; GFNIAVX512VL-NEXT: vpbroadcastd {{.*#+}} ymm7 = [4244438268,4244438268,4244438268,4244438268,4244438268,4244438268,4244438268,4244438268]
-; GFNIAVX512VL-NEXT: vpternlogd $226, %ymm4, %ymm7, %ymm6
-; GFNIAVX512VL-NEXT: vpaddb %ymm3, %ymm3, %ymm3
-; GFNIAVX512VL-NEXT: vpblendvb %ymm3, %ymm6, %ymm2, %ymm2
-; GFNIAVX512VL-NEXT: vpsrlw $7, %ymm2, %ymm4
-; GFNIAVX512VL-NEXT: vpaddb %ymm2, %ymm2, %ymm6
-; GFNIAVX512VL-NEXT: vpbroadcastd {{.*#+}} ymm8 = [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1]
-; GFNIAVX512VL-NEXT: vpternlogq $248, %ymm8, %ymm4, %ymm6
-; GFNIAVX512VL-NEXT: vpaddb %ymm3, %ymm3, %ymm3
-; GFNIAVX512VL-NEXT: vpblendvb %ymm3, %ymm6, %ymm2, %ymm2
-; GFNIAVX512VL-NEXT: vpsrlw $4, %ymm0, %ymm3
-; GFNIAVX512VL-NEXT: vpsllw $4, %ymm0, %ymm4
-; GFNIAVX512VL-NEXT: vpternlogd $226, %ymm3, %ymm5, %ymm4
+; GFNIAVX512VL-NEXT: vpbroadcastq {{.*#+}} ymm3 = [1161999622361579520,1161999622361579520,1161999622361579520,1161999622361579520]
+; GFNIAVX512VL-NEXT: vgf2p8affineqb $0, %ymm3, %ymm2, %ymm4
+; GFNIAVX512VL-NEXT: vpbroadcastq {{.*#+}} ymm5 = [16909320,16909320,16909320,16909320]
+; GFNIAVX512VL-NEXT: vgf2p8affineqb $0, %ymm5, %ymm2, %ymm6
+; GFNIAVX512VL-NEXT: vpor %ymm4, %ymm6, %ymm4
+; GFNIAVX512VL-NEXT: vextracti64x4 $1, %zmm1, %ymm6
+; GFNIAVX512VL-NEXT: vpsllw $5, %ymm6, %ymm6
+; GFNIAVX512VL-NEXT: vpblendvb %ymm6, %ymm4, %ymm2, %ymm2
+; GFNIAVX512VL-NEXT: vpbroadcastq {{.*#+}} ymm4 = [4647714815446351872,4647714815446351872,4647714815446351872,4647714815446351872]
+; GFNIAVX512VL-NEXT: vgf2p8affineqb $0, %ymm4, %ymm2, %ymm7
+; GFNIAVX512VL-NEXT: vpbroadcastq {{.*#+}} ymm8 = [1108169199648,1108169199648,1108169199648,1108169199648]
+; GFNIAVX512VL-NEXT: vgf2p8affineqb $0, %ymm8, %ymm2, %ymm9
+; GFNIAVX512VL-NEXT: vpor %ymm7, %ymm9, %ymm7
+; GFNIAVX512VL-NEXT: vpaddb %ymm6, %ymm6, %ymm6
+; GFNIAVX512VL-NEXT: vpblendvb %ymm6, %ymm7, %ymm2, %ymm2
+; GFNIAVX512VL-NEXT: vpbroadcastq {{.*#+}} ymm7 = [9223372036854775808,9223372036854775808,9223372036854775808,9223372036854775808]
+; GFNIAVX512VL-NEXT: vgf2p8affineqb $0, %ymm7, %ymm2, %ymm9
+; GFNIAVX512VL-NEXT: vpaddb %ymm2, %ymm2, %ymm10
+; GFNIAVX512VL-NEXT: vpor %ymm9, %ymm10, %ymm9
+; GFNIAVX512VL-NEXT: vpaddb %ymm6, %ymm6, %ymm6
+; GFNIAVX512VL-NEXT: vpblendvb %ymm6, %ymm9, %ymm2, %ymm2
+; GFNIAVX512VL-NEXT: vgf2p8affineqb $0, %ymm3, %ymm0, %ymm3
+; GFNIAVX512VL-NEXT: vgf2p8affineqb $0, %ymm5, %ymm0, %ymm5
+; GFNIAVX512VL-NEXT: vpor %ymm3, %ymm5, %ymm3
; GFNIAVX512VL-NEXT: vpsllw $5, %ymm1, %ymm1
-; GFNIAVX512VL-NEXT: vpblendvb %ymm1, %ymm4, %ymm0, %ymm0
-; GFNIAVX512VL-NEXT: vpsrlw $6, %ymm0, %ymm3
-; GFNIAVX512VL-NEXT: vpsllw $2, %ymm0, %ymm4
-; GFNIAVX512VL-NEXT: vpternlogd $226, %ymm3, %ymm7, %ymm4
+; GFNIAVX512VL-NEXT: vpblendvb %ymm1, %ymm3, %ymm0, %ymm0
+; GFNIAVX512VL-NEXT: vgf2p8affineqb $0, %ymm4, %ymm0, %ymm3
+; GFNIAVX512VL-NEXT: vgf2p8affineqb $0, %ymm8, %ymm0, %ymm4
+; GFNIAVX512VL-NEXT: vpor %ymm3, %ymm4, %ymm3
; GFNIAVX512VL-NEXT: vpaddb %ymm1, %ymm1, %ymm1
-; GFNIAVX512VL-NEXT: vpblendvb %ymm1, %ymm4, %ymm0, %ymm0
-; GFNIAVX512VL-NEXT: vpsrlw $7, %ymm0, %ymm3
+; GFNIAVX512VL-NEXT: vpblendvb %ymm1, %ymm3, %ymm0, %ymm0
+; GFNIAVX512VL-NEXT: vgf2p8affineqb $0, %ymm7, %ymm0, %ymm3
; GFNIAVX512VL-NEXT: vpaddb %ymm0, %ymm0, %ymm4
-; GFNIAVX512VL-NEXT: vpternlogq $248, %ymm8, %ymm3, %ymm4
+; GFNIAVX512VL-NEXT: vpor %ymm3, %ymm4, %ymm3
; GFNIAVX512VL-NEXT: vpaddb %ymm1, %ymm1, %ymm1
-; GFNIAVX512VL-NEXT: vpblendvb %ymm1, %ymm4, %ymm0, %ymm0
+; GFNIAVX512VL-NEXT: vpblendvb %ymm1, %ymm3, %ymm0, %ymm0
; GFNIAVX512VL-NEXT: vinserti64x4 $1, %ymm2, %zmm0, %zmm0
; GFNIAVX512VL-NEXT: retq
;
@@ -1587,123 +1422,99 @@ define <64 x i8> @var_rotr_v64i8(<64 x i8> %a, <64 x i8> %amt) nounwind {
; GFNISSE-LABEL: var_rotr_v64i8:
; GFNISSE: # %bb.0:
; GFNISSE-NEXT: movdqa %xmm0, %xmm9
-; GFNISSE-NEXT: psrlw $4, %xmm0
-; GFNISSE-NEXT: movdqa {{.*#+}} xmm10 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240]
-; GFNISSE-NEXT: movdqa %xmm10, %xmm8
-; GFNISSE-NEXT: pandn %xmm0, %xmm8
-; GFNISSE-NEXT: movdqa %xmm9, %xmm11
-; GFNISSE-NEXT: psllw $4, %xmm11
-; GFNISSE-NEXT: pand %xmm10, %xmm11
-; GFNISSE-NEXT: por %xmm8, %xmm11
+; GFNISSE-NEXT: movdqa {{.*#+}} xmm10 = [1161999622361579520,1161999622361579520]
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm10, %xmm0
+; GFNISSE-NEXT: pmovsxdq {{.*#+}} xmm11 = [16909320,16909320]
+; GFNISSE-NEXT: movdqa %xmm9, %xmm12
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm11, %xmm12
+; GFNISSE-NEXT: por %xmm0, %xmm12
; GFNISSE-NEXT: pxor %xmm8, %xmm8
; GFNISSE-NEXT: pxor %xmm0, %xmm0
; GFNISSE-NEXT: psubb %xmm4, %xmm0
; GFNISSE-NEXT: psllw $5, %xmm0
-; GFNISSE-NEXT: pblendvb %xmm0, %xmm11, %xmm9
-; GFNISSE-NEXT: movdqa %xmm9, %xmm11
-; GFNISSE-NEXT: psrlw $6, %xmm11
-; GFNISSE-NEXT: movdqa {{.*#+}} xmm4 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252]
-; GFNISSE-NEXT: movdqa %xmm4, %xmm12
-; GFNISSE-NEXT: pandn %xmm11, %xmm12
-; GFNISSE-NEXT: movdqa %xmm9, %xmm11
-; GFNISSE-NEXT: psllw $2, %xmm11
-; GFNISSE-NEXT: pand %xmm4, %xmm11
-; GFNISSE-NEXT: por %xmm12, %xmm11
-; GFNISSE-NEXT: paddb %xmm0, %xmm0
-; GFNISSE-NEXT: pblendvb %xmm0, %xmm11, %xmm9
-; GFNISSE-NEXT: movdqa %xmm9, %xmm12
-; GFNISSE-NEXT: psrlw $7, %xmm12
-; GFNISSE-NEXT: movdqa {{.*#+}} xmm11 = [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1]
-; GFNISSE-NEXT: pand %xmm11, %xmm12
+; GFNISSE-NEXT: pblendvb %xmm0, %xmm12, %xmm9
+; GFNISSE-NEXT: movdqa {{.*#+}} xmm4 = [4647714815446351872,4647714815446351872]
; GFNISSE-NEXT: movdqa %xmm9, %xmm13
-; GFNISSE-NEXT: paddb %xmm9, %xmm13
-; GFNISSE-NEXT: por %xmm12, %xmm13
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm4, %xmm13
+; GFNISSE-NEXT: movdqa {{.*#+}} xmm12 = [1108169199648,1108169199648]
+; GFNISSE-NEXT: movdqa %xmm9, %xmm14
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm12, %xmm14
+; GFNISSE-NEXT: por %xmm13, %xmm14
; GFNISSE-NEXT: paddb %xmm0, %xmm0
-; GFNISSE-NEXT: pblendvb %xmm0, %xmm13, %xmm9
+; GFNISSE-NEXT: pblendvb %xmm0, %xmm14, %xmm9
+; GFNISSE-NEXT: movdqa {{.*#+}} xmm13 = [9223372036854775808,9223372036854775808]
+; GFNISSE-NEXT: movdqa %xmm9, %xmm14
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm13, %xmm14
+; GFNISSE-NEXT: movdqa %xmm9, %xmm15
+; GFNISSE-NEXT: paddb %xmm9, %xmm15
+; GFNISSE-NEXT: por %xmm14, %xmm15
+; GFNISSE-NEXT: paddb %xmm0, %xmm0
+; GFNISSE-NEXT: pblendvb %xmm0, %xmm15, %xmm9
; GFNISSE-NEXT: movdqa %xmm1, %xmm0
-; GFNISSE-NEXT: psrlw $4, %xmm0
-; GFNISSE-NEXT: movdqa %xmm10, %xmm12
-; GFNISSE-NEXT: pandn %xmm0, %xmm12
-; GFNISSE-NEXT: movdqa %xmm1, %xmm13
-; GFNISSE-NEXT: psllw $4, %xmm13
-; GFNISSE-NEXT: pand %xmm10, %xmm13
-; GFNISSE-NEXT: por %xmm12, %xmm13
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm10, %xmm0
+; GFNISSE-NEXT: movdqa %xmm1, %xmm14
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm11, %xmm14
+; GFNISSE-NEXT: por %xmm0, %xmm14
; GFNISSE-NEXT: pxor %xmm0, %xmm0
; GFNISSE-NEXT: psubb %xmm5, %xmm0
; GFNISSE-NEXT: psllw $5, %xmm0
-; GFNISSE-NEXT: pblendvb %xmm0, %xmm13, %xmm1
-; GFNISSE-NEXT: movdqa %xmm1, %xmm5
-; GFNISSE-NEXT: psrlw $6, %xmm5
-; GFNISSE-NEXT: movdqa %xmm4, %xmm12
-; GFNISSE-NEXT: pandn %xmm5, %xmm12
+; GFNISSE-NEXT: pblendvb %xmm0, %xmm14, %xmm1
; GFNISSE-NEXT: movdqa %xmm1, %xmm5
-; GFNISSE-NEXT: psllw $2, %xmm5
-; GFNISSE-NEXT: pand %xmm4, %xmm5
-; GFNISSE-NEXT: por %xmm12, %xmm5
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm4, %xmm5
+; GFNISSE-NEXT: movdqa %xmm1, %xmm14
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm12, %xmm14
+; GFNISSE-NEXT: por %xmm5, %xmm14
; GFNISSE-NEXT: paddb %xmm0, %xmm0
-; GFNISSE-NEXT: pblendvb %xmm0, %xmm5, %xmm1
+; GFNISSE-NEXT: pblendvb %xmm0, %xmm14, %xmm1
; GFNISSE-NEXT: movdqa %xmm1, %xmm5
-; GFNISSE-NEXT: psrlw $7, %xmm5
-; GFNISSE-NEXT: pand %xmm11, %xmm5
-; GFNISSE-NEXT: movdqa %xmm1, %xmm12
-; GFNISSE-NEXT: paddb %xmm1, %xmm12
-; GFNISSE-NEXT: por %xmm5, %xmm12
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm13, %xmm5
+; GFNISSE-NEXT: movdqa %xmm1, %xmm14
+; GFNISSE-NEXT: paddb %xmm1, %xmm14
+; GFNISSE-NEXT: por %xmm5, %xmm14
; GFNISSE-NEXT: paddb %xmm0, %xmm0
-; GFNISSE-NEXT: pblendvb %xmm0, %xmm12, %xmm1
+; GFNISSE-NEXT: pblendvb %xmm0, %xmm14, %xmm1
; GFNISSE-NEXT: movdqa %xmm2, %xmm0
-; GFNISSE-NEXT: psrlw $4, %xmm0
-; GFNISSE-NEXT: movdqa %xmm10, %xmm5
-; GFNISSE-NEXT: pandn %xmm0, %xmm5
-; GFNISSE-NEXT: movdqa %xmm2, %xmm12
-; GFNISSE-NEXT: psllw $4, %xmm12
-; GFNISSE-NEXT: pand %xmm10, %xmm12
-; GFNISSE-NEXT: por %xmm5, %xmm12
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm10, %xmm0
+; GFNISSE-NEXT: movdqa %xmm2, %xmm5
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm11, %xmm5
+; GFNISSE-NEXT: por %xmm0, %xmm5
; GFNISSE-NEXT: pxor %xmm0, %xmm0
; GFNISSE-NEXT: psubb %xmm6, %xmm0
; GFNISSE-NEXT: psllw $5, %xmm0
-; GFNISSE-NEXT: pblendvb %xmm0, %xmm12, %xmm2
-; GFNISSE-NEXT: movdqa %xmm2, %xmm5
-; GFNISSE-NEXT: psrlw $6, %xmm5
-; GFNISSE-NEXT: movdqa %xmm4, %xmm6
-; GFNISSE-NEXT: pandn %xmm5, %xmm6
+; GFNISSE-NEXT: pblendvb %xmm0, %xmm5, %xmm2
; GFNISSE-NEXT: movdqa %xmm2, %xmm5
-; GFNISSE-NEXT: psllw $2, %xmm5
-; GFNISSE-NEXT: pand %xmm4, %xmm5
-; GFNISSE-NEXT: por %xmm6, %xmm5
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm4, %xmm5
+; GFNISSE-NEXT: movdqa %xmm2, %xmm6
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm12, %xmm6
+; GFNISSE-NEXT: por %xmm5, %xmm6
; GFNISSE-NEXT: paddb %xmm0, %xmm0
-; GFNISSE-NEXT: pblendvb %xmm0, %xmm5, %xmm2
+; GFNISSE-NEXT: pblendvb %xmm0, %xmm6, %xmm2
; GFNISSE-NEXT: movdqa %xmm2, %xmm5
-; GFNISSE-NEXT: psrlw $7, %xmm5
-; GFNISSE-NEXT: pand %xmm11, %xmm5
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm13, %xmm5
; GFNISSE-NEXT: movdqa %xmm2, %xmm6
; GFNISSE-NEXT: paddb %xmm2, %xmm6
; GFNISSE-NEXT: por %xmm5, %xmm6
; GFNISSE-NEXT: paddb %xmm0, %xmm0
; GFNISSE-NEXT: pblendvb %xmm0, %xmm6, %xmm2
; GFNISSE-NEXT: movdqa %xmm3, %xmm0
-; GFNISSE-NEXT: psrlw $4, %xmm0
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm10, %xmm0
; GFNISSE-NEXT: movdqa %xmm3, %xmm5
-; GFNISSE-NEXT: psllw $4, %xmm5
-; GFNISSE-NEXT: pand %xmm10, %xmm5
-; GFNISSE-NEXT: pandn %xmm0, %xmm10
-; GFNISSE-NEXT: por %xmm5, %xmm10
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm11, %xmm5
+; GFNISSE-NEXT: por %xmm0, %xmm5
; GFNISSE-NEXT: psubb %xmm7, %xmm8
; GFNISSE-NEXT: psllw $5, %xmm8
; GFNISSE-NEXT: movdqa %xmm8, %xmm0
-; GFNISSE-NEXT: pblendvb %xmm0, %xmm10, %xmm3
+; GFNISSE-NEXT: pblendvb %xmm0, %xmm5, %xmm3
; GFNISSE-NEXT: movdqa %xmm3, %xmm0
-; GFNISSE-NEXT: psrlw $6, %xmm0
-; GFNISSE-NEXT: movdqa %xmm3, %xmm5
-; GFNISSE-NEXT: psllw $2, %xmm5
-; GFNISSE-NEXT: pand %xmm4, %xmm5
-; GFNISSE-NEXT: pandn %xmm0, %xmm4
-; GFNISSE-NEXT: por %xmm5, %xmm4
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm4, %xmm0
+; GFNISSE-NEXT: movdqa %xmm3, %xmm4
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm12, %xmm4
+; GFNISSE-NEXT: por %xmm0, %xmm4
; GFNISSE-NEXT: paddb %xmm8, %xmm8
; GFNISSE-NEXT: movdqa %xmm8, %xmm0
; GFNISSE-NEXT: pblendvb %xmm0, %xmm4, %xmm3
; GFNISSE-NEXT: movdqa %xmm3, %xmm0
-; GFNISSE-NEXT: psrlw $7, %xmm0
-; GFNISSE-NEXT: pand %xmm11, %xmm0
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm13, %xmm0
; GFNISSE-NEXT: movdqa %xmm3, %xmm4
; GFNISSE-NEXT: paddb %xmm3, %xmm4
; GFNISSE-NEXT: por %xmm0, %xmm4
@@ -1715,95 +1526,82 @@ define <64 x i8> @var_rotr_v64i8(<64 x i8> %a, <64 x i8> %amt) nounwind {
;
; GFNIAVX1-LABEL: var_rotr_v64i8:
; GFNIAVX1: # %bb.0:
-; GFNIAVX1-NEXT: vextractf128 $1, %ymm0, %xmm5
-; GFNIAVX1-NEXT: vpsrlw $4, %xmm5, %xmm6
-; GFNIAVX1-NEXT: vbroadcastss {{.*#+}} xmm4 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240]
-; GFNIAVX1-NEXT: vpandn %xmm6, %xmm4, %xmm6
-; GFNIAVX1-NEXT: vpsllw $4, %xmm5, %xmm7
-; GFNIAVX1-NEXT: vpand %xmm4, %xmm7, %xmm7
-; GFNIAVX1-NEXT: vpor %xmm6, %xmm7, %xmm7
-; GFNIAVX1-NEXT: vextractf128 $1, %ymm2, %xmm8
+; GFNIAVX1-NEXT: vextractf128 $1, %ymm0, %xmm7
+; GFNIAVX1-NEXT: vmovddup {{.*#+}} xmm4 = [1161999622361579520,1161999622361579520]
+; GFNIAVX1-NEXT: # xmm4 = mem[0,0]
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm4, %xmm7, %xmm6
+; GFNIAVX1-NEXT: vmovddup {{.*#+}} xmm5 = [16909320,16909320]
+; GFNIAVX1-NEXT: # xmm5 = mem[0,0]
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm5, %xmm7, %xmm8
+; GFNIAVX1-NEXT: vpor %xmm6, %xmm8, %xmm8
+; GFNIAVX1-NEXT: vextractf128 $1, %ymm2, %xmm9
; GFNIAVX1-NEXT: vpxor %xmm6, %xmm6, %xmm6
-; GFNIAVX1-NEXT: vpsubb %xmm8, %xmm6, %xmm8
-; GFNIAVX1-NEXT: vpsllw $5, %xmm8, %xmm8
-; GFNIAVX1-NEXT: vpblendvb %xmm8, %xmm7, %xmm5, %xmm7
-; GFNIAVX1-NEXT: vpsrlw $6, %xmm7, %xmm9
-; GFNIAVX1-NEXT: vbroadcastss {{.*#+}} xmm5 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252]
-; GFNIAVX1-NEXT: vpandn %xmm9, %xmm5, %xmm9
-; GFNIAVX1-NEXT: vpsllw $2, %xmm7, %xmm10
-; GFNIAVX1-NEXT: vpand %xmm5, %xmm10, %xmm10
-; GFNIAVX1-NEXT: vpor %xmm9, %xmm10, %xmm9
-; GFNIAVX1-NEXT: vpaddb %xmm8, %xmm8, %xmm8
-; GFNIAVX1-NEXT: vpblendvb %xmm8, %xmm9, %xmm7, %xmm9
-; GFNIAVX1-NEXT: vpsrlw $7, %xmm9, %xmm10
-; GFNIAVX1-NEXT: vbroadcastss {{.*#+}} xmm7 = [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1]
-; GFNIAVX1-NEXT: vpand %xmm7, %xmm10, %xmm10
-; GFNIAVX1-NEXT: vpaddb %xmm9, %xmm9, %xmm11
-; GFNIAVX1-NEXT: vpor %xmm10, %xmm11, %xmm10
-; GFNIAVX1-NEXT: vpaddb %xmm8, %xmm8, %xmm8
-; GFNIAVX1-NEXT: vpblendvb %xmm8, %xmm10, %xmm9, %xmm8
-; GFNIAVX1-NEXT: vpsrlw $4, %xmm0, %xmm9
-; GFNIAVX1-NEXT: vpandn %xmm9, %xmm4, %xmm9
-; GFNIAVX1-NEXT: vpsllw $4, %xmm0, %xmm10
-; GFNIAVX1-NEXT: vpand %xmm4, %xmm10, %xmm10
-; GFNIAVX1-NEXT: vpor %xmm9, %xmm10, %xmm9
+; GFNIAVX1-NEXT: vpsubb %xmm9, %xmm6, %xmm9
+; GFNIAVX1-NEXT: vpsllw $5, %xmm9, %xmm9
+; GFNIAVX1-NEXT: vpblendvb %xmm9, %xmm8, %xmm7, %xmm10
+; GFNIAVX1-NEXT: vmovddup {{.*#+}} xmm7 = [4647714815446351872,4647714815446351872]
+; GFNIAVX1-NEXT: # xmm7 = mem[0,0]
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm7, %xmm10, %xmm11
+; GFNIAVX1-NEXT: vmovddup {{.*#+}} xmm8 = [1108169199648,1108169199648]
+; GFNIAVX1-NEXT: # xmm8 = mem[0,0]
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm8, %xmm10, %xmm12
+; GFNIAVX1-NEXT: vpor %xmm11, %xmm12, %xmm11
+; GFNIAVX1-NEXT: vpaddb %xmm9, %xmm9, %xmm12
+; GFNIAVX1-NEXT: vpblendvb %xmm12, %xmm11, %xmm10, %xmm10
+; GFNIAVX1-NEXT: vmovddup {{.*#+}} xmm9 = [9223372036854775808,9223372036854775808]
+; GFNIAVX1-NEXT: # xmm9 = mem[0,0]
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm9, %xmm10, %xmm11
+; GFNIAVX1-NEXT: vpaddb %xmm10, %xmm10, %xmm13
+; GFNIAVX1-NEXT: vpor %xmm11, %xmm13, %xmm11
+; GFNIAVX1-NEXT: vpaddb %xmm12, %xmm12, %xmm12
+; GFNIAVX1-NEXT: vpblendvb %xmm12, %xmm11, %xmm10, %xmm10
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm4, %xmm0, %xmm11
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm5, %xmm0, %xmm12
+; GFNIAVX1-NEXT: vpor %xmm11, %xmm12, %xmm11
; GFNIAVX1-NEXT: vpsubb %xmm2, %xmm6, %xmm2
; GFNIAVX1-NEXT: vpsllw $5, %xmm2, %xmm2
-; GFNIAVX1-NEXT: vpblendvb %xmm2, %xmm9, %xmm0, %xmm0
-; GFNIAVX1-NEXT: vpsrlw $6, %xmm0, %xmm9
-; GFNIAVX1-NEXT: vpandn %xmm9, %xmm5, %xmm9
-; GFNIAVX1-NEXT: vpsllw $2, %xmm0, %xmm10
-; GFNIAVX1-NEXT: vpand %xmm5, %xmm10, %xmm10
-; GFNIAVX1-NEXT: vpor %xmm9, %xmm10, %xmm9
+; GFNIAVX1-NEXT: vpblendvb %xmm2, %xmm11, %xmm0, %xmm0
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm7, %xmm0, %xmm11
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm8, %xmm0, %xmm12
+; GFNIAVX1-NEXT: vpor %xmm11, %xmm12, %xmm11
; GFNIAVX1-NEXT: vpaddb %xmm2, %xmm2, %xmm2
-; GFNIAVX1-NEXT: vpblendvb %xmm2, %xmm9, %xmm0, %xmm0
-; GFNIAVX1-NEXT: vpsrlw $7, %xmm0, %xmm9
-; GFNIAVX1-NEXT: vpand %xmm7, %xmm9, %xmm9
-; GFNIAVX1-NEXT: vpaddb %xmm0, %xmm0, %xmm10
-; GFNIAVX1-NEXT: vpor %xmm9, %xmm10, %xmm9
+; GFNIAVX1-NEXT: vpblendvb %xmm2, %xmm11, %xmm0, %xmm0
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm9, %xmm0, %xmm11
+; GFNIAVX1-NEXT: vpaddb %xmm0, %xmm0, %xmm12
+; GFNIAVX1-NEXT: vpor %xmm11, %xmm12, %xmm11
; GFNIAVX1-NEXT: vpaddb %xmm2, %xmm2, %xmm2
-; GFNIAVX1-NEXT: vpblendvb %xmm2, %xmm9, %xmm0, %xmm0
-; GFNIAVX1-NEXT: vinsertf128 $1, %xmm8, %ymm0, %ymm0
+; GFNIAVX1-NEXT: vpblendvb %xmm2, %xmm11, %xmm0, %xmm0
+; GFNIAVX1-NEXT: vinsertf128 $1, %xmm10, %ymm0, %ymm0
; GFNIAVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
-; GFNIAVX1-NEXT: vpsrlw $4, %xmm2, %xmm8
-; GFNIAVX1-NEXT: vpandn %xmm8, %xmm4, %xmm8
-; GFNIAVX1-NEXT: vpsllw $4, %xmm2, %xmm9
-; GFNIAVX1-NEXT: vpand %xmm4, %xmm9, %xmm9
-; GFNIAVX1-NEXT: vpor %xmm8, %xmm9, %xmm8
-; GFNIAVX1-NEXT: vextractf128 $1, %ymm3, %xmm9
-; GFNIAVX1-NEXT: vpsubb %xmm9, %xmm6, %xmm9
-; GFNIAVX1-NEXT: vpsllw $5, %xmm9, %xmm9
-; GFNIAVX1-NEXT: vpblendvb %xmm9, %xmm8, %xmm2, %xmm2
-; GFNIAVX1-NEXT: vpsrlw $6, %xmm2, %xmm8
-; GFNIAVX1-NEXT: vpandn %xmm8, %xmm5, %xmm8
-; GFNIAVX1-NEXT: vpsllw $2, %xmm2, %xmm10
-; GFNIAVX1-NEXT: vpand %xmm5, %xmm10, %xmm10
-; GFNIAVX1-NEXT: vpor %xmm8, %xmm10, %xmm8
-; GFNIAVX1-NEXT: vpaddb %xmm9, %xmm9, %xmm9
-; GFNIAVX1-NEXT: vpblendvb %xmm9, %xmm8, %xmm2, %xmm2
-; GFNIAVX1-NEXT: vpsrlw $7, %xmm2, %xmm8
-; GFNIAVX1-NEXT: vpand %xmm7, %xmm8, %xmm8
-; GFNIAVX1-NEXT: vpaddb %xmm2, %xmm2, %xmm10
-; GFNIAVX1-NEXT: vpor %xmm8, %xmm10, %xmm8
-; GFNIAVX1-NEXT: vpaddb %xmm9, %xmm9, %xmm9
-; GFNIAVX1-NEXT: vpblendvb %xmm9, %xmm8, %xmm2, %xmm2
-; GFNIAVX1-NEXT: vpsrlw $4, %xmm1, %xmm8
-; GFNIAVX1-NEXT: vpandn %xmm8, %xmm4, %xmm8
-; GFNIAVX1-NEXT: vpsllw $4, %xmm1, %xmm9
-; GFNIAVX1-NEXT: vpand %xmm4, %xmm9, %xmm4
-; GFNIAVX1-NEXT: vpor %xmm4, %xmm8, %xmm4
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm4, %xmm2, %xmm10
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm5, %xmm2, %xmm11
+; GFNIAVX1-NEXT: vpor %xmm10, %xmm11, %xmm10
+; GFNIAVX1-NEXT: vextractf128 $1, %ymm3, %xmm11
+; GFNIAVX1-NEXT: vpsubb %xmm11, %xmm6, %xmm11
+; GFNIAVX1-NEXT: vpsllw $5, %xmm11, %xmm11
+; GFNIAVX1-NEXT: vpblendvb %xmm11, %xmm10, %xmm2, %xmm2
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm7, %xmm2, %xmm10
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm8, %xmm2, %xmm12
+; GFNIAVX1-NEXT: vpor %xmm10, %xmm12, %xmm10
+; GFNIAVX1-NEXT: vpaddb %xmm11, %xmm11, %xmm11
+; GFNIAVX1-NEXT: vpblendvb %xmm11, %xmm10, %xmm2, %xmm2
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm9, %xmm2, %xmm10
+; GFNIAVX1-NEXT: vpaddb %xmm2, %xmm2, %xmm12
+; GFNIAVX1-NEXT: vpor %xmm10, %xmm12, %xmm10
+; GFNIAVX1-NEXT: vpaddb %xmm11, %xmm11, %xmm11
+; GFNIAVX1-NEXT: vpblendvb %xmm11, %xmm10, %xmm2, %xmm2
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm4, %xmm1, %xmm4
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm5, %xmm1, %xmm5
+; GFNIAVX1-NEXT: vpor %xmm4, %xmm5, %xmm4
; GFNIAVX1-NEXT: vpsubb %xmm3, %xmm6, %xmm3
; GFNIAVX1-NEXT: vpsllw $5, %xmm3, %xmm3
; GFNIAVX1-NEXT: vpblendvb %xmm3, %xmm4, %xmm1, %xmm1
-; GFNIAVX1-NEXT: vpsrlw $6, %xmm1, %xmm4
-; GFNIAVX1-NEXT: vpandn %xmm4, %xmm5, %xmm4
-; GFNIAVX1-NEXT: vpsllw $2, %xmm1, %xmm6
-; GFNIAVX1-NEXT: vpand %xmm5, %xmm6, %xmm5
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm7, %xmm1, %xmm4
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm8, %xmm1, %xmm5
; GFNIAVX1-NEXT: vpor %xmm4, %xmm5, %xmm4
; GFNIAVX1-NEXT: vpaddb %xmm3, %xmm3, %xmm3
; GFNIAVX1-NEXT: vpblendvb %xmm3, %xmm4, %xmm1, %xmm1
-; GFNIAVX1-NEXT: vpsrlw $7, %xmm1, %xmm4
-; GFNIAVX1-NEXT: vpand %xmm7, %xmm4, %xmm4
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm9, %xmm1, %xmm4
; GFNIAVX1-NEXT: vpaddb %xmm1, %xmm1, %xmm5
; GFNIAVX1-NEXT: vpor %xmm4, %xmm5, %xmm4
; GFNIAVX1-NEXT: vpaddb %xmm3, %xmm3, %xmm3
@@ -1813,48 +1611,40 @@ define <64 x i8> @var_rotr_v64i8(<64 x i8> %a, <64 x i8> %amt) nounwind {
;
; GFNIAVX2-LABEL: var_rotr_v64i8:
; GFNIAVX2: # %bb.0:
-; GFNIAVX2-NEXT: vpsrlw $4, %ymm0, %ymm4
-; GFNIAVX2-NEXT: vpbroadcastb {{.*#+}} ymm5 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240]
-; GFNIAVX2-NEXT: vpandn %ymm4, %ymm5, %ymm4
-; GFNIAVX2-NEXT: vpsllw $4, %ymm0, %ymm6
-; GFNIAVX2-NEXT: vpand %ymm5, %ymm6, %ymm6
-; GFNIAVX2-NEXT: vpor %ymm4, %ymm6, %ymm4
-; GFNIAVX2-NEXT: vpxor %xmm6, %xmm6, %xmm6
-; GFNIAVX2-NEXT: vpsubb %ymm2, %ymm6, %ymm2
+; GFNIAVX2-NEXT: vpbroadcastq {{.*#+}} ymm4 = [1161999622361579520,1161999622361579520,1161999622361579520,1161999622361579520]
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, %ymm4, %ymm0, %ymm5
+; GFNIAVX2-NEXT: vpbroadcastq {{.*#+}} ymm6 = [16909320,16909320,16909320,16909320]
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, %ymm6, %ymm0, %ymm7
+; GFNIAVX2-NEXT: vpor %ymm5, %ymm7, %ymm5
+; GFNIAVX2-NEXT: vpxor %xmm7, %xmm7, %xmm7
+; GFNIAVX2-NEXT: vpsubb %ymm2, %ymm7, %ymm2
; GFNIAVX2-NEXT: vpsllw $5, %ymm2, %ymm2
-; GFNIAVX2-NEXT: vpblendvb %ymm2, %ymm4, %ymm0, %ymm0
-; GFNIAVX2-NEXT: vpsrlw $6, %ymm0, %ymm4
-; GFNIAVX2-NEXT: vpbroadcastb {{.*#+}} ymm7 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252]
-; GFNIAVX2-NEXT: vpandn %ymm4, %ymm7, %ymm4
-; GFNIAVX2-NEXT: vpsllw $2, %ymm0, %ymm8
-; GFNIAVX2-NEXT: vpand %ymm7, %ymm8, %ymm8
-; GFNIAVX2-NEXT: vpor %ymm4, %ymm8, %ymm4
+; GFNIAVX2-NEXT: vpblendvb %ymm2, %ymm5, %ymm0, %ymm0
+; GFNIAVX2-NEXT: vpbroadcastq {{.*#+}} ymm5 = [4647714815446351872,4647714815446351872,4647714815446351872,4647714815446351872]
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, %ymm5, %ymm0, %ymm8
+; GFNIAVX2-NEXT: vpbroadcastq {{.*#+}} ymm9 = [1108169199648,1108169199648,1108169199648,1108169199648]
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, %ymm9, %ymm0, %ymm10
+; GFNIAVX2-NEXT: vpor %ymm8, %ymm10, %ymm8
; GFNIAVX2-NEXT: vpaddb %ymm2, %ymm2, %ymm2
-; GFNIAVX2-NEXT: vpblendvb %ymm2, %ymm4, %ymm0, %ymm0
-; GFNIAVX2-NEXT: vpsrlw $7, %ymm0, %ymm4
-; GFNIAVX2-NEXT: vpbroadcastb {{.*#+}} ymm8 = [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1]
-; GFNIAVX2-NEXT: vpand %ymm4, %ymm8, %ymm4
-; GFNIAVX2-NEXT: vpaddb %ymm0, %ymm0, %ymm9
-; GFNIAVX2-NEXT: vpor %ymm4, %ymm9, %ymm4
+; GFNIAVX2-NEXT: vpblendvb %ymm2, %ymm8, %ymm0, %ymm0
+; GFNIAVX2-NEXT: vpbroadcastq {{.*#+}} ymm8 = [9223372036854775808,9223372036854775808,9223372036854775808,9223372036854775808]
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, %ymm8, %ymm0, %ymm10
+; GFNIAVX2-NEXT: vpaddb %ymm0, %ymm0, %ymm11
+; GFNIAVX2-NEXT: vpor %ymm10, %ymm11, %ymm10
; GFNIAVX2-NEXT: vpaddb %ymm2, %ymm2, %ymm2
-; GFNIAVX2-NEXT: vpblendvb %ymm2, %ymm4, %ymm0, %ymm0
-; GFNIAVX2-NEXT: vpsrlw $4, %ymm1, %ymm2
-; GFNIAVX2-NEXT: vpandn %ymm2, %ymm5, %ymm2
-; GFNIAVX2-NEXT: vpsllw $4, %ymm1, %ymm4
-; GFNIAVX2-NEXT: vpand %ymm5, %ymm4, %ymm4
+; GFNIAVX2-NEXT: vpblendvb %ymm2, %ymm10, %ymm0, %ymm0
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, %ymm4, %ymm1, %ymm2
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, %ymm6, %ymm1, %ymm4
; GFNIAVX2-NEXT: vpor %ymm2, %ymm4, %ymm2
-; GFNIAVX2-NEXT: vpsubb %ymm3, %ymm6, %ymm3
+; GFNIAVX2-NEXT: vpsubb %ymm3, %ymm7, %ymm3
; GFNIAVX2-NEXT: vpsllw $5, %ymm3, %ymm3
; GFNIAVX2-NEXT: vpblendvb %ymm3, %ymm2, %ymm1, %ymm1
-; GFNIAVX2-NEXT: vpsrlw $6, %ymm1, %ymm2
-; GFNIAVX2-NEXT: vpandn %ymm2, %ymm7, %ymm2
-; GFNIAVX2-NEXT: vpsllw $2, %ymm1, %ymm4
-; GFNIAVX2-NEXT: vpand %ymm7, %ymm4, %ymm4
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, %ymm5, %ymm1, %ymm2
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, %ymm9, %ymm1, %ymm4
; GFNIAVX2-NEXT: vpor %ymm2, %ymm4, %ymm2
; GFNIAVX2-NEXT: vpaddb %ymm3, %ymm3, %ymm3
; GFNIAVX2-NEXT: vpblendvb %ymm3, %ymm2, %ymm1, %ymm1
-; GFNIAVX2-NEXT: vpsrlw $7, %ymm1, %ymm2
-; GFNIAVX2-NEXT: vpand %ymm2, %ymm8, %ymm2
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, %ymm8, %ymm1, %ymm2
; GFNIAVX2-NEXT: vpaddb %ymm1, %ymm1, %ymm4
; GFNIAVX2-NEXT: vpor %ymm2, %ymm4, %ymm2
; GFNIAVX2-NEXT: vpaddb %ymm3, %ymm3, %ymm3
@@ -1864,40 +1654,43 @@ define <64 x i8> @var_rotr_v64i8(<64 x i8> %a, <64 x i8> %amt) nounwind {
; GFNIAVX512VL-LABEL: var_rotr_v64i8:
; GFNIAVX512VL: # %bb.0:
; GFNIAVX512VL-NEXT: vextracti64x4 $1, %zmm0, %ymm2
-; GFNIAVX512VL-NEXT: vpsllw $4, %ymm2, %ymm3
-; GFNIAVX512VL-NEXT: vpsrlw $4, %ymm2, %ymm4
-; GFNIAVX512VL-NEXT: vpbroadcastd {{.*#+}} ymm5 = [252645135,252645135,252645135,252645135,252645135,252645135,252645135,252645135]
-; GFNIAVX512VL-NEXT: vpternlogd $226, %ymm3, %ymm5, %ymm4
-; GFNIAVX512VL-NEXT: vextracti64x4 $1, %zmm1, %ymm3
-; GFNIAVX512VL-NEXT: vpsllw $5, %ymm3, %ymm3
-; GFNIAVX512VL-NEXT: vpblendvb %ymm3, %ymm4, %ymm2, %ymm2
-; GFNIAVX512VL-NEXT: vpsllw $6, %ymm2, %ymm4
-; GFNIAVX512VL-NEXT: vpsrlw $2, %ymm2, %ymm6
-; GFNIAVX512VL-NEXT: vpbroadcastd {{.*#+}} ymm7 = [1061109567,1061109567,1061109567,1061109567,1061109567,1061109567,1061109567,1061109567]
-; GFNIAVX512VL-NEXT: vpternlogd $226, %ymm4, %ymm7, %ymm6
-; GFNIAVX512VL-NEXT: vpaddb %ymm3, %ymm3, %ymm3
-; GFNIAVX512VL-NEXT: vpblendvb %ymm3, %ymm6, %ymm2, %ymm2
-; GFNIAVX512VL-NEXT: vpsllw $7, %ymm2, %ymm4
-; GFNIAVX512VL-NEXT: vpsrlw $1, %ymm2, %ymm6
-; GFNIAVX512VL-NEXT: vpbroadcastd {{.*#+}} ymm8 = [2139062143,2139062143,2139062143,2139062143,2139062143,2139062143,2139062143,2139062143]
-; GFNIAVX512VL-NEXT: vpternlogd $226, %ymm4, %ymm8, %ymm6
-; GFNIAVX512VL-NEXT: vpaddb %ymm3, %ymm3, %ymm3
-; GFNIAVX512VL-NEXT: vpblendvb %ymm3, %ymm6, %ymm2, %ymm2
-; GFNIAVX512VL-NEXT: vpsllw $4, %ymm0, %ymm3
-; GFNIAVX512VL-NEXT: vpsrlw $4, %ymm0, %ymm4
-; GFNIAVX512VL-NEXT: vpternlogd $226, %ymm3, %ymm5, %ymm4
+; GFNIAVX512VL-NEXT: vpbroadcastq {{.*#+}} ymm3 = [16909320,16909320,16909320,16909320]
+; GFNIAVX512VL-NEXT: vgf2p8affineqb $0, %ymm3, %ymm2, %ymm4
+; GFNIAVX512VL-NEXT: vpbroadcastq {{.*#+}} ymm5 = [1161999622361579520,1161999622361579520,1161999622361579520,1161999622361579520]
+; GFNIAVX512VL-NEXT: vgf2p8affineqb $0, %ymm5, %ymm2, %ymm6
+; GFNIAVX512VL-NEXT: vpor %ymm4, %ymm6, %ymm4
+; GFNIAVX512VL-NEXT: vextracti64x4 $1, %zmm1, %ymm6
+; GFNIAVX512VL-NEXT: vpsllw $5, %ymm6, %ymm6
+; GFNIAVX512VL-NEXT: vpblendvb %ymm6, %ymm4, %ymm2, %ymm2
+; GFNIAVX512VL-NEXT: vpbroadcastq {{.*#+}} ymm4 = [258,258,258,258]
+; GFNIAVX512VL-NEXT: vgf2p8affineqb $0, %ymm4, %ymm2, %ymm7
+; GFNIAVX512VL-NEXT: vpbroadcastq {{.*#+}} ymm8 = [290499906672525312,290499906672525312,290499906672525312,290499906672525312]
+; GFNIAVX512VL-NEXT: vgf2p8affineqb $0, %ymm8, %ymm2, %ymm9
+; GFNIAVX512VL-NEXT: vpor %ymm7, %ymm9, %ymm7
+; GFNIAVX512VL-NEXT: vpaddb %ymm6, %ymm6, %ymm6
+; GFNIAVX512VL-NEXT: vpblendvb %ymm6, %ymm7, %ymm2, %ymm2
+; GFNIAVX512VL-NEXT: vpbroadcastq {{.*#+}} ymm7 = [1,1,1,1]
+; GFNIAVX512VL-NEXT: vgf2p8affineqb $0, %ymm7, %ymm2, %ymm9
+; GFNIAVX512VL-NEXT: vpbroadcastq {{.*#+}} ymm10 = [145249953336295424,145249953336295424,145249953336295424,145249953336295424]
+; GFNIAVX512VL-NEXT: vgf2p8affineqb $0, %ymm10, %ymm2, %ymm11
+; GFNIAVX512VL-NEXT: vpor %ymm9, %ymm11, %ymm9
+; GFNIAVX512VL-NEXT: vpaddb %ymm6, %ymm6, %ymm6
+; GFNIAVX512VL-NEXT: vpblendvb %ymm6, %ymm9, %ymm2, %ymm2
+; GFNIAVX512VL-NEXT: vgf2p8affineqb $0, %ymm3, %ymm0, %ymm3
+; GFNIAVX512VL-NEXT: vgf2p8affineqb $0, %ymm5, %ymm0, %ymm5
+; GFNIAVX512VL-NEXT: vpor %ymm3, %ymm5, %ymm3
; GFNIAVX512VL-NEXT: vpsllw $5, %ymm1, %ymm1
-; GFNIAVX512VL-NEXT: vpblendvb %ymm1, %ymm4, %ymm0, %ymm0
-; GFNIAVX512VL-NEXT: vpsllw $6, %ymm0, %ymm3
-; GFNIAVX512VL-NEXT: vpsrlw $2, %ymm0, %ymm4
-; GFNIAVX512VL-NEXT: vpternlogd $226, %ymm3, %ymm7, %ymm4
+; GFNIAVX512VL-NEXT: vpblendvb %ymm1, %ymm3, %ymm0, %ymm0
+; GFNIAVX512VL-NEXT: vgf2p8affineqb $0, %ymm4, %ymm0, %ymm3
+; GFNIAVX512VL-NEXT: vgf2p8affineqb $0, %ymm8, %ymm0, %ymm4
+; GFNIAVX512VL-NEXT: vpor %ymm3, %ymm4, %ymm3
; GFNIAVX512VL-NEXT: vpaddb %ymm1, %ymm1, %ymm1
-; GFNIAVX512VL-NEXT: vpblendvb %ymm1, %ymm4, %ymm0, %ymm0
-; GFNIAVX512VL-NEXT: vpsllw $7, %ymm0, %ymm3
-; GFNIAVX512VL-NEXT: vpsrlw $1, %ymm0, %ymm4
-; GFNIAVX512VL-NEXT: vpternlogd $226, %ymm3, %ymm8, %ymm4
+; GFNIAVX512VL-NEXT: vpblendvb %ymm1, %ymm3, %ymm0, %ymm0
+; GFNIAVX512VL-NEXT: vgf2p8affineqb $0, %ymm7, %ymm0, %ymm3
+; GFNIAVX512VL-NEXT: vgf2p8affineqb $0, %ymm10, %ymm0, %ymm4
+; GFNIAVX512VL-NEXT: vpor %ymm3, %ymm4, %ymm3
; GFNIAVX512VL-NEXT: vpaddb %ymm1, %ymm1, %ymm1
-; GFNIAVX512VL-NEXT: vpblendvb %ymm1, %ymm4, %ymm0, %ymm0
+; GFNIAVX512VL-NEXT: vpblendvb %ymm1, %ymm3, %ymm0, %ymm0
; GFNIAVX512VL-NEXT: vinserti64x4 $1, %ymm2, %zmm0, %zmm0
; GFNIAVX512VL-NEXT: retq
;
@@ -2464,85 +2257,31 @@ define <64 x i8> @constant_rotr_v64i8(<64 x i8> %a) nounwind {
define <64 x i8> @splatconstant_rotl_v64i8(<64 x i8> %a) nounwind {
; GFNISSE-LABEL: splatconstant_rotl_v64i8:
; GFNISSE: # %bb.0:
-; GFNISSE-NEXT: movdqa %xmm0, %xmm4
-; GFNISSE-NEXT: psrlw $7, %xmm4
-; GFNISSE-NEXT: movdqa {{.*#+}} xmm5 = [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1]
-; GFNISSE-NEXT: pand %xmm5, %xmm4
-; GFNISSE-NEXT: paddb %xmm0, %xmm0
-; GFNISSE-NEXT: por %xmm4, %xmm0
-; GFNISSE-NEXT: movdqa %xmm1, %xmm4
-; GFNISSE-NEXT: psrlw $7, %xmm4
-; GFNISSE-NEXT: pand %xmm5, %xmm4
-; GFNISSE-NEXT: paddb %xmm1, %xmm1
-; GFNISSE-NEXT: por %xmm4, %xmm1
-; GFNISSE-NEXT: movdqa %xmm2, %xmm4
-; GFNISSE-NEXT: psrlw $7, %xmm4
-; GFNISSE-NEXT: pand %xmm5, %xmm4
-; GFNISSE-NEXT: paddb %xmm2, %xmm2
-; GFNISSE-NEXT: por %xmm4, %xmm2
-; GFNISSE-NEXT: movdqa %xmm3, %xmm4
-; GFNISSE-NEXT: psrlw $7, %xmm4
-; GFNISSE-NEXT: pand %xmm5, %xmm4
-; GFNISSE-NEXT: paddb %xmm3, %xmm3
-; GFNISSE-NEXT: por %xmm4, %xmm3
+; GFNISSE-NEXT: movdqa {{.*#+}} xmm4 = [9223655728169885760,9223655728169885760]
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm4, %xmm0
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm4, %xmm1
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm4, %xmm2
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm4, %xmm3
; GFNISSE-NEXT: retq
;
; GFNIAVX1-LABEL: splatconstant_rotl_v64i8:
; GFNIAVX1: # %bb.0:
-; GFNIAVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
-; GFNIAVX1-NEXT: vpsrlw $7, %xmm2, %xmm3
-; GFNIAVX1-NEXT: vbroadcastss {{.*#+}} xmm4 = [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1]
-; GFNIAVX1-NEXT: vpand %xmm4, %xmm3, %xmm3
-; GFNIAVX1-NEXT: vpaddb %xmm2, %xmm2, %xmm2
-; GFNIAVX1-NEXT: vpor %xmm3, %xmm2, %xmm2
-; GFNIAVX1-NEXT: vpsrlw $7, %xmm0, %xmm3
-; GFNIAVX1-NEXT: vpand %xmm4, %xmm3, %xmm3
-; GFNIAVX1-NEXT: vpaddb %xmm0, %xmm0, %xmm0
-; GFNIAVX1-NEXT: vpor %xmm3, %xmm0, %xmm0
-; GFNIAVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
-; GFNIAVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
-; GFNIAVX1-NEXT: vpsrlw $7, %xmm2, %xmm3
-; GFNIAVX1-NEXT: vpand %xmm4, %xmm3, %xmm3
-; GFNIAVX1-NEXT: vpaddb %xmm2, %xmm2, %xmm2
-; GFNIAVX1-NEXT: vpor %xmm3, %xmm2, %xmm2
-; GFNIAVX1-NEXT: vpsrlw $7, %xmm1, %xmm3
-; GFNIAVX1-NEXT: vpand %xmm4, %xmm3, %xmm3
-; GFNIAVX1-NEXT: vpaddb %xmm1, %xmm1, %xmm1
-; GFNIAVX1-NEXT: vpor %xmm3, %xmm1, %xmm1
-; GFNIAVX1-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1
+; GFNIAVX1-NEXT: vbroadcastsd {{.*#+}} ymm2 = [9223655728169885760,9223655728169885760,9223655728169885760,9223655728169885760]
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %ymm2, %ymm0, %ymm0
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %ymm2, %ymm1, %ymm1
; GFNIAVX1-NEXT: retq
;
; GFNIAVX2-LABEL: splatconstant_rotl_v64i8:
; GFNIAVX2: # %bb.0:
-; GFNIAVX2-NEXT: vpsrlw $7, %ymm0, %ymm2
-; GFNIAVX2-NEXT: vpbroadcastb {{.*#+}} ymm3 = [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1]
-; GFNIAVX2-NEXT: vpand %ymm3, %ymm2, %ymm2
-; GFNIAVX2-NEXT: vpaddb %ymm0, %ymm0, %ymm0
-; GFNIAVX2-NEXT: vpor %ymm2, %ymm0, %ymm0
-; GFNIAVX2-NEXT: vpsrlw $7, %ymm1, %ymm2
-; GFNIAVX2-NEXT: vpand %ymm3, %ymm2, %ymm2
-; GFNIAVX2-NEXT: vpaddb %ymm1, %ymm1, %ymm1
-; GFNIAVX2-NEXT: vpor %ymm2, %ymm1, %ymm1
+; GFNIAVX2-NEXT: vpbroadcastq {{.*#+}} ymm2 = [9223655728169885760,9223655728169885760,9223655728169885760,9223655728169885760]
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, %ymm2, %ymm0, %ymm0
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, %ymm2, %ymm1, %ymm1
; GFNIAVX2-NEXT: retq
;
-; GFNIAVX512VL-LABEL: splatconstant_rotl_v64i8:
-; GFNIAVX512VL: # %bb.0:
-; GFNIAVX512VL-NEXT: vpsrlw $7, %ymm0, %ymm1
-; GFNIAVX512VL-NEXT: vextracti64x4 $1, %zmm0, %ymm2
-; GFNIAVX512VL-NEXT: vpsrlw $7, %ymm2, %ymm3
-; GFNIAVX512VL-NEXT: vinserti64x4 $1, %ymm3, %zmm1, %zmm1
-; GFNIAVX512VL-NEXT: vpaddb %ymm0, %ymm0, %ymm0
-; GFNIAVX512VL-NEXT: vpaddb %ymm2, %ymm2, %ymm2
-; GFNIAVX512VL-NEXT: vinserti64x4 $1, %ymm2, %zmm0, %zmm0
-; GFNIAVX512VL-NEXT: vpternlogd $248, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm1, %zmm0
-; GFNIAVX512VL-NEXT: retq
-;
-; GFNIAVX512BW-LABEL: splatconstant_rotl_v64i8:
-; GFNIAVX512BW: # %bb.0:
-; GFNIAVX512BW-NEXT: vpsrlw $7, %zmm0, %zmm1
-; GFNIAVX512BW-NEXT: vpaddb %zmm0, %zmm0, %zmm0
-; GFNIAVX512BW-NEXT: vpternlogd $248, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm1, %zmm0
-; GFNIAVX512BW-NEXT: retq
+; GFNIAVX512-LABEL: splatconstant_rotl_v64i8:
+; GFNIAVX512: # %bb.0:
+; GFNIAVX512-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0
+; GFNIAVX512-NEXT: retq
%res = call <64 x i8> @llvm.fshl.v64i8(<64 x i8> %a, <64 x i8> %a, <64 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>)
ret <64 x i8> %res
}
@@ -2551,98 +2290,31 @@ declare <64 x i8> @llvm.fshl.v64i8(<64 x i8>, <64 x i8>, <64 x i8>)
define <64 x i8> @splatconstant_rotr_v64i8(<64 x i8> %a) nounwind {
; GFNISSE-LABEL: splatconstant_rotr_v64i8:
; GFNISSE: # %bb.0:
-; GFNISSE-NEXT: movdqa %xmm0, %xmm5
-; GFNISSE-NEXT: psrlw $2, %xmm5
-; GFNISSE-NEXT: movdqa {{.*#+}} xmm4 = [192,192,192,192,192,192,192,192,192,192,192,192,192,192,192,192]
-; GFNISSE-NEXT: movdqa %xmm4, %xmm6
-; GFNISSE-NEXT: pandn %xmm5, %xmm6
-; GFNISSE-NEXT: psllw $6, %xmm0
-; GFNISSE-NEXT: pand %xmm4, %xmm0
-; GFNISSE-NEXT: por %xmm6, %xmm0
-; GFNISSE-NEXT: movdqa %xmm1, %xmm5
-; GFNISSE-NEXT: psrlw $2, %xmm5
-; GFNISSE-NEXT: movdqa %xmm4, %xmm6
-; GFNISSE-NEXT: pandn %xmm5, %xmm6
-; GFNISSE-NEXT: psllw $6, %xmm1
-; GFNISSE-NEXT: pand %xmm4, %xmm1
-; GFNISSE-NEXT: por %xmm6, %xmm1
-; GFNISSE-NEXT: movdqa %xmm2, %xmm5
-; GFNISSE-NEXT: psrlw $2, %xmm5
-; GFNISSE-NEXT: movdqa %xmm4, %xmm6
-; GFNISSE-NEXT: pandn %xmm5, %xmm6
-; GFNISSE-NEXT: psllw $6, %xmm2
-; GFNISSE-NEXT: pand %xmm4, %xmm2
-; GFNISSE-NEXT: por %xmm6, %xmm2
-; GFNISSE-NEXT: movdqa %xmm3, %xmm5
-; GFNISSE-NEXT: psrlw $2, %xmm5
-; GFNISSE-NEXT: psllw $6, %xmm3
-; GFNISSE-NEXT: pand %xmm4, %xmm3
-; GFNISSE-NEXT: pandn %xmm5, %xmm4
-; GFNISSE-NEXT: por %xmm4, %xmm3
+; GFNISSE-NEXT: movdqa {{.*#+}} xmm4 = [290499906672525570,290499906672525570]
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm4, %xmm0
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm4, %xmm1
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm4, %xmm2
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm4, %xmm3
; GFNISSE-NEXT: retq
;
; GFNIAVX1-LABEL: splatconstant_rotr_v64i8:
; GFNIAVX1: # %bb.0:
-; GFNIAVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
-; GFNIAVX1-NEXT: vpsrlw $2, %xmm2, %xmm3
-; GFNIAVX1-NEXT: vbroadcastss {{.*#+}} xmm4 = [192,192,192,192,192,192,192,192,192,192,192,192,192,192,192,192]
-; GFNIAVX1-NEXT: vpandn %xmm3, %xmm4, %xmm3
-; GFNIAVX1-NEXT: vpsllw $6, %xmm2, %xmm2
-; GFNIAVX1-NEXT: vpand %xmm4, %xmm2, %xmm2
-; GFNIAVX1-NEXT: vpor %xmm3, %xmm2, %xmm2
-; GFNIAVX1-NEXT: vpsrlw $2, %xmm0, %xmm3
-; GFNIAVX1-NEXT: vpandn %xmm3, %xmm4, %xmm3
-; GFNIAVX1-NEXT: vpsllw $6, %xmm0, %xmm0
-; GFNIAVX1-NEXT: vpand %xmm4, %xmm0, %xmm0
-; GFNIAVX1-NEXT: vpor %xmm3, %xmm0, %xmm0
-; GFNIAVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
-; GFNIAVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
-; GFNIAVX1-NEXT: vpsrlw $2, %xmm2, %xmm3
-; GFNIAVX1-NEXT: vpandn %xmm3, %xmm4, %xmm3
-; GFNIAVX1-NEXT: vpsllw $6, %xmm2, %xmm2
-; GFNIAVX1-NEXT: vpand %xmm4, %xmm2, %xmm2
-; GFNIAVX1-NEXT: vpor %xmm3, %xmm2, %xmm2
-; GFNIAVX1-NEXT: vpsrlw $2, %xmm1, %xmm3
-; GFNIAVX1-NEXT: vpandn %xmm3, %xmm4, %xmm3
-; GFNIAVX1-NEXT: vpsllw $6, %xmm1, %xmm1
-; GFNIAVX1-NEXT: vpand %xmm4, %xmm1, %xmm1
-; GFNIAVX1-NEXT: vpor %xmm3, %xmm1, %xmm1
-; GFNIAVX1-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1
+; GFNIAVX1-NEXT: vbroadcastsd {{.*#+}} ymm2 = [290499906672525570,290499906672525570,290499906672525570,290499906672525570]
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %ymm2, %ymm0, %ymm0
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %ymm2, %ymm1, %ymm1
; GFNIAVX1-NEXT: retq
;
; GFNIAVX2-LABEL: splatconstant_rotr_v64i8:
; GFNIAVX2: # %bb.0:
-; GFNIAVX2-NEXT: vpsrlw $2, %ymm0, %ymm2
-; GFNIAVX2-NEXT: vpbroadcastb {{.*#+}} ymm3 = [192,192,192,192,192,192,192,192,192,192,192,192,192,192,192,192,192,192,192,192,192,192,192,192,192,192,192,192,192,192,192,192]
-; GFNIAVX2-NEXT: vpandn %ymm2, %ymm3, %ymm2
-; GFNIAVX2-NEXT: vpsllw $6, %ymm0, %ymm0
-; GFNIAVX2-NEXT: vpand %ymm3, %ymm0, %ymm0
-; GFNIAVX2-NEXT: vpor %ymm2, %ymm0, %ymm0
-; GFNIAVX2-NEXT: vpsrlw $2, %ymm1, %ymm2
-; GFNIAVX2-NEXT: vpandn %ymm2, %ymm3, %ymm2
-; GFNIAVX2-NEXT: vpsllw $6, %ymm1, %ymm1
-; GFNIAVX2-NEXT: vpand %ymm3, %ymm1, %ymm1
-; GFNIAVX2-NEXT: vpor %ymm2, %ymm1, %ymm1
+; GFNIAVX2-NEXT: vpbroadcastq {{.*#+}} ymm2 = [290499906672525570,290499906672525570,290499906672525570,290499906672525570]
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, %ymm2, %ymm0, %ymm0
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, %ymm2, %ymm1, %ymm1
; GFNIAVX2-NEXT: retq
;
-; GFNIAVX512VL-LABEL: splatconstant_rotr_v64i8:
-; GFNIAVX512VL: # %bb.0:
-; GFNIAVX512VL-NEXT: vpsllw $6, %ymm0, %ymm1
-; GFNIAVX512VL-NEXT: vextracti64x4 $1, %zmm0, %ymm2
-; GFNIAVX512VL-NEXT: vpsllw $6, %ymm2, %ymm3
-; GFNIAVX512VL-NEXT: vinserti64x4 $1, %ymm3, %zmm1, %zmm1
-; GFNIAVX512VL-NEXT: vpsrlw $2, %ymm0, %ymm0
-; GFNIAVX512VL-NEXT: vpsrlw $2, %ymm2, %ymm2
-; GFNIAVX512VL-NEXT: vinserti64x4 $1, %ymm2, %zmm0, %zmm0
-; GFNIAVX512VL-NEXT: vpternlogd $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm1, %zmm0
-; GFNIAVX512VL-NEXT: retq
-;
-; GFNIAVX512BW-LABEL: splatconstant_rotr_v64i8:
-; GFNIAVX512BW: # %bb.0:
-; GFNIAVX512BW-NEXT: vpsllw $6, %zmm0, %zmm1
-; GFNIAVX512BW-NEXT: vpsrlw $2, %zmm0, %zmm0
-; GFNIAVX512BW-NEXT: vpternlogd $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm1, %zmm0
-; GFNIAVX512BW-NEXT: retq
+; GFNIAVX512-LABEL: splatconstant_rotr_v64i8:
+; GFNIAVX512: # %bb.0:
+; GFNIAVX512-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0
+; GFNIAVX512-NEXT: retq
%res = call <64 x i8> @llvm.fshr.v64i8(<64 x i8> %a, <64 x i8> %a, <64 x i8> <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2>)
ret <64 x i8> %res
}
diff --git a/llvm/test/CodeGen/X86/gfni-shifts.ll b/llvm/test/CodeGen/X86/gfni-shifts.ll
index f79407d08ab0a3..6232488bea71b4 100644
--- a/llvm/test/CodeGen/X86/gfni-shifts.ll
+++ b/llvm/test/CodeGen/X86/gfni-shifts.ll
@@ -15,13 +15,11 @@ define <16 x i8> @var_shl_v16i8(<16 x i8> %a, <16 x i8> %b) nounwind {
; GFNISSE-NEXT: movdqa %xmm0, %xmm2
; GFNISSE-NEXT: psllw $5, %xmm1
; GFNISSE-NEXT: movdqa %xmm0, %xmm3
-; GFNISSE-NEXT: psllw $4, %xmm3
-; GFNISSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
+; GFNISSE-NEXT: gf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
; GFNISSE-NEXT: movdqa %xmm1, %xmm0
; GFNISSE-NEXT: pblendvb %xmm0, %xmm3, %xmm2
; GFNISSE-NEXT: movdqa %xmm2, %xmm3
-; GFNISSE-NEXT: psllw $2, %xmm3
-; GFNISSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
+; GFNISSE-NEXT: gf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
; GFNISSE-NEXT: paddb %xmm1, %xmm1
; GFNISSE-NEXT: movdqa %xmm1, %xmm0
; GFNISSE-NEXT: pblendvb %xmm0, %xmm3, %xmm2
@@ -36,11 +34,9 @@ define <16 x i8> @var_shl_v16i8(<16 x i8> %a, <16 x i8> %b) nounwind {
; GFNIAVX1OR2-LABEL: var_shl_v16i8:
; GFNIAVX1OR2: # %bb.0:
; GFNIAVX1OR2-NEXT: vpsllw $5, %xmm1, %xmm1
-; GFNIAVX1OR2-NEXT: vpsllw $4, %xmm0, %xmm2
-; GFNIAVX1OR2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
+; GFNIAVX1OR2-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm2
; GFNIAVX1OR2-NEXT: vpblendvb %xmm1, %xmm2, %xmm0, %xmm0
-; GFNIAVX1OR2-NEXT: vpsllw $2, %xmm0, %xmm2
-; GFNIAVX1OR2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
+; GFNIAVX1OR2-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm2
; GFNIAVX1OR2-NEXT: vpaddb %xmm1, %xmm1, %xmm1
; GFNIAVX1OR2-NEXT: vpblendvb %xmm1, %xmm2, %xmm0, %xmm0
; GFNIAVX1OR2-NEXT: vpaddb %xmm0, %xmm0, %xmm2
@@ -75,19 +71,16 @@ define <16 x i8> @var_lshr_v16i8(<16 x i8> %a, <16 x i8> %b) nounwind {
; GFNISSE-NEXT: movdqa %xmm0, %xmm2
; GFNISSE-NEXT: psllw $5, %xmm1
; GFNISSE-NEXT: movdqa %xmm0, %xmm3
-; GFNISSE-NEXT: psrlw $4, %xmm3
-; GFNISSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
+; GFNISSE-NEXT: gf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
; GFNISSE-NEXT: movdqa %xmm1, %xmm0
; GFNISSE-NEXT: pblendvb %xmm0, %xmm3, %xmm2
; GFNISSE-NEXT: movdqa %xmm2, %xmm3
-; GFNISSE-NEXT: psrlw $2, %xmm3
-; GFNISSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
+; GFNISSE-NEXT: gf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
; GFNISSE-NEXT: paddb %xmm1, %xmm1
; GFNISSE-NEXT: movdqa %xmm1, %xmm0
; GFNISSE-NEXT: pblendvb %xmm0, %xmm3, %xmm2
; GFNISSE-NEXT: movdqa %xmm2, %xmm3
-; GFNISSE-NEXT: psrlw $1, %xmm3
-; GFNISSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
+; GFNISSE-NEXT: gf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
; GFNISSE-NEXT: paddb %xmm1, %xmm1
; GFNISSE-NEXT: movdqa %xmm1, %xmm0
; GFNISSE-NEXT: pblendvb %xmm0, %xmm3, %xmm2
@@ -97,15 +90,12 @@ define <16 x i8> @var_lshr_v16i8(<16 x i8> %a, <16 x i8> %b) nounwind {
; GFNIAVX1OR2-LABEL: var_lshr_v16i8:
; GFNIAVX1OR2: # %bb.0:
; GFNIAVX1OR2-NEXT: vpsllw $5, %xmm1, %xmm1
-; GFNIAVX1OR2-NEXT: vpsrlw $4, %xmm0, %xmm2
-; GFNIAVX1OR2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
+; GFNIAVX1OR2-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm2
; GFNIAVX1OR2-NEXT: vpblendvb %xmm1, %xmm2, %xmm0, %xmm0
-; GFNIAVX1OR2-NEXT: vpsrlw $2, %xmm0, %xmm2
-; GFNIAVX1OR2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
+; GFNIAVX1OR2-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm2
; GFNIAVX1OR2-NEXT: vpaddb %xmm1, %xmm1, %xmm1
; GFNIAVX1OR2-NEXT: vpblendvb %xmm1, %xmm2, %xmm0, %xmm0
-; GFNIAVX1OR2-NEXT: vpsrlw $1, %xmm0, %xmm2
-; GFNIAVX1OR2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
+; GFNIAVX1OR2-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm2
; GFNIAVX1OR2-NEXT: vpaddb %xmm1, %xmm1, %xmm1
; GFNIAVX1OR2-NEXT: vpblendvb %xmm1, %xmm2, %xmm0, %xmm0
; GFNIAVX1OR2-NEXT: retq
@@ -562,20 +552,17 @@ define <16 x i8> @constant_ashr_v16i8(<16 x i8> %a) nounwind {
define <16 x i8> @splatconstant_shl_v16i8(<16 x i8> %a) nounwind {
; GFNISSE-LABEL: splatconstant_shl_v16i8:
; GFNISSE: # %bb.0:
-; GFNISSE-NEXT: psllw $3, %xmm0
-; GFNISSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; GFNISSE-NEXT: gf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; GFNISSE-NEXT: retq
;
; GFNIAVX1OR2-LABEL: splatconstant_shl_v16i8:
; GFNIAVX1OR2: # %bb.0:
-; GFNIAVX1OR2-NEXT: vpsllw $3, %xmm0, %xmm0
-; GFNIAVX1OR2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; GFNIAVX1OR2-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; GFNIAVX1OR2-NEXT: retq
;
; GFNIAVX512-LABEL: splatconstant_shl_v16i8:
; GFNIAVX512: # %bb.0:
-; GFNIAVX512-NEXT: vpsllw $3, %xmm0, %xmm0
-; GFNIAVX512-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
+; GFNIAVX512-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0
; GFNIAVX512-NEXT: retq
%shift = shl <16 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
ret <16 x i8> %shift
@@ -584,20 +571,17 @@ define <16 x i8> @splatconstant_shl_v16i8(<16 x i8> %a) nounwind {
define <16 x i8> @splatconstant_lshr_v16i8(<16 x i8> %a) nounwind {
; GFNISSE-LABEL: splatconstant_lshr_v16i8:
; GFNISSE: # %bb.0:
-; GFNISSE-NEXT: psrlw $7, %xmm0
-; GFNISSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; GFNISSE-NEXT: gf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; GFNISSE-NEXT: retq
;
; GFNIAVX1OR2-LABEL: splatconstant_lshr_v16i8:
; GFNIAVX1OR2: # %bb.0:
-; GFNIAVX1OR2-NEXT: vpsrlw $7, %xmm0, %xmm0
-; GFNIAVX1OR2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; GFNIAVX1OR2-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; GFNIAVX1OR2-NEXT: retq
;
; GFNIAVX512-LABEL: splatconstant_lshr_v16i8:
; GFNIAVX512: # %bb.0:
-; GFNIAVX512-NEXT: vpsrlw $7, %xmm0, %xmm0
-; GFNIAVX512-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
+; GFNIAVX512-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0
; GFNIAVX512-NEXT: retq
%shift = lshr <16 x i8> %a, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
ret <16 x i8> %shift
@@ -606,46 +590,18 @@ define <16 x i8> @splatconstant_lshr_v16i8(<16 x i8> %a) nounwind {
define <16 x i8> @splatconstant_ashr_v16i8(<16 x i8> %a) nounwind {
; GFNISSE-LABEL: splatconstant_ashr_v16i8:
; GFNISSE: # %bb.0:
-; GFNISSE-NEXT: psrlw $4, %xmm0
-; GFNISSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
-; GFNISSE-NEXT: movdqa {{.*#+}} xmm1 = [8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8]
-; GFNISSE-NEXT: pxor %xmm1, %xmm0
-; GFNISSE-NEXT: psubb %xmm1, %xmm0
+; GFNISSE-NEXT: gf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; GFNISSE-NEXT: retq
;
-; GFNIAVX1-LABEL: splatconstant_ashr_v16i8:
-; GFNIAVX1: # %bb.0:
-; GFNIAVX1-NEXT: vpsrlw $4, %xmm0, %xmm0
-; GFNIAVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
-; GFNIAVX1-NEXT: vbroadcastss {{.*#+}} xmm1 = [8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8]
-; GFNIAVX1-NEXT: vpxor %xmm1, %xmm0, %xmm0
-; GFNIAVX1-NEXT: vpsubb %xmm1, %xmm0, %xmm0
-; GFNIAVX1-NEXT: retq
-;
-; GFNIAVX2-LABEL: splatconstant_ashr_v16i8:
-; GFNIAVX2: # %bb.0:
-; GFNIAVX2-NEXT: vpsrlw $4, %xmm0, %xmm0
-; GFNIAVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
-; GFNIAVX2-NEXT: vpbroadcastb {{.*#+}} xmm1 = [8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8]
-; GFNIAVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0
-; GFNIAVX2-NEXT: vpsubb %xmm1, %xmm0, %xmm0
-; GFNIAVX2-NEXT: retq
-;
-; GFNIAVX512VL-LABEL: splatconstant_ashr_v16i8:
-; GFNIAVX512VL: # %bb.0:
-; GFNIAVX512VL-NEXT: vpsrlw $4, %xmm0, %xmm0
-; GFNIAVX512VL-NEXT: vpbroadcastd {{.*#+}} xmm1 = [8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8]
-; GFNIAVX512VL-NEXT: vpternlogd $108, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm1, %xmm0
-; GFNIAVX512VL-NEXT: vpsubb %xmm1, %xmm0, %xmm0
-; GFNIAVX512VL-NEXT: retq
+; GFNIAVX1OR2-LABEL: splatconstant_ashr_v16i8:
+; GFNIAVX1OR2: # %bb.0:
+; GFNIAVX1OR2-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; GFNIAVX1OR2-NEXT: retq
;
-; GFNIAVX512BW-LABEL: splatconstant_ashr_v16i8:
-; GFNIAVX512BW: # %bb.0:
-; GFNIAVX512BW-NEXT: vpsrlw $4, %xmm0, %xmm0
-; GFNIAVX512BW-NEXT: vpbroadcastb {{.*#+}} xmm1 = [8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8]
-; GFNIAVX512BW-NEXT: vpternlogd $108, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm1, %xmm0
-; GFNIAVX512BW-NEXT: vpsubb %xmm1, %xmm0, %xmm0
-; GFNIAVX512BW-NEXT: retq
+; GFNIAVX512-LABEL: splatconstant_ashr_v16i8:
+; GFNIAVX512: # %bb.0:
+; GFNIAVX512-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0
+; GFNIAVX512-NEXT: retq
%shift = ashr <16 x i8> %a, <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4>
ret <16 x i8> %shift
}
@@ -659,34 +615,30 @@ define <32 x i8> @var_shl_v32i8(<32 x i8> %a, <32 x i8> %b) nounwind {
; GFNISSE: # %bb.0:
; GFNISSE-NEXT: movdqa %xmm2, %xmm4
; GFNISSE-NEXT: movdqa %xmm0, %xmm2
-; GFNISSE-NEXT: movdqa %xmm0, %xmm5
-; GFNISSE-NEXT: psllw $4, %xmm5
-; GFNISSE-NEXT: movdqa {{.*#+}} xmm6 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240]
-; GFNISSE-NEXT: pand %xmm6, %xmm5
+; GFNISSE-NEXT: pmovsxdq {{.*#+}} xmm5 = [16909320,16909320]
+; GFNISSE-NEXT: movdqa %xmm0, %xmm6
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm5, %xmm6
; GFNISSE-NEXT: psllw $5, %xmm4
; GFNISSE-NEXT: movdqa %xmm4, %xmm0
-; GFNISSE-NEXT: pblendvb %xmm0, %xmm5, %xmm2
-; GFNISSE-NEXT: movdqa %xmm2, %xmm5
-; GFNISSE-NEXT: psllw $2, %xmm5
-; GFNISSE-NEXT: movdqa {{.*#+}} xmm7 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252]
-; GFNISSE-NEXT: pand %xmm7, %xmm5
+; GFNISSE-NEXT: pblendvb %xmm0, %xmm6, %xmm2
+; GFNISSE-NEXT: movdqa {{.*#+}} xmm6 = [1108169199648,1108169199648]
+; GFNISSE-NEXT: movdqa %xmm2, %xmm7
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm6, %xmm7
; GFNISSE-NEXT: paddb %xmm4, %xmm4
; GFNISSE-NEXT: movdqa %xmm4, %xmm0
-; GFNISSE-NEXT: pblendvb %xmm0, %xmm5, %xmm2
-; GFNISSE-NEXT: movdqa %xmm2, %xmm5
-; GFNISSE-NEXT: paddb %xmm2, %xmm5
+; GFNISSE-NEXT: pblendvb %xmm0, %xmm7, %xmm2
+; GFNISSE-NEXT: movdqa %xmm2, %xmm7
+; GFNISSE-NEXT: paddb %xmm2, %xmm7
; GFNISSE-NEXT: paddb %xmm4, %xmm4
; GFNISSE-NEXT: movdqa %xmm4, %xmm0
-; GFNISSE-NEXT: pblendvb %xmm0, %xmm5, %xmm2
+; GFNISSE-NEXT: pblendvb %xmm0, %xmm7, %xmm2
; GFNISSE-NEXT: movdqa %xmm1, %xmm4
-; GFNISSE-NEXT: psllw $4, %xmm4
-; GFNISSE-NEXT: pand %xmm6, %xmm4
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm5, %xmm4
; GFNISSE-NEXT: psllw $5, %xmm3
; GFNISSE-NEXT: movdqa %xmm3, %xmm0
; GFNISSE-NEXT: pblendvb %xmm0, %xmm4, %xmm1
; GFNISSE-NEXT: movdqa %xmm1, %xmm4
-; GFNISSE-NEXT: psllw $2, %xmm4
-; GFNISSE-NEXT: pand %xmm7, %xmm4
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm6, %xmm4
; GFNISSE-NEXT: paddb %xmm3, %xmm3
; GFNISSE-NEXT: movdqa %xmm3, %xmm0
; GFNISSE-NEXT: pblendvb %xmm0, %xmm4, %xmm1
@@ -701,26 +653,24 @@ define <32 x i8> @var_shl_v32i8(<32 x i8> %a, <32 x i8> %b) nounwind {
; GFNIAVX1-LABEL: var_shl_v32i8:
; GFNIAVX1: # %bb.0:
; GFNIAVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
-; GFNIAVX1-NEXT: vpsllw $4, %xmm2, %xmm3
-; GFNIAVX1-NEXT: vbroadcastss {{.*#+}} xmm4 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240]
-; GFNIAVX1-NEXT: vpand %xmm4, %xmm3, %xmm3
+; GFNIAVX1-NEXT: vmovddup {{.*#+}} xmm3 = [16909320,16909320]
+; GFNIAVX1-NEXT: # xmm3 = mem[0,0]
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm3, %xmm2, %xmm4
; GFNIAVX1-NEXT: vextractf128 $1, %ymm1, %xmm5
; GFNIAVX1-NEXT: vpsllw $5, %xmm5, %xmm5
-; GFNIAVX1-NEXT: vpblendvb %xmm5, %xmm3, %xmm2, %xmm2
-; GFNIAVX1-NEXT: vpsllw $2, %xmm2, %xmm3
-; GFNIAVX1-NEXT: vbroadcastss {{.*#+}} xmm6 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252]
-; GFNIAVX1-NEXT: vpand %xmm6, %xmm3, %xmm3
+; GFNIAVX1-NEXT: vpblendvb %xmm5, %xmm4, %xmm2, %xmm2
+; GFNIAVX1-NEXT: vmovddup {{.*#+}} xmm4 = [1108169199648,1108169199648]
+; GFNIAVX1-NEXT: # xmm4 = mem[0,0]
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm4, %xmm2, %xmm6
; GFNIAVX1-NEXT: vpaddb %xmm5, %xmm5, %xmm5
-; GFNIAVX1-NEXT: vpblendvb %xmm5, %xmm3, %xmm2, %xmm2
-; GFNIAVX1-NEXT: vpaddb %xmm2, %xmm2, %xmm3
+; GFNIAVX1-NEXT: vpblendvb %xmm5, %xmm6, %xmm2, %xmm2
+; GFNIAVX1-NEXT: vpaddb %xmm2, %xmm2, %xmm6
; GFNIAVX1-NEXT: vpaddb %xmm5, %xmm5, %xmm5
-; GFNIAVX1-NEXT: vpblendvb %xmm5, %xmm3, %xmm2, %xmm2
-; GFNIAVX1-NEXT: vpsllw $4, %xmm0, %xmm3
-; GFNIAVX1-NEXT: vpand %xmm4, %xmm3, %xmm3
+; GFNIAVX1-NEXT: vpblendvb %xmm5, %xmm6, %xmm2, %xmm2
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm3, %xmm0, %xmm3
; GFNIAVX1-NEXT: vpsllw $5, %xmm1, %xmm1
; GFNIAVX1-NEXT: vpblendvb %xmm1, %xmm3, %xmm0, %xmm0
-; GFNIAVX1-NEXT: vpsllw $2, %xmm0, %xmm3
-; GFNIAVX1-NEXT: vpand %xmm6, %xmm3, %xmm3
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm4, %xmm0, %xmm3
; GFNIAVX1-NEXT: vpaddb %xmm1, %xmm1, %xmm1
; GFNIAVX1-NEXT: vpblendvb %xmm1, %xmm3, %xmm0, %xmm0
; GFNIAVX1-NEXT: vpaddb %xmm0, %xmm0, %xmm3
@@ -731,12 +681,12 @@ define <32 x i8> @var_shl_v32i8(<32 x i8> %a, <32 x i8> %b) nounwind {
;
; GFNIAVX2-LABEL: var_shl_v32i8:
; GFNIAVX2: # %bb.0:
+; GFNIAVX2-NEXT: vpbroadcastq {{.*#+}} ymm2 = [16909320,16909320,16909320,16909320]
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, %ymm2, %ymm0, %ymm2
; GFNIAVX2-NEXT: vpsllw $5, %ymm1, %ymm1
-; GFNIAVX2-NEXT: vpsllw $4, %ymm0, %ymm2
-; GFNIAVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
; GFNIAVX2-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
-; GFNIAVX2-NEXT: vpsllw $2, %ymm0, %ymm2
-; GFNIAVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
+; GFNIAVX2-NEXT: vpbroadcastq {{.*#+}} ymm2 = [1108169199648,1108169199648,1108169199648,1108169199648]
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, %ymm2, %ymm0, %ymm2
; GFNIAVX2-NEXT: vpaddb %ymm1, %ymm1, %ymm1
; GFNIAVX2-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
; GFNIAVX2-NEXT: vpaddb %ymm0, %ymm0, %ymm2
@@ -747,11 +697,9 @@ define <32 x i8> @var_shl_v32i8(<32 x i8> %a, <32 x i8> %b) nounwind {
; GFNIAVX512VL-LABEL: var_shl_v32i8:
; GFNIAVX512VL: # %bb.0:
; GFNIAVX512VL-NEXT: vpsllw $5, %ymm1, %ymm1
-; GFNIAVX512VL-NEXT: vpsllw $4, %ymm0, %ymm2
-; GFNIAVX512VL-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm2, %ymm2
+; GFNIAVX512VL-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %ymm2
; GFNIAVX512VL-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
-; GFNIAVX512VL-NEXT: vpsllw $2, %ymm0, %ymm2
-; GFNIAVX512VL-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm2, %ymm2
+; GFNIAVX512VL-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %ymm2
; GFNIAVX512VL-NEXT: vpaddb %ymm1, %ymm1, %ymm1
; GFNIAVX512VL-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
; GFNIAVX512VL-NEXT: vpaddb %ymm0, %ymm0, %ymm2
@@ -775,42 +723,36 @@ define <32 x i8> @var_lshr_v32i8(<32 x i8> %a, <32 x i8> %b) nounwind {
; GFNISSE: # %bb.0:
; GFNISSE-NEXT: movdqa %xmm2, %xmm4
; GFNISSE-NEXT: movdqa %xmm0, %xmm2
-; GFNISSE-NEXT: movdqa %xmm0, %xmm5
-; GFNISSE-NEXT: psrlw $4, %xmm5
-; GFNISSE-NEXT: movdqa {{.*#+}} xmm6 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
-; GFNISSE-NEXT: pand %xmm6, %xmm5
+; GFNISSE-NEXT: movdqa {{.*#+}} xmm5 = [1161999622361579520,1161999622361579520]
+; GFNISSE-NEXT: movdqa %xmm0, %xmm6
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm5, %xmm6
; GFNISSE-NEXT: psllw $5, %xmm4
; GFNISSE-NEXT: movdqa %xmm4, %xmm0
-; GFNISSE-NEXT: pblendvb %xmm0, %xmm5, %xmm2
-; GFNISSE-NEXT: movdqa %xmm2, %xmm5
-; GFNISSE-NEXT: psrlw $2, %xmm5
-; GFNISSE-NEXT: movdqa {{.*#+}} xmm7 = [63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63]
-; GFNISSE-NEXT: pand %xmm7, %xmm5
+; GFNISSE-NEXT: pblendvb %xmm0, %xmm6, %xmm2
+; GFNISSE-NEXT: movdqa {{.*#+}} xmm6 = [290499906672525312,290499906672525312]
+; GFNISSE-NEXT: movdqa %xmm2, %xmm7
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm6, %xmm7
; GFNISSE-NEXT: paddb %xmm4, %xmm4
; GFNISSE-NEXT: movdqa %xmm4, %xmm0
-; GFNISSE-NEXT: pblendvb %xmm0, %xmm5, %xmm2
-; GFNISSE-NEXT: movdqa %xmm2, %xmm5
-; GFNISSE-NEXT: psrlw $1, %xmm5
-; GFNISSE-NEXT: movdqa {{.*#+}} xmm8 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127]
-; GFNISSE-NEXT: pand %xmm8, %xmm5
+; GFNISSE-NEXT: pblendvb %xmm0, %xmm7, %xmm2
+; GFNISSE-NEXT: movdqa {{.*#+}} xmm7 = [145249953336295424,145249953336295424]
+; GFNISSE-NEXT: movdqa %xmm2, %xmm8
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm7, %xmm8
; GFNISSE-NEXT: paddb %xmm4, %xmm4
; GFNISSE-NEXT: movdqa %xmm4, %xmm0
-; GFNISSE-NEXT: pblendvb %xmm0, %xmm5, %xmm2
+; GFNISSE-NEXT: pblendvb %xmm0, %xmm8, %xmm2
; GFNISSE-NEXT: movdqa %xmm1, %xmm4
-; GFNISSE-NEXT: psrlw $4, %xmm4
-; GFNISSE-NEXT: pand %xmm6, %xmm4
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm5, %xmm4
; GFNISSE-NEXT: psllw $5, %xmm3
; GFNISSE-NEXT: movdqa %xmm3, %xmm0
; GFNISSE-NEXT: pblendvb %xmm0, %xmm4, %xmm1
; GFNISSE-NEXT: movdqa %xmm1, %xmm4
-; GFNISSE-NEXT: psrlw $2, %xmm4
-; GFNISSE-NEXT: pand %xmm7, %xmm4
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm6, %xmm4
; GFNISSE-NEXT: paddb %xmm3, %xmm3
; GFNISSE-NEXT: movdqa %xmm3, %xmm0
; GFNISSE-NEXT: pblendvb %xmm0, %xmm4, %xmm1
; GFNISSE-NEXT: movdqa %xmm1, %xmm4
-; GFNISSE-NEXT: psrlw $1, %xmm4
-; GFNISSE-NEXT: pand %xmm8, %xmm4
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm7, %xmm4
; GFNISSE-NEXT: paddb %xmm3, %xmm3
; GFNISSE-NEXT: movdqa %xmm3, %xmm0
; GFNISSE-NEXT: pblendvb %xmm0, %xmm4, %xmm1
@@ -820,32 +762,29 @@ define <32 x i8> @var_lshr_v32i8(<32 x i8> %a, <32 x i8> %b) nounwind {
; GFNIAVX1-LABEL: var_lshr_v32i8:
; GFNIAVX1: # %bb.0:
; GFNIAVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
-; GFNIAVX1-NEXT: vpsrlw $4, %xmm2, %xmm3
-; GFNIAVX1-NEXT: vbroadcastss {{.*#+}} xmm4 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
-; GFNIAVX1-NEXT: vpand %xmm4, %xmm3, %xmm3
+; GFNIAVX1-NEXT: vmovddup {{.*#+}} xmm3 = [1161999622361579520,1161999622361579520]
+; GFNIAVX1-NEXT: # xmm3 = mem[0,0]
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm3, %xmm2, %xmm4
; GFNIAVX1-NEXT: vextractf128 $1, %ymm1, %xmm5
; GFNIAVX1-NEXT: vpsllw $5, %xmm5, %xmm5
-; GFNIAVX1-NEXT: vpblendvb %xmm5, %xmm3, %xmm2, %xmm2
-; GFNIAVX1-NEXT: vpsrlw $2, %xmm2, %xmm3
-; GFNIAVX1-NEXT: vbroadcastss {{.*#+}} xmm6 = [63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63]
-; GFNIAVX1-NEXT: vpand %xmm6, %xmm3, %xmm3
+; GFNIAVX1-NEXT: vpblendvb %xmm5, %xmm4, %xmm2, %xmm2
+; GFNIAVX1-NEXT: vmovddup {{.*#+}} xmm4 = [290499906672525312,290499906672525312]
+; GFNIAVX1-NEXT: # xmm4 = mem[0,0]
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm4, %xmm2, %xmm6
; GFNIAVX1-NEXT: vpaddb %xmm5, %xmm5, %xmm5
-; GFNIAVX1-NEXT: vpblendvb %xmm5, %xmm3, %xmm2, %xmm2
-; GFNIAVX1-NEXT: vpsrlw $1, %xmm2, %xmm3
-; GFNIAVX1-NEXT: vbroadcastss {{.*#+}} xmm7 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127]
-; GFNIAVX1-NEXT: vpand %xmm7, %xmm3, %xmm3
+; GFNIAVX1-NEXT: vpblendvb %xmm5, %xmm6, %xmm2, %xmm2
+; GFNIAVX1-NEXT: vmovddup {{.*#+}} xmm6 = [145249953336295424,145249953336295424]
+; GFNIAVX1-NEXT: # xmm6 = mem[0,0]
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm6, %xmm2, %xmm7
; GFNIAVX1-NEXT: vpaddb %xmm5, %xmm5, %xmm5
-; GFNIAVX1-NEXT: vpblendvb %xmm5, %xmm3, %xmm2, %xmm2
-; GFNIAVX1-NEXT: vpsrlw $4, %xmm0, %xmm3
-; GFNIAVX1-NEXT: vpand %xmm4, %xmm3, %xmm3
+; GFNIAVX1-NEXT: vpblendvb %xmm5, %xmm7, %xmm2, %xmm2
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm3, %xmm0, %xmm3
; GFNIAVX1-NEXT: vpsllw $5, %xmm1, %xmm1
; GFNIAVX1-NEXT: vpblendvb %xmm1, %xmm3, %xmm0, %xmm0
-; GFNIAVX1-NEXT: vpsrlw $2, %xmm0, %xmm3
-; GFNIAVX1-NEXT: vpand %xmm6, %xmm3, %xmm3
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm4, %xmm0, %xmm3
; GFNIAVX1-NEXT: vpaddb %xmm1, %xmm1, %xmm1
; GFNIAVX1-NEXT: vpblendvb %xmm1, %xmm3, %xmm0, %xmm0
-; GFNIAVX1-NEXT: vpsrlw $1, %xmm0, %xmm3
-; GFNIAVX1-NEXT: vpand %xmm7, %xmm3, %xmm3
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm6, %xmm0, %xmm3
; GFNIAVX1-NEXT: vpaddb %xmm1, %xmm1, %xmm1
; GFNIAVX1-NEXT: vpblendvb %xmm1, %xmm3, %xmm0, %xmm0
; GFNIAVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
@@ -853,16 +792,16 @@ define <32 x i8> @var_lshr_v32i8(<32 x i8> %a, <32 x i8> %b) nounwind {
;
; GFNIAVX2-LABEL: var_lshr_v32i8:
; GFNIAVX2: # %bb.0:
+; GFNIAVX2-NEXT: vpbroadcastq {{.*#+}} ymm2 = [1161999622361579520,1161999622361579520,1161999622361579520,1161999622361579520]
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, %ymm2, %ymm0, %ymm2
; GFNIAVX2-NEXT: vpsllw $5, %ymm1, %ymm1
-; GFNIAVX2-NEXT: vpsrlw $4, %ymm0, %ymm2
-; GFNIAVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
; GFNIAVX2-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
-; GFNIAVX2-NEXT: vpsrlw $2, %ymm0, %ymm2
-; GFNIAVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
+; GFNIAVX2-NEXT: vpbroadcastq {{.*#+}} ymm2 = [290499906672525312,290499906672525312,290499906672525312,290499906672525312]
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, %ymm2, %ymm0, %ymm2
; GFNIAVX2-NEXT: vpaddb %ymm1, %ymm1, %ymm1
; GFNIAVX2-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
-; GFNIAVX2-NEXT: vpsrlw $1, %ymm0, %ymm2
-; GFNIAVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
+; GFNIAVX2-NEXT: vpbroadcastq {{.*#+}} ymm2 = [145249953336295424,145249953336295424,145249953336295424,145249953336295424]
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, %ymm2, %ymm0, %ymm2
; GFNIAVX2-NEXT: vpaddb %ymm1, %ymm1, %ymm1
; GFNIAVX2-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
; GFNIAVX2-NEXT: retq
@@ -870,15 +809,12 @@ define <32 x i8> @var_lshr_v32i8(<32 x i8> %a, <32 x i8> %b) nounwind {
; GFNIAVX512VL-LABEL: var_lshr_v32i8:
; GFNIAVX512VL: # %bb.0:
; GFNIAVX512VL-NEXT: vpsllw $5, %ymm1, %ymm1
-; GFNIAVX512VL-NEXT: vpsrlw $4, %ymm0, %ymm2
-; GFNIAVX512VL-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm2, %ymm2
+; GFNIAVX512VL-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %ymm2
; GFNIAVX512VL-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
-; GFNIAVX512VL-NEXT: vpsrlw $2, %ymm0, %ymm2
-; GFNIAVX512VL-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm2, %ymm2
+; GFNIAVX512VL-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %ymm2
; GFNIAVX512VL-NEXT: vpaddb %ymm1, %ymm1, %ymm1
; GFNIAVX512VL-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
-; GFNIAVX512VL-NEXT: vpsrlw $1, %ymm0, %ymm2
-; GFNIAVX512VL-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm2, %ymm2
+; GFNIAVX512VL-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %ymm2
; GFNIAVX512VL-NEXT: vpaddb %ymm1, %ymm1, %ymm1
; GFNIAVX512VL-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
; GFNIAVX512VL-NEXT: retq
@@ -1539,34 +1475,25 @@ define <32 x i8> @constant_ashr_v32i8(<32 x i8> %a) nounwind {
define <32 x i8> @splatconstant_shl_v32i8(<32 x i8> %a) nounwind {
; GFNISSE-LABEL: splatconstant_shl_v32i8:
; GFNISSE: # %bb.0:
-; GFNISSE-NEXT: psllw $6, %xmm0
-; GFNISSE-NEXT: movdqa {{.*#+}} xmm2 = [192,192,192,192,192,192,192,192,192,192,192,192,192,192,192,192]
-; GFNISSE-NEXT: pand %xmm2, %xmm0
-; GFNISSE-NEXT: psllw $6, %xmm1
-; GFNISSE-NEXT: pand %xmm2, %xmm1
+; GFNISSE-NEXT: pmovsxwq {{.*#+}} xmm2 = [258,258]
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm2, %xmm0
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm2, %xmm1
; GFNISSE-NEXT: retq
;
; GFNIAVX1-LABEL: splatconstant_shl_v32i8:
; GFNIAVX1: # %bb.0:
-; GFNIAVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
-; GFNIAVX1-NEXT: vpsllw $6, %xmm1, %xmm1
-; GFNIAVX1-NEXT: vbroadcastss {{.*#+}} xmm2 = [192,192,192,192,192,192,192,192,192,192,192,192,192,192,192,192]
-; GFNIAVX1-NEXT: vpand %xmm2, %xmm1, %xmm1
-; GFNIAVX1-NEXT: vpsllw $6, %xmm0, %xmm0
-; GFNIAVX1-NEXT: vpand %xmm2, %xmm0, %xmm0
-; GFNIAVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; GFNIAVX1-NEXT: retq
;
; GFNIAVX2-LABEL: splatconstant_shl_v32i8:
; GFNIAVX2: # %bb.0:
-; GFNIAVX2-NEXT: vpsllw $6, %ymm0, %ymm0
-; GFNIAVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
+; GFNIAVX2-NEXT: vpbroadcastq {{.*#+}} ymm1 = [258,258,258,258]
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, %ymm1, %ymm0, %ymm0
; GFNIAVX2-NEXT: retq
;
; GFNIAVX512-LABEL: splatconstant_shl_v32i8:
; GFNIAVX512: # %bb.0:
-; GFNIAVX512-NEXT: vpsllw $6, %ymm0, %ymm0
-; GFNIAVX512-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %ymm0
+; GFNIAVX512-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %ymm0
; GFNIAVX512-NEXT: retq
%shift = shl <32 x i8> %a, <i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6>
ret <32 x i8> %shift
@@ -1575,34 +1502,25 @@ define <32 x i8> @splatconstant_shl_v32i8(<32 x i8> %a) nounwind {
define <32 x i8> @splatconstant_lshr_v32i8(<32 x i8> %a) nounwind {
; GFNISSE-LABEL: splatconstant_lshr_v32i8:
; GFNISSE: # %bb.0:
-; GFNISSE-NEXT: psrlw $1, %xmm0
-; GFNISSE-NEXT: movdqa {{.*#+}} xmm2 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127]
-; GFNISSE-NEXT: pand %xmm2, %xmm0
-; GFNISSE-NEXT: psrlw $1, %xmm1
-; GFNISSE-NEXT: pand %xmm2, %xmm1
+; GFNISSE-NEXT: movdqa {{.*#+}} xmm2 = [145249953336295424,145249953336295424]
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm2, %xmm0
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm2, %xmm1
; GFNISSE-NEXT: retq
;
; GFNIAVX1-LABEL: splatconstant_lshr_v32i8:
; GFNIAVX1: # %bb.0:
-; GFNIAVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
-; GFNIAVX1-NEXT: vpsrlw $1, %xmm1, %xmm1
-; GFNIAVX1-NEXT: vbroadcastss {{.*#+}} xmm2 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127]
-; GFNIAVX1-NEXT: vpand %xmm2, %xmm1, %xmm1
-; GFNIAVX1-NEXT: vpsrlw $1, %xmm0, %xmm0
-; GFNIAVX1-NEXT: vpand %xmm2, %xmm0, %xmm0
-; GFNIAVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; GFNIAVX1-NEXT: retq
;
; GFNIAVX2-LABEL: splatconstant_lshr_v32i8:
; GFNIAVX2: # %bb.0:
-; GFNIAVX2-NEXT: vpsrlw $1, %ymm0, %ymm0
-; GFNIAVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
+; GFNIAVX2-NEXT: vpbroadcastq {{.*#+}} ymm1 = [145249953336295424,145249953336295424,145249953336295424,145249953336295424]
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, %ymm1, %ymm0, %ymm0
; GFNIAVX2-NEXT: retq
;
; GFNIAVX512-LABEL: splatconstant_lshr_v32i8:
; GFNIAVX512: # %bb.0:
-; GFNIAVX512-NEXT: vpsrlw $1, %ymm0, %ymm0
-; GFNIAVX512-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %ymm0
+; GFNIAVX512-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %ymm0
; GFNIAVX512-NEXT: retq
%shift = lshr <32 x i8> %a, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
ret <32 x i8> %shift
@@ -1611,58 +1529,26 @@ define <32 x i8> @splatconstant_lshr_v32i8(<32 x i8> %a) nounwind {
define <32 x i8> @splatconstant_ashr_v32i8(<32 x i8> %a) nounwind {
; GFNISSE-LABEL: splatconstant_ashr_v32i8:
; GFNISSE: # %bb.0:
-; GFNISSE-NEXT: psrlw $2, %xmm0
-; GFNISSE-NEXT: movdqa {{.*#+}} xmm2 = [63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63]
-; GFNISSE-NEXT: pand %xmm2, %xmm0
-; GFNISSE-NEXT: movdqa {{.*#+}} xmm3 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]
-; GFNISSE-NEXT: pxor %xmm3, %xmm0
-; GFNISSE-NEXT: psubb %xmm3, %xmm0
-; GFNISSE-NEXT: psrlw $2, %xmm1
-; GFNISSE-NEXT: pand %xmm2, %xmm1
-; GFNISSE-NEXT: pxor %xmm3, %xmm1
-; GFNISSE-NEXT: psubb %xmm3, %xmm1
+; GFNISSE-NEXT: movdqa {{.*#+}} xmm2 = [290499906672558208,290499906672558208]
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm2, %xmm0
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm2, %xmm1
; GFNISSE-NEXT: retq
;
; GFNIAVX1-LABEL: splatconstant_ashr_v32i8:
; GFNIAVX1: # %bb.0:
-; GFNIAVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
-; GFNIAVX1-NEXT: vpsrlw $2, %xmm1, %xmm1
-; GFNIAVX1-NEXT: vbroadcastss {{.*#+}} xmm2 = [63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63]
-; GFNIAVX1-NEXT: vpand %xmm2, %xmm1, %xmm1
-; GFNIAVX1-NEXT: vbroadcastss {{.*#+}} xmm3 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]
-; GFNIAVX1-NEXT: vpxor %xmm3, %xmm1, %xmm1
-; GFNIAVX1-NEXT: vpsubb %xmm3, %xmm1, %xmm1
-; GFNIAVX1-NEXT: vpsrlw $2, %xmm0, %xmm0
-; GFNIAVX1-NEXT: vpand %xmm2, %xmm0, %xmm0
-; GFNIAVX1-NEXT: vpxor %xmm3, %xmm0, %xmm0
-; GFNIAVX1-NEXT: vpsubb %xmm3, %xmm0, %xmm0
-; GFNIAVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; GFNIAVX1-NEXT: retq
;
; GFNIAVX2-LABEL: splatconstant_ashr_v32i8:
; GFNIAVX2: # %bb.0:
-; GFNIAVX2-NEXT: vpsrlw $2, %ymm0, %ymm0
-; GFNIAVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
-; GFNIAVX2-NEXT: vpbroadcastb {{.*#+}} ymm1 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]
-; GFNIAVX2-NEXT: vpxor %ymm1, %ymm0, %ymm0
-; GFNIAVX2-NEXT: vpsubb %ymm1, %ymm0, %ymm0
+; GFNIAVX2-NEXT: vpbroadcastq {{.*#+}} ymm1 = [290499906672558208,290499906672558208,290499906672558208,290499906672558208]
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, %ymm1, %ymm0, %ymm0
; GFNIAVX2-NEXT: retq
;
-; GFNIAVX512VL-LABEL: splatconstant_ashr_v32i8:
-; GFNIAVX512VL: # %bb.0:
-; GFNIAVX512VL-NEXT: vpsrlw $2, %ymm0, %ymm0
-; GFNIAVX512VL-NEXT: vpbroadcastd {{.*#+}} ymm1 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]
-; GFNIAVX512VL-NEXT: vpternlogd $108, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm1, %ymm0
-; GFNIAVX512VL-NEXT: vpsubb %ymm1, %ymm0, %ymm0
-; GFNIAVX512VL-NEXT: retq
-;
-; GFNIAVX512BW-LABEL: splatconstant_ashr_v32i8:
-; GFNIAVX512BW: # %bb.0:
-; GFNIAVX512BW-NEXT: vpsrlw $2, %ymm0, %ymm0
-; GFNIAVX512BW-NEXT: vpbroadcastb {{.*#+}} ymm1 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]
-; GFNIAVX512BW-NEXT: vpternlogd $108, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm1, %ymm0
-; GFNIAVX512BW-NEXT: vpsubb %ymm1, %ymm0, %ymm0
-; GFNIAVX512BW-NEXT: retq
+; GFNIAVX512-LABEL: splatconstant_ashr_v32i8:
+; GFNIAVX512: # %bb.0:
+; GFNIAVX512-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %ymm0
+; GFNIAVX512-NEXT: retq
%shift = ashr <32 x i8> %a, <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2>
ret <32 x i8> %shift
}
@@ -1676,17 +1562,15 @@ define <64 x i8> @var_shl_v64i8(<64 x i8> %a, <64 x i8> %b) nounwind {
; GFNISSE: # %bb.0:
; GFNISSE-NEXT: movdqa %xmm4, %xmm8
; GFNISSE-NEXT: movdqa %xmm0, %xmm4
+; GFNISSE-NEXT: pmovsxdq {{.*#+}} xmm9 = [16909320,16909320]
; GFNISSE-NEXT: movdqa %xmm0, %xmm10
-; GFNISSE-NEXT: psllw $4, %xmm10
-; GFNISSE-NEXT: movdqa {{.*#+}} xmm9 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240]
-; GFNISSE-NEXT: pand %xmm9, %xmm10
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm9, %xmm10
; GFNISSE-NEXT: psllw $5, %xmm8
; GFNISSE-NEXT: movdqa %xmm8, %xmm0
; GFNISSE-NEXT: pblendvb %xmm0, %xmm10, %xmm4
+; GFNISSE-NEXT: movdqa {{.*#+}} xmm10 = [1108169199648,1108169199648]
; GFNISSE-NEXT: movdqa %xmm4, %xmm11
-; GFNISSE-NEXT: psllw $2, %xmm11
-; GFNISSE-NEXT: movdqa {{.*#+}} xmm10 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252]
-; GFNISSE-NEXT: pand %xmm10, %xmm11
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm10, %xmm11
; GFNISSE-NEXT: paddb %xmm8, %xmm8
; GFNISSE-NEXT: movdqa %xmm8, %xmm0
; GFNISSE-NEXT: pblendvb %xmm0, %xmm11, %xmm4
@@ -1696,14 +1580,12 @@ define <64 x i8> @var_shl_v64i8(<64 x i8> %a, <64 x i8> %b) nounwind {
; GFNISSE-NEXT: movdqa %xmm8, %xmm0
; GFNISSE-NEXT: pblendvb %xmm0, %xmm11, %xmm4
; GFNISSE-NEXT: movdqa %xmm1, %xmm8
-; GFNISSE-NEXT: psllw $4, %xmm8
-; GFNISSE-NEXT: pand %xmm9, %xmm8
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm9, %xmm8
; GFNISSE-NEXT: psllw $5, %xmm5
; GFNISSE-NEXT: movdqa %xmm5, %xmm0
; GFNISSE-NEXT: pblendvb %xmm0, %xmm8, %xmm1
; GFNISSE-NEXT: movdqa %xmm1, %xmm8
-; GFNISSE-NEXT: psllw $2, %xmm8
-; GFNISSE-NEXT: pand %xmm10, %xmm8
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm10, %xmm8
; GFNISSE-NEXT: paddb %xmm5, %xmm5
; GFNISSE-NEXT: movdqa %xmm5, %xmm0
; GFNISSE-NEXT: pblendvb %xmm0, %xmm8, %xmm1
@@ -1713,14 +1595,12 @@ define <64 x i8> @var_shl_v64i8(<64 x i8> %a, <64 x i8> %b) nounwind {
; GFNISSE-NEXT: movdqa %xmm5, %xmm0
; GFNISSE-NEXT: pblendvb %xmm0, %xmm8, %xmm1
; GFNISSE-NEXT: movdqa %xmm2, %xmm5
-; GFNISSE-NEXT: psllw $4, %xmm5
-; GFNISSE-NEXT: pand %xmm9, %xmm5
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm9, %xmm5
; GFNISSE-NEXT: psllw $5, %xmm6
; GFNISSE-NEXT: movdqa %xmm6, %xmm0
; GFNISSE-NEXT: pblendvb %xmm0, %xmm5, %xmm2
; GFNISSE-NEXT: movdqa %xmm2, %xmm5
-; GFNISSE-NEXT: psllw $2, %xmm5
-; GFNISSE-NEXT: pand %xmm10, %xmm5
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm10, %xmm5
; GFNISSE-NEXT: paddb %xmm6, %xmm6
; GFNISSE-NEXT: movdqa %xmm6, %xmm0
; GFNISSE-NEXT: pblendvb %xmm0, %xmm5, %xmm2
@@ -1730,14 +1610,12 @@ define <64 x i8> @var_shl_v64i8(<64 x i8> %a, <64 x i8> %b) nounwind {
; GFNISSE-NEXT: movdqa %xmm6, %xmm0
; GFNISSE-NEXT: pblendvb %xmm0, %xmm5, %xmm2
; GFNISSE-NEXT: movdqa %xmm3, %xmm5
-; GFNISSE-NEXT: psllw $4, %xmm5
-; GFNISSE-NEXT: pand %xmm9, %xmm5
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm9, %xmm5
; GFNISSE-NEXT: psllw $5, %xmm7
; GFNISSE-NEXT: movdqa %xmm7, %xmm0
; GFNISSE-NEXT: pblendvb %xmm0, %xmm5, %xmm3
; GFNISSE-NEXT: movdqa %xmm3, %xmm5
-; GFNISSE-NEXT: psllw $2, %xmm5
-; GFNISSE-NEXT: pand %xmm10, %xmm5
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm10, %xmm5
; GFNISSE-NEXT: paddb %xmm7, %xmm7
; GFNISSE-NEXT: movdqa %xmm7, %xmm0
; GFNISSE-NEXT: pblendvb %xmm0, %xmm5, %xmm3
@@ -1752,26 +1630,24 @@ define <64 x i8> @var_shl_v64i8(<64 x i8> %a, <64 x i8> %b) nounwind {
; GFNIAVX1-LABEL: var_shl_v64i8:
; GFNIAVX1: # %bb.0:
; GFNIAVX1-NEXT: vextractf128 $1, %ymm0, %xmm5
-; GFNIAVX1-NEXT: vpsllw $4, %xmm5, %xmm6
-; GFNIAVX1-NEXT: vbroadcastss {{.*#+}} xmm4 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240]
-; GFNIAVX1-NEXT: vpand %xmm4, %xmm6, %xmm6
+; GFNIAVX1-NEXT: vmovddup {{.*#+}} xmm4 = [16909320,16909320]
+; GFNIAVX1-NEXT: # xmm4 = mem[0,0]
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm4, %xmm5, %xmm6
; GFNIAVX1-NEXT: vextractf128 $1, %ymm2, %xmm7
; GFNIAVX1-NEXT: vpsllw $5, %xmm7, %xmm7
; GFNIAVX1-NEXT: vpblendvb %xmm7, %xmm6, %xmm5, %xmm6
-; GFNIAVX1-NEXT: vpsllw $2, %xmm6, %xmm8
-; GFNIAVX1-NEXT: vbroadcastss {{.*#+}} xmm5 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252]
-; GFNIAVX1-NEXT: vpand %xmm5, %xmm8, %xmm8
+; GFNIAVX1-NEXT: vmovddup {{.*#+}} xmm5 = [1108169199648,1108169199648]
+; GFNIAVX1-NEXT: # xmm5 = mem[0,0]
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm5, %xmm6, %xmm8
; GFNIAVX1-NEXT: vpaddb %xmm7, %xmm7, %xmm7
; GFNIAVX1-NEXT: vpblendvb %xmm7, %xmm8, %xmm6, %xmm6
; GFNIAVX1-NEXT: vpaddb %xmm6, %xmm6, %xmm8
; GFNIAVX1-NEXT: vpaddb %xmm7, %xmm7, %xmm7
; GFNIAVX1-NEXT: vpblendvb %xmm7, %xmm8, %xmm6, %xmm6
-; GFNIAVX1-NEXT: vpsllw $4, %xmm0, %xmm7
-; GFNIAVX1-NEXT: vpand %xmm4, %xmm7, %xmm7
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm4, %xmm0, %xmm7
; GFNIAVX1-NEXT: vpsllw $5, %xmm2, %xmm2
; GFNIAVX1-NEXT: vpblendvb %xmm2, %xmm7, %xmm0, %xmm0
-; GFNIAVX1-NEXT: vpsllw $2, %xmm0, %xmm7
-; GFNIAVX1-NEXT: vpand %xmm5, %xmm7, %xmm7
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm5, %xmm0, %xmm7
; GFNIAVX1-NEXT: vpaddb %xmm2, %xmm2, %xmm2
; GFNIAVX1-NEXT: vpblendvb %xmm2, %xmm7, %xmm0, %xmm0
; GFNIAVX1-NEXT: vpaddb %xmm0, %xmm0, %xmm7
@@ -1779,24 +1655,20 @@ define <64 x i8> @var_shl_v64i8(<64 x i8> %a, <64 x i8> %b) nounwind {
; GFNIAVX1-NEXT: vpblendvb %xmm2, %xmm7, %xmm0, %xmm0
; GFNIAVX1-NEXT: vinsertf128 $1, %xmm6, %ymm0, %ymm0
; GFNIAVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
-; GFNIAVX1-NEXT: vpsllw $4, %xmm2, %xmm6
-; GFNIAVX1-NEXT: vpand %xmm4, %xmm6, %xmm6
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm4, %xmm2, %xmm6
; GFNIAVX1-NEXT: vextractf128 $1, %ymm3, %xmm7
; GFNIAVX1-NEXT: vpsllw $5, %xmm7, %xmm7
; GFNIAVX1-NEXT: vpblendvb %xmm7, %xmm6, %xmm2, %xmm2
-; GFNIAVX1-NEXT: vpsllw $2, %xmm2, %xmm6
-; GFNIAVX1-NEXT: vpand %xmm5, %xmm6, %xmm6
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm5, %xmm2, %xmm6
; GFNIAVX1-NEXT: vpaddb %xmm7, %xmm7, %xmm7
; GFNIAVX1-NEXT: vpblendvb %xmm7, %xmm6, %xmm2, %xmm2
; GFNIAVX1-NEXT: vpaddb %xmm2, %xmm2, %xmm6
; GFNIAVX1-NEXT: vpaddb %xmm7, %xmm7, %xmm7
; GFNIAVX1-NEXT: vpblendvb %xmm7, %xmm6, %xmm2, %xmm2
-; GFNIAVX1-NEXT: vpsllw $4, %xmm1, %xmm6
-; GFNIAVX1-NEXT: vpand %xmm4, %xmm6, %xmm4
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm4, %xmm1, %xmm4
; GFNIAVX1-NEXT: vpsllw $5, %xmm3, %xmm3
; GFNIAVX1-NEXT: vpblendvb %xmm3, %xmm4, %xmm1, %xmm1
-; GFNIAVX1-NEXT: vpsllw $2, %xmm1, %xmm4
-; GFNIAVX1-NEXT: vpand %xmm5, %xmm4, %xmm4
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm5, %xmm1, %xmm4
; GFNIAVX1-NEXT: vpaddb %xmm3, %xmm3, %xmm3
; GFNIAVX1-NEXT: vpblendvb %xmm3, %xmm4, %xmm1, %xmm1
; GFNIAVX1-NEXT: vpaddb %xmm1, %xmm1, %xmm4
@@ -1807,25 +1679,21 @@ define <64 x i8> @var_shl_v64i8(<64 x i8> %a, <64 x i8> %b) nounwind {
;
; GFNIAVX2-LABEL: var_shl_v64i8:
; GFNIAVX2: # %bb.0:
-; GFNIAVX2-NEXT: vpsllw $4, %ymm0, %ymm4
-; GFNIAVX2-NEXT: vpbroadcastb {{.*#+}} ymm5 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240]
-; GFNIAVX2-NEXT: vpand %ymm5, %ymm4, %ymm4
+; GFNIAVX2-NEXT: vpbroadcastq {{.*#+}} ymm4 = [16909320,16909320,16909320,16909320]
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, %ymm4, %ymm0, %ymm5
; GFNIAVX2-NEXT: vpsllw $5, %ymm2, %ymm2
-; GFNIAVX2-NEXT: vpblendvb %ymm2, %ymm4, %ymm0, %ymm0
-; GFNIAVX2-NEXT: vpsllw $2, %ymm0, %ymm4
-; GFNIAVX2-NEXT: vpbroadcastb {{.*#+}} ymm6 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252]
-; GFNIAVX2-NEXT: vpand %ymm6, %ymm4, %ymm4
+; GFNIAVX2-NEXT: vpblendvb %ymm2, %ymm5, %ymm0, %ymm0
+; GFNIAVX2-NEXT: vpbroadcastq {{.*#+}} ymm5 = [1108169199648,1108169199648,1108169199648,1108169199648]
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, %ymm5, %ymm0, %ymm6
; GFNIAVX2-NEXT: vpaddb %ymm2, %ymm2, %ymm2
-; GFNIAVX2-NEXT: vpblendvb %ymm2, %ymm4, %ymm0, %ymm0
-; GFNIAVX2-NEXT: vpaddb %ymm0, %ymm0, %ymm4
+; GFNIAVX2-NEXT: vpblendvb %ymm2, %ymm6, %ymm0, %ymm0
+; GFNIAVX2-NEXT: vpaddb %ymm0, %ymm0, %ymm6
; GFNIAVX2-NEXT: vpaddb %ymm2, %ymm2, %ymm2
-; GFNIAVX2-NEXT: vpblendvb %ymm2, %ymm4, %ymm0, %ymm0
-; GFNIAVX2-NEXT: vpsllw $4, %ymm1, %ymm2
-; GFNIAVX2-NEXT: vpand %ymm5, %ymm2, %ymm2
+; GFNIAVX2-NEXT: vpblendvb %ymm2, %ymm6, %ymm0, %ymm0
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, %ymm4, %ymm1, %ymm2
; GFNIAVX2-NEXT: vpsllw $5, %ymm3, %ymm3
; GFNIAVX2-NEXT: vpblendvb %ymm3, %ymm2, %ymm1, %ymm1
-; GFNIAVX2-NEXT: vpsllw $2, %ymm1, %ymm2
-; GFNIAVX2-NEXT: vpand %ymm6, %ymm2, %ymm2
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, %ymm5, %ymm1, %ymm2
; GFNIAVX2-NEXT: vpaddb %ymm3, %ymm3, %ymm3
; GFNIAVX2-NEXT: vpblendvb %ymm3, %ymm2, %ymm1, %ymm1
; GFNIAVX2-NEXT: vpaddb %ymm1, %ymm1, %ymm2
@@ -1836,26 +1704,22 @@ define <64 x i8> @var_shl_v64i8(<64 x i8> %a, <64 x i8> %b) nounwind {
; GFNIAVX512VL-LABEL: var_shl_v64i8:
; GFNIAVX512VL: # %bb.0:
; GFNIAVX512VL-NEXT: vextracti64x4 $1, %zmm0, %ymm2
-; GFNIAVX512VL-NEXT: vpsllw $4, %ymm2, %ymm3
-; GFNIAVX512VL-NEXT: vpbroadcastd {{.*#+}} ymm4 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240]
-; GFNIAVX512VL-NEXT: vpand %ymm4, %ymm3, %ymm3
+; GFNIAVX512VL-NEXT: vpbroadcastq {{.*#+}} ymm3 = [16909320,16909320,16909320,16909320]
+; GFNIAVX512VL-NEXT: vgf2p8affineqb $0, %ymm3, %ymm2, %ymm4
; GFNIAVX512VL-NEXT: vextracti64x4 $1, %zmm1, %ymm5
; GFNIAVX512VL-NEXT: vpsllw $5, %ymm5, %ymm5
-; GFNIAVX512VL-NEXT: vpblendvb %ymm5, %ymm3, %ymm2, %ymm2
-; GFNIAVX512VL-NEXT: vpsllw $2, %ymm2, %ymm3
-; GFNIAVX512VL-NEXT: vpbroadcastd {{.*#+}} ymm6 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252]
-; GFNIAVX512VL-NEXT: vpand %ymm6, %ymm3, %ymm3
+; GFNIAVX512VL-NEXT: vpblendvb %ymm5, %ymm4, %ymm2, %ymm2
+; GFNIAVX512VL-NEXT: vpbroadcastq {{.*#+}} ymm4 = [1108169199648,1108169199648,1108169199648,1108169199648]
+; GFNIAVX512VL-NEXT: vgf2p8affineqb $0, %ymm4, %ymm2, %ymm6
; GFNIAVX512VL-NEXT: vpaddb %ymm5, %ymm5, %ymm5
-; GFNIAVX512VL-NEXT: vpblendvb %ymm5, %ymm3, %ymm2, %ymm2
-; GFNIAVX512VL-NEXT: vpaddb %ymm2, %ymm2, %ymm3
+; GFNIAVX512VL-NEXT: vpblendvb %ymm5, %ymm6, %ymm2, %ymm2
+; GFNIAVX512VL-NEXT: vpaddb %ymm2, %ymm2, %ymm6
; GFNIAVX512VL-NEXT: vpaddb %ymm5, %ymm5, %ymm5
-; GFNIAVX512VL-NEXT: vpblendvb %ymm5, %ymm3, %ymm2, %ymm2
-; GFNIAVX512VL-NEXT: vpsllw $4, %ymm0, %ymm3
-; GFNIAVX512VL-NEXT: vpand %ymm4, %ymm3, %ymm3
+; GFNIAVX512VL-NEXT: vpblendvb %ymm5, %ymm6, %ymm2, %ymm2
+; GFNIAVX512VL-NEXT: vgf2p8affineqb $0, %ymm3, %ymm0, %ymm3
; GFNIAVX512VL-NEXT: vpsllw $5, %ymm1, %ymm1
; GFNIAVX512VL-NEXT: vpblendvb %ymm1, %ymm3, %ymm0, %ymm0
-; GFNIAVX512VL-NEXT: vpsllw $2, %ymm0, %ymm3
-; GFNIAVX512VL-NEXT: vpand %ymm6, %ymm3, %ymm3
+; GFNIAVX512VL-NEXT: vgf2p8affineqb $0, %ymm4, %ymm0, %ymm3
; GFNIAVX512VL-NEXT: vpaddb %ymm1, %ymm1, %ymm1
; GFNIAVX512VL-NEXT: vpblendvb %ymm1, %ymm3, %ymm0, %ymm0
; GFNIAVX512VL-NEXT: vpaddb %ymm0, %ymm0, %ymm3
@@ -1866,16 +1730,12 @@ define <64 x i8> @var_shl_v64i8(<64 x i8> %a, <64 x i8> %b) nounwind {
;
; GFNIAVX512BW-LABEL: var_shl_v64i8:
; GFNIAVX512BW: # %bb.0:
-; GFNIAVX512BW-NEXT: vpsllw $4, %zmm0, %zmm2
-; GFNIAVX512BW-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm2, %zmm2
; GFNIAVX512BW-NEXT: vpsllw $5, %zmm1, %zmm1
; GFNIAVX512BW-NEXT: vpmovb2m %zmm1, %k1
-; GFNIAVX512BW-NEXT: vmovdqu8 %zmm2, %zmm0 {%k1}
-; GFNIAVX512BW-NEXT: vpsllw $2, %zmm0, %zmm2
-; GFNIAVX512BW-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm2, %zmm2
+; GFNIAVX512BW-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0 {%k1}
; GFNIAVX512BW-NEXT: vpaddb %zmm1, %zmm1, %zmm1
; GFNIAVX512BW-NEXT: vpmovb2m %zmm1, %k1
-; GFNIAVX512BW-NEXT: vmovdqu8 %zmm2, %zmm0 {%k1}
+; GFNIAVX512BW-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0 {%k1}
; GFNIAVX512BW-NEXT: vpaddb %zmm1, %zmm1, %zmm1
; GFNIAVX512BW-NEXT: vpmovb2m %zmm1, %k1
; GFNIAVX512BW-NEXT: vpaddb %zmm0, %zmm0, %zmm0 {%k1}
@@ -1889,78 +1749,66 @@ define <64 x i8> @var_lshr_v64i8(<64 x i8> %a, <64 x i8> %b) nounwind {
; GFNISSE: # %bb.0:
; GFNISSE-NEXT: movdqa %xmm4, %xmm8
; GFNISSE-NEXT: movdqa %xmm0, %xmm4
+; GFNISSE-NEXT: movdqa {{.*#+}} xmm9 = [1161999622361579520,1161999622361579520]
; GFNISSE-NEXT: movdqa %xmm0, %xmm10
-; GFNISSE-NEXT: psrlw $4, %xmm10
-; GFNISSE-NEXT: movdqa {{.*#+}} xmm9 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
-; GFNISSE-NEXT: pand %xmm9, %xmm10
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm9, %xmm10
; GFNISSE-NEXT: psllw $5, %xmm8
; GFNISSE-NEXT: movdqa %xmm8, %xmm0
; GFNISSE-NEXT: pblendvb %xmm0, %xmm10, %xmm4
+; GFNISSE-NEXT: movdqa {{.*#+}} xmm10 = [290499906672525312,290499906672525312]
; GFNISSE-NEXT: movdqa %xmm4, %xmm11
-; GFNISSE-NEXT: psrlw $2, %xmm11
-; GFNISSE-NEXT: movdqa {{.*#+}} xmm10 = [63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63]
-; GFNISSE-NEXT: pand %xmm10, %xmm11
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm10, %xmm11
; GFNISSE-NEXT: paddb %xmm8, %xmm8
; GFNISSE-NEXT: movdqa %xmm8, %xmm0
; GFNISSE-NEXT: pblendvb %xmm0, %xmm11, %xmm4
+; GFNISSE-NEXT: movdqa {{.*#+}} xmm11 = [145249953336295424,145249953336295424]
; GFNISSE-NEXT: movdqa %xmm4, %xmm12
-; GFNISSE-NEXT: psrlw $1, %xmm12
-; GFNISSE-NEXT: movdqa {{.*#+}} xmm11 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127]
-; GFNISSE-NEXT: pand %xmm11, %xmm12
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm11, %xmm12
; GFNISSE-NEXT: paddb %xmm8, %xmm8
; GFNISSE-NEXT: movdqa %xmm8, %xmm0
; GFNISSE-NEXT: pblendvb %xmm0, %xmm12, %xmm4
; GFNISSE-NEXT: movdqa %xmm1, %xmm8
-; GFNISSE-NEXT: psrlw $4, %xmm8
-; GFNISSE-NEXT: pand %xmm9, %xmm8
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm9, %xmm8
; GFNISSE-NEXT: psllw $5, %xmm5
; GFNISSE-NEXT: movdqa %xmm5, %xmm0
; GFNISSE-NEXT: pblendvb %xmm0, %xmm8, %xmm1
; GFNISSE-NEXT: movdqa %xmm1, %xmm8
-; GFNISSE-NEXT: psrlw $2, %xmm8
-; GFNISSE-NEXT: pand %xmm10, %xmm8
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm10, %xmm8
; GFNISSE-NEXT: paddb %xmm5, %xmm5
; GFNISSE-NEXT: movdqa %xmm5, %xmm0
; GFNISSE-NEXT: pblendvb %xmm0, %xmm8, %xmm1
; GFNISSE-NEXT: movdqa %xmm1, %xmm8
-; GFNISSE-NEXT: psrlw $1, %xmm8
-; GFNISSE-NEXT: pand %xmm11, %xmm8
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm11, %xmm8
; GFNISSE-NEXT: paddb %xmm5, %xmm5
; GFNISSE-NEXT: movdqa %xmm5, %xmm0
; GFNISSE-NEXT: pblendvb %xmm0, %xmm8, %xmm1
; GFNISSE-NEXT: movdqa %xmm2, %xmm5
-; GFNISSE-NEXT: psrlw $4, %xmm5
-; GFNISSE-NEXT: pand %xmm9, %xmm5
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm9, %xmm5
; GFNISSE-NEXT: psllw $5, %xmm6
; GFNISSE-NEXT: movdqa %xmm6, %xmm0
; GFNISSE-NEXT: pblendvb %xmm0, %xmm5, %xmm2
; GFNISSE-NEXT: movdqa %xmm2, %xmm5
-; GFNISSE-NEXT: psrlw $2, %xmm5
-; GFNISSE-NEXT: pand %xmm10, %xmm5
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm10, %xmm5
; GFNISSE-NEXT: paddb %xmm6, %xmm6
; GFNISSE-NEXT: movdqa %xmm6, %xmm0
; GFNISSE-NEXT: pblendvb %xmm0, %xmm5, %xmm2
; GFNISSE-NEXT: movdqa %xmm2, %xmm5
-; GFNISSE-NEXT: psrlw $1, %xmm5
-; GFNISSE-NEXT: pand %xmm11, %xmm5
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm11, %xmm5
; GFNISSE-NEXT: paddb %xmm6, %xmm6
; GFNISSE-NEXT: movdqa %xmm6, %xmm0
; GFNISSE-NEXT: pblendvb %xmm0, %xmm5, %xmm2
; GFNISSE-NEXT: movdqa %xmm3, %xmm5
-; GFNISSE-NEXT: psrlw $4, %xmm5
-; GFNISSE-NEXT: pand %xmm9, %xmm5
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm9, %xmm5
; GFNISSE-NEXT: psllw $5, %xmm7
; GFNISSE-NEXT: movdqa %xmm7, %xmm0
; GFNISSE-NEXT: pblendvb %xmm0, %xmm5, %xmm3
; GFNISSE-NEXT: movdqa %xmm3, %xmm5
-; GFNISSE-NEXT: psrlw $2, %xmm5
-; GFNISSE-NEXT: pand %xmm10, %xmm5
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm10, %xmm5
; GFNISSE-NEXT: paddb %xmm7, %xmm7
; GFNISSE-NEXT: movdqa %xmm7, %xmm0
; GFNISSE-NEXT: pblendvb %xmm0, %xmm5, %xmm3
; GFNISSE-NEXT: movdqa %xmm3, %xmm5
-; GFNISSE-NEXT: psrlw $1, %xmm5
-; GFNISSE-NEXT: pand %xmm11, %xmm5
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm11, %xmm5
; GFNISSE-NEXT: paddb %xmm7, %xmm7
; GFNISSE-NEXT: movdqa %xmm7, %xmm0
; GFNISSE-NEXT: pblendvb %xmm0, %xmm5, %xmm3
@@ -1970,59 +1818,50 @@ define <64 x i8> @var_lshr_v64i8(<64 x i8> %a, <64 x i8> %b) nounwind {
; GFNIAVX1-LABEL: var_lshr_v64i8:
; GFNIAVX1: # %bb.0:
; GFNIAVX1-NEXT: vextractf128 $1, %ymm0, %xmm5
-; GFNIAVX1-NEXT: vpsrlw $4, %xmm5, %xmm6
-; GFNIAVX1-NEXT: vbroadcastss {{.*#+}} xmm4 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
-; GFNIAVX1-NEXT: vpand %xmm4, %xmm6, %xmm6
+; GFNIAVX1-NEXT: vmovddup {{.*#+}} xmm4 = [1161999622361579520,1161999622361579520]
+; GFNIAVX1-NEXT: # xmm4 = mem[0,0]
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm4, %xmm5, %xmm6
; GFNIAVX1-NEXT: vextractf128 $1, %ymm2, %xmm7
; GFNIAVX1-NEXT: vpsllw $5, %xmm7, %xmm7
; GFNIAVX1-NEXT: vpblendvb %xmm7, %xmm6, %xmm5, %xmm6
-; GFNIAVX1-NEXT: vpsrlw $2, %xmm6, %xmm8
-; GFNIAVX1-NEXT: vbroadcastss {{.*#+}} xmm5 = [63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63]
-; GFNIAVX1-NEXT: vpand %xmm5, %xmm8, %xmm8
+; GFNIAVX1-NEXT: vmovddup {{.*#+}} xmm5 = [290499906672525312,290499906672525312]
+; GFNIAVX1-NEXT: # xmm5 = mem[0,0]
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm5, %xmm6, %xmm8
; GFNIAVX1-NEXT: vpaddb %xmm7, %xmm7, %xmm7
; GFNIAVX1-NEXT: vpblendvb %xmm7, %xmm8, %xmm6, %xmm8
-; GFNIAVX1-NEXT: vpsrlw $1, %xmm8, %xmm9
-; GFNIAVX1-NEXT: vbroadcastss {{.*#+}} xmm6 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127]
-; GFNIAVX1-NEXT: vpand %xmm6, %xmm9, %xmm9
+; GFNIAVX1-NEXT: vmovddup {{.*#+}} xmm6 = [145249953336295424,145249953336295424]
+; GFNIAVX1-NEXT: # xmm6 = mem[0,0]
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm6, %xmm8, %xmm9
; GFNIAVX1-NEXT: vpaddb %xmm7, %xmm7, %xmm7
; GFNIAVX1-NEXT: vpblendvb %xmm7, %xmm9, %xmm8, %xmm7
-; GFNIAVX1-NEXT: vpsrlw $4, %xmm0, %xmm8
-; GFNIAVX1-NEXT: vpand %xmm4, %xmm8, %xmm8
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm4, %xmm0, %xmm8
; GFNIAVX1-NEXT: vpsllw $5, %xmm2, %xmm2
; GFNIAVX1-NEXT: vpblendvb %xmm2, %xmm8, %xmm0, %xmm0
-; GFNIAVX1-NEXT: vpsrlw $2, %xmm0, %xmm8
-; GFNIAVX1-NEXT: vpand %xmm5, %xmm8, %xmm8
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm5, %xmm0, %xmm8
; GFNIAVX1-NEXT: vpaddb %xmm2, %xmm2, %xmm2
; GFNIAVX1-NEXT: vpblendvb %xmm2, %xmm8, %xmm0, %xmm0
-; GFNIAVX1-NEXT: vpsrlw $1, %xmm0, %xmm8
-; GFNIAVX1-NEXT: vpand %xmm6, %xmm8, %xmm8
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm6, %xmm0, %xmm8
; GFNIAVX1-NEXT: vpaddb %xmm2, %xmm2, %xmm2
; GFNIAVX1-NEXT: vpblendvb %xmm2, %xmm8, %xmm0, %xmm0
; GFNIAVX1-NEXT: vinsertf128 $1, %xmm7, %ymm0, %ymm0
; GFNIAVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
-; GFNIAVX1-NEXT: vpsrlw $4, %xmm2, %xmm7
-; GFNIAVX1-NEXT: vpand %xmm4, %xmm7, %xmm7
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm4, %xmm2, %xmm7
; GFNIAVX1-NEXT: vextractf128 $1, %ymm3, %xmm8
; GFNIAVX1-NEXT: vpsllw $5, %xmm8, %xmm8
; GFNIAVX1-NEXT: vpblendvb %xmm8, %xmm7, %xmm2, %xmm2
-; GFNIAVX1-NEXT: vpsrlw $2, %xmm2, %xmm7
-; GFNIAVX1-NEXT: vpand %xmm5, %xmm7, %xmm7
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm5, %xmm2, %xmm7
; GFNIAVX1-NEXT: vpaddb %xmm8, %xmm8, %xmm8
; GFNIAVX1-NEXT: vpblendvb %xmm8, %xmm7, %xmm2, %xmm2
-; GFNIAVX1-NEXT: vpsrlw $1, %xmm2, %xmm7
-; GFNIAVX1-NEXT: vpand %xmm6, %xmm7, %xmm7
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm6, %xmm2, %xmm7
; GFNIAVX1-NEXT: vpaddb %xmm8, %xmm8, %xmm8
; GFNIAVX1-NEXT: vpblendvb %xmm8, %xmm7, %xmm2, %xmm2
-; GFNIAVX1-NEXT: vpsrlw $4, %xmm1, %xmm7
-; GFNIAVX1-NEXT: vpand %xmm4, %xmm7, %xmm4
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm4, %xmm1, %xmm4
; GFNIAVX1-NEXT: vpsllw $5, %xmm3, %xmm3
; GFNIAVX1-NEXT: vpblendvb %xmm3, %xmm4, %xmm1, %xmm1
-; GFNIAVX1-NEXT: vpsrlw $2, %xmm1, %xmm4
-; GFNIAVX1-NEXT: vpand %xmm5, %xmm4, %xmm4
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm5, %xmm1, %xmm4
; GFNIAVX1-NEXT: vpaddb %xmm3, %xmm3, %xmm3
; GFNIAVX1-NEXT: vpblendvb %xmm3, %xmm4, %xmm1, %xmm1
-; GFNIAVX1-NEXT: vpsrlw $1, %xmm1, %xmm4
-; GFNIAVX1-NEXT: vpand %xmm6, %xmm4, %xmm4
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm6, %xmm1, %xmm4
; GFNIAVX1-NEXT: vpaddb %xmm3, %xmm3, %xmm3
; GFNIAVX1-NEXT: vpblendvb %xmm3, %xmm4, %xmm1, %xmm1
; GFNIAVX1-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1
@@ -2030,31 +1869,25 @@ define <64 x i8> @var_lshr_v64i8(<64 x i8> %a, <64 x i8> %b) nounwind {
;
; GFNIAVX2-LABEL: var_lshr_v64i8:
; GFNIAVX2: # %bb.0:
-; GFNIAVX2-NEXT: vpsrlw $4, %ymm0, %ymm4
-; GFNIAVX2-NEXT: vpbroadcastb {{.*#+}} ymm5 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
-; GFNIAVX2-NEXT: vpand %ymm5, %ymm4, %ymm4
+; GFNIAVX2-NEXT: vpbroadcastq {{.*#+}} ymm4 = [1161999622361579520,1161999622361579520,1161999622361579520,1161999622361579520]
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, %ymm4, %ymm0, %ymm5
; GFNIAVX2-NEXT: vpsllw $5, %ymm2, %ymm2
-; GFNIAVX2-NEXT: vpblendvb %ymm2, %ymm4, %ymm0, %ymm0
-; GFNIAVX2-NEXT: vpsrlw $2, %ymm0, %ymm4
-; GFNIAVX2-NEXT: vpbroadcastb {{.*#+}} ymm6 = [63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63]
-; GFNIAVX2-NEXT: vpand %ymm6, %ymm4, %ymm4
+; GFNIAVX2-NEXT: vpblendvb %ymm2, %ymm5, %ymm0, %ymm0
+; GFNIAVX2-NEXT: vpbroadcastq {{.*#+}} ymm5 = [290499906672525312,290499906672525312,290499906672525312,290499906672525312]
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, %ymm5, %ymm0, %ymm6
; GFNIAVX2-NEXT: vpaddb %ymm2, %ymm2, %ymm2
-; GFNIAVX2-NEXT: vpblendvb %ymm2, %ymm4, %ymm0, %ymm0
-; GFNIAVX2-NEXT: vpsrlw $1, %ymm0, %ymm4
-; GFNIAVX2-NEXT: vpbroadcastb {{.*#+}} ymm7 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127]
-; GFNIAVX2-NEXT: vpand %ymm7, %ymm4, %ymm4
+; GFNIAVX2-NEXT: vpblendvb %ymm2, %ymm6, %ymm0, %ymm0
+; GFNIAVX2-NEXT: vpbroadcastq {{.*#+}} ymm6 = [145249953336295424,145249953336295424,145249953336295424,145249953336295424]
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, %ymm6, %ymm0, %ymm7
; GFNIAVX2-NEXT: vpaddb %ymm2, %ymm2, %ymm2
-; GFNIAVX2-NEXT: vpblendvb %ymm2, %ymm4, %ymm0, %ymm0
-; GFNIAVX2-NEXT: vpsrlw $4, %ymm1, %ymm2
-; GFNIAVX2-NEXT: vpand %ymm5, %ymm2, %ymm2
+; GFNIAVX2-NEXT: vpblendvb %ymm2, %ymm7, %ymm0, %ymm0
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, %ymm4, %ymm1, %ymm2
; GFNIAVX2-NEXT: vpsllw $5, %ymm3, %ymm3
; GFNIAVX2-NEXT: vpblendvb %ymm3, %ymm2, %ymm1, %ymm1
-; GFNIAVX2-NEXT: vpsrlw $2, %ymm1, %ymm2
-; GFNIAVX2-NEXT: vpand %ymm6, %ymm2, %ymm2
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, %ymm5, %ymm1, %ymm2
; GFNIAVX2-NEXT: vpaddb %ymm3, %ymm3, %ymm3
; GFNIAVX2-NEXT: vpblendvb %ymm3, %ymm2, %ymm1, %ymm1
-; GFNIAVX2-NEXT: vpsrlw $1, %ymm1, %ymm2
-; GFNIAVX2-NEXT: vpand %ymm7, %ymm2, %ymm2
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, %ymm6, %ymm1, %ymm2
; GFNIAVX2-NEXT: vpaddb %ymm3, %ymm3, %ymm3
; GFNIAVX2-NEXT: vpblendvb %ymm3, %ymm2, %ymm1, %ymm1
; GFNIAVX2-NEXT: retq
@@ -2062,32 +1895,26 @@ define <64 x i8> @var_lshr_v64i8(<64 x i8> %a, <64 x i8> %b) nounwind {
; GFNIAVX512VL-LABEL: var_lshr_v64i8:
; GFNIAVX512VL: # %bb.0:
; GFNIAVX512VL-NEXT: vextracti64x4 $1, %zmm0, %ymm2
-; GFNIAVX512VL-NEXT: vpsrlw $4, %ymm2, %ymm3
-; GFNIAVX512VL-NEXT: vpbroadcastd {{.*#+}} ymm4 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
-; GFNIAVX512VL-NEXT: vpand %ymm4, %ymm3, %ymm3
+; GFNIAVX512VL-NEXT: vpbroadcastq {{.*#+}} ymm3 = [1161999622361579520,1161999622361579520,1161999622361579520,1161999622361579520]
+; GFNIAVX512VL-NEXT: vgf2p8affineqb $0, %ymm3, %ymm2, %ymm4
; GFNIAVX512VL-NEXT: vextracti64x4 $1, %zmm1, %ymm5
; GFNIAVX512VL-NEXT: vpsllw $5, %ymm5, %ymm5
-; GFNIAVX512VL-NEXT: vpblendvb %ymm5, %ymm3, %ymm2, %ymm2
-; GFNIAVX512VL-NEXT: vpsrlw $2, %ymm2, %ymm3
-; GFNIAVX512VL-NEXT: vpbroadcastd {{.*#+}} ymm6 = [63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63]
-; GFNIAVX512VL-NEXT: vpand %ymm6, %ymm3, %ymm3
+; GFNIAVX512VL-NEXT: vpblendvb %ymm5, %ymm4, %ymm2, %ymm2
+; GFNIAVX512VL-NEXT: vpbroadcastq {{.*#+}} ymm4 = [290499906672525312,290499906672525312,290499906672525312,290499906672525312]
+; GFNIAVX512VL-NEXT: vgf2p8affineqb $0, %ymm4, %ymm2, %ymm6
; GFNIAVX512VL-NEXT: vpaddb %ymm5, %ymm5, %ymm5
-; GFNIAVX512VL-NEXT: vpblendvb %ymm5, %ymm3, %ymm2, %ymm2
-; GFNIAVX512VL-NEXT: vpsrlw $1, %ymm2, %ymm3
-; GFNIAVX512VL-NEXT: vpbroadcastd {{.*#+}} ymm7 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127]
-; GFNIAVX512VL-NEXT: vpand %ymm7, %ymm3, %ymm3
+; GFNIAVX512VL-NEXT: vpblendvb %ymm5, %ymm6, %ymm2, %ymm2
+; GFNIAVX512VL-NEXT: vpbroadcastq {{.*#+}} ymm6 = [145249953336295424,145249953336295424,145249953336295424,145249953336295424]
+; GFNIAVX512VL-NEXT: vgf2p8affineqb $0, %ymm6, %ymm2, %ymm7
; GFNIAVX512VL-NEXT: vpaddb %ymm5, %ymm5, %ymm5
-; GFNIAVX512VL-NEXT: vpblendvb %ymm5, %ymm3, %ymm2, %ymm2
-; GFNIAVX512VL-NEXT: vpsrlw $4, %ymm0, %ymm3
-; GFNIAVX512VL-NEXT: vpand %ymm4, %ymm3, %ymm3
+; GFNIAVX512VL-NEXT: vpblendvb %ymm5, %ymm7, %ymm2, %ymm2
+; GFNIAVX512VL-NEXT: vgf2p8affineqb $0, %ymm3, %ymm0, %ymm3
; GFNIAVX512VL-NEXT: vpsllw $5, %ymm1, %ymm1
; GFNIAVX512VL-NEXT: vpblendvb %ymm1, %ymm3, %ymm0, %ymm0
-; GFNIAVX512VL-NEXT: vpsrlw $2, %ymm0, %ymm3
-; GFNIAVX512VL-NEXT: vpand %ymm6, %ymm3, %ymm3
+; GFNIAVX512VL-NEXT: vgf2p8affineqb $0, %ymm4, %ymm0, %ymm3
; GFNIAVX512VL-NEXT: vpaddb %ymm1, %ymm1, %ymm1
; GFNIAVX512VL-NEXT: vpblendvb %ymm1, %ymm3, %ymm0, %ymm0
-; GFNIAVX512VL-NEXT: vpsrlw $1, %ymm0, %ymm3
-; GFNIAVX512VL-NEXT: vpand %ymm7, %ymm3, %ymm3
+; GFNIAVX512VL-NEXT: vgf2p8affineqb $0, %ymm6, %ymm0, %ymm3
; GFNIAVX512VL-NEXT: vpaddb %ymm1, %ymm1, %ymm1
; GFNIAVX512VL-NEXT: vpblendvb %ymm1, %ymm3, %ymm0, %ymm0
; GFNIAVX512VL-NEXT: vinserti64x4 $1, %ymm2, %zmm0, %zmm0
@@ -2095,21 +1922,15 @@ define <64 x i8> @var_lshr_v64i8(<64 x i8> %a, <64 x i8> %b) nounwind {
;
; GFNIAVX512BW-LABEL: var_lshr_v64i8:
; GFNIAVX512BW: # %bb.0:
-; GFNIAVX512BW-NEXT: vpsrlw $4, %zmm0, %zmm2
-; GFNIAVX512BW-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm2, %zmm2
; GFNIAVX512BW-NEXT: vpsllw $5, %zmm1, %zmm1
; GFNIAVX512BW-NEXT: vpmovb2m %zmm1, %k1
-; GFNIAVX512BW-NEXT: vmovdqu8 %zmm2, %zmm0 {%k1}
-; GFNIAVX512BW-NEXT: vpsrlw $2, %zmm0, %zmm2
-; GFNIAVX512BW-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm2, %zmm2
+; GFNIAVX512BW-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0 {%k1}
; GFNIAVX512BW-NEXT: vpaddb %zmm1, %zmm1, %zmm1
; GFNIAVX512BW-NEXT: vpmovb2m %zmm1, %k1
-; GFNIAVX512BW-NEXT: vmovdqu8 %zmm2, %zmm0 {%k1}
-; GFNIAVX512BW-NEXT: vpsrlw $1, %zmm0, %zmm2
-; GFNIAVX512BW-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm2, %zmm2
+; GFNIAVX512BW-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0 {%k1}
; GFNIAVX512BW-NEXT: vpaddb %zmm1, %zmm1, %zmm1
; GFNIAVX512BW-NEXT: vpmovb2m %zmm1, %k1
-; GFNIAVX512BW-NEXT: vmovdqu8 %zmm2, %zmm0 {%k1}
+; GFNIAVX512BW-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0 {%k1}
; GFNIAVX512BW-NEXT: retq
%shift = lshr <64 x i8> %a, %b
ret <64 x i8> %shift
@@ -3214,57 +3035,31 @@ define <64 x i8> @constant_ashr_v64i8(<64 x i8> %a) nounwind {
define <64 x i8> @splatconstant_shl_v64i8(<64 x i8> %a) nounwind {
; GFNISSE-LABEL: splatconstant_shl_v64i8:
; GFNISSE: # %bb.0:
-; GFNISSE-NEXT: psllw $5, %xmm0
-; GFNISSE-NEXT: movdqa {{.*#+}} xmm4 = [224,224,224,224,224,224,224,224,224,224,224,224,224,224,224,224]
-; GFNISSE-NEXT: pand %xmm4, %xmm0
-; GFNISSE-NEXT: psllw $5, %xmm1
-; GFNISSE-NEXT: pand %xmm4, %xmm1
-; GFNISSE-NEXT: psllw $5, %xmm2
-; GFNISSE-NEXT: pand %xmm4, %xmm2
-; GFNISSE-NEXT: psllw $5, %xmm3
-; GFNISSE-NEXT: pand %xmm4, %xmm3
+; GFNISSE-NEXT: pmovsxdq {{.*#+}} xmm4 = [66052,66052]
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm4, %xmm0
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm4, %xmm1
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm4, %xmm2
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm4, %xmm3
; GFNISSE-NEXT: retq
;
; GFNIAVX1-LABEL: splatconstant_shl_v64i8:
; GFNIAVX1: # %bb.0:
-; GFNIAVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
-; GFNIAVX1-NEXT: vpsllw $5, %xmm2, %xmm2
-; GFNIAVX1-NEXT: vbroadcastss {{.*#+}} xmm3 = [224,224,224,224,224,224,224,224,224,224,224,224,224,224,224,224]
-; GFNIAVX1-NEXT: vpand %xmm3, %xmm2, %xmm2
-; GFNIAVX1-NEXT: vpsllw $5, %xmm0, %xmm0
-; GFNIAVX1-NEXT: vpand %xmm3, %xmm0, %xmm0
-; GFNIAVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
-; GFNIAVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
-; GFNIAVX1-NEXT: vpsllw $5, %xmm2, %xmm2
-; GFNIAVX1-NEXT: vpand %xmm3, %xmm2, %xmm2
-; GFNIAVX1-NEXT: vpsllw $5, %xmm1, %xmm1
-; GFNIAVX1-NEXT: vpand %xmm3, %xmm1, %xmm1
-; GFNIAVX1-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1
+; GFNIAVX1-NEXT: vbroadcastsd {{.*#+}} ymm2 = [4,2,1,0,0,0,0,0,4,2,1,0,0,0,0,0,4,2,1,0,0,0,0,0,4,2,1,0,0,0,0,0]
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %ymm2, %ymm0, %ymm0
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %ymm2, %ymm1, %ymm1
; GFNIAVX1-NEXT: retq
;
; GFNIAVX2-LABEL: splatconstant_shl_v64i8:
; GFNIAVX2: # %bb.0:
-; GFNIAVX2-NEXT: vpsllw $5, %ymm0, %ymm0
-; GFNIAVX2-NEXT: vpbroadcastb {{.*#+}} ymm2 = [224,224,224,224,224,224,224,224,224,224,224,224,224,224,224,224,224,224,224,224,224,224,224,224,224,224,224,224,224,224,224,224]
-; GFNIAVX2-NEXT: vpand %ymm2, %ymm0, %ymm0
-; GFNIAVX2-NEXT: vpsllw $5, %ymm1, %ymm1
-; GFNIAVX2-NEXT: vpand %ymm2, %ymm1, %ymm1
+; GFNIAVX2-NEXT: vpbroadcastq {{.*#+}} ymm2 = [66052,66052,66052,66052]
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, %ymm2, %ymm0, %ymm0
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, %ymm2, %ymm1, %ymm1
; GFNIAVX2-NEXT: retq
;
-; GFNIAVX512VL-LABEL: splatconstant_shl_v64i8:
-; GFNIAVX512VL: # %bb.0:
-; GFNIAVX512VL-NEXT: vpsllw $5, %ymm0, %ymm1
-; GFNIAVX512VL-NEXT: vextracti64x4 $1, %zmm0, %ymm0
-; GFNIAVX512VL-NEXT: vpsllw $5, %ymm0, %ymm0
-; GFNIAVX512VL-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0
-; GFNIAVX512VL-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm0
-; GFNIAVX512VL-NEXT: retq
-;
-; GFNIAVX512BW-LABEL: splatconstant_shl_v64i8:
-; GFNIAVX512BW: # %bb.0:
-; GFNIAVX512BW-NEXT: vpsllw $5, %zmm0, %zmm0
-; GFNIAVX512BW-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm0
-; GFNIAVX512BW-NEXT: retq
+; GFNIAVX512-LABEL: splatconstant_shl_v64i8:
+; GFNIAVX512: # %bb.0:
+; GFNIAVX512-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0
+; GFNIAVX512-NEXT: retq
%shift = shl <64 x i8> %a, <i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5>
ret <64 x i8> %shift
}
@@ -3272,57 +3067,31 @@ define <64 x i8> @splatconstant_shl_v64i8(<64 x i8> %a) nounwind {
define <64 x i8> @splatconstant_lshr_v64i8(<64 x i8> %a) nounwind {
; GFNISSE-LABEL: splatconstant_lshr_v64i8:
; GFNISSE: # %bb.0:
-; GFNISSE-NEXT: psrlw $7, %xmm0
-; GFNISSE-NEXT: movdqa {{.*#+}} xmm4 = [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1]
-; GFNISSE-NEXT: pand %xmm4, %xmm0
-; GFNISSE-NEXT: psrlw $7, %xmm1
-; GFNISSE-NEXT: pand %xmm4, %xmm1
-; GFNISSE-NEXT: psrlw $7, %xmm2
-; GFNISSE-NEXT: pand %xmm4, %xmm2
-; GFNISSE-NEXT: psrlw $7, %xmm3
-; GFNISSE-NEXT: pand %xmm4, %xmm3
+; GFNISSE-NEXT: movdqa {{.*#+}} xmm4 = [9223372036854775808,9223372036854775808]
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm4, %xmm0
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm4, %xmm1
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm4, %xmm2
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm4, %xmm3
; GFNISSE-NEXT: retq
;
; GFNIAVX1-LABEL: splatconstant_lshr_v64i8:
; GFNIAVX1: # %bb.0:
-; GFNIAVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
-; GFNIAVX1-NEXT: vpsrlw $7, %xmm2, %xmm2
-; GFNIAVX1-NEXT: vbroadcastss {{.*#+}} xmm3 = [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1]
-; GFNIAVX1-NEXT: vpand %xmm3, %xmm2, %xmm2
-; GFNIAVX1-NEXT: vpsrlw $7, %xmm0, %xmm0
-; GFNIAVX1-NEXT: vpand %xmm3, %xmm0, %xmm0
-; GFNIAVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
-; GFNIAVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
-; GFNIAVX1-NEXT: vpsrlw $7, %xmm2, %xmm2
-; GFNIAVX1-NEXT: vpand %xmm3, %xmm2, %xmm2
-; GFNIAVX1-NEXT: vpsrlw $7, %xmm1, %xmm1
-; GFNIAVX1-NEXT: vpand %xmm3, %xmm1, %xmm1
-; GFNIAVX1-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1
+; GFNIAVX1-NEXT: vbroadcastsd {{.*#+}} ymm2 = [0,0,0,0,0,0,0,128,0,0,0,0,0,0,0,128,0,0,0,0,0,0,0,128,0,0,0,0,0,0,0,128]
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %ymm2, %ymm0, %ymm0
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %ymm2, %ymm1, %ymm1
; GFNIAVX1-NEXT: retq
;
; GFNIAVX2-LABEL: splatconstant_lshr_v64i8:
; GFNIAVX2: # %bb.0:
-; GFNIAVX2-NEXT: vpsrlw $7, %ymm0, %ymm0
-; GFNIAVX2-NEXT: vpbroadcastb {{.*#+}} ymm2 = [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1]
-; GFNIAVX2-NEXT: vpand %ymm2, %ymm0, %ymm0
-; GFNIAVX2-NEXT: vpsrlw $7, %ymm1, %ymm1
-; GFNIAVX2-NEXT: vpand %ymm2, %ymm1, %ymm1
+; GFNIAVX2-NEXT: vpbroadcastq {{.*#+}} ymm2 = [9223372036854775808,9223372036854775808,9223372036854775808,9223372036854775808]
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, %ymm2, %ymm0, %ymm0
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, %ymm2, %ymm1, %ymm1
; GFNIAVX2-NEXT: retq
;
-; GFNIAVX512VL-LABEL: splatconstant_lshr_v64i8:
-; GFNIAVX512VL: # %bb.0:
-; GFNIAVX512VL-NEXT: vpsrlw $7, %ymm0, %ymm1
-; GFNIAVX512VL-NEXT: vextracti64x4 $1, %zmm0, %ymm0
-; GFNIAVX512VL-NEXT: vpsrlw $7, %ymm0, %ymm0
-; GFNIAVX512VL-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0
-; GFNIAVX512VL-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm0
-; GFNIAVX512VL-NEXT: retq
-;
-; GFNIAVX512BW-LABEL: splatconstant_lshr_v64i8:
-; GFNIAVX512BW: # %bb.0:
-; GFNIAVX512BW-NEXT: vpsrlw $7, %zmm0, %zmm0
-; GFNIAVX512BW-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm0
-; GFNIAVX512BW-NEXT: retq
+; GFNIAVX512-LABEL: splatconstant_lshr_v64i8:
+; GFNIAVX512: # %bb.0:
+; GFNIAVX512-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0
+; GFNIAVX512-NEXT: retq
%shift = lshr <64 x i8> %a, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
ret <64 x i8> %shift
}
@@ -3330,87 +3099,31 @@ define <64 x i8> @splatconstant_lshr_v64i8(<64 x i8> %a) nounwind {
define <64 x i8> @splatconstant_ashr_v64i8(<64 x i8> %a) nounwind {
; GFNISSE-LABEL: splatconstant_ashr_v64i8:
; GFNISSE: # %bb.0:
-; GFNISSE-NEXT: psrlw $1, %xmm0
-; GFNISSE-NEXT: movdqa {{.*#+}} xmm4 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127]
-; GFNISSE-NEXT: pand %xmm4, %xmm0
-; GFNISSE-NEXT: movdqa {{.*#+}} xmm5 = [64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64]
-; GFNISSE-NEXT: pxor %xmm5, %xmm0
-; GFNISSE-NEXT: psubb %xmm5, %xmm0
-; GFNISSE-NEXT: psrlw $1, %xmm1
-; GFNISSE-NEXT: pand %xmm4, %xmm1
-; GFNISSE-NEXT: pxor %xmm5, %xmm1
-; GFNISSE-NEXT: psubb %xmm5, %xmm1
-; GFNISSE-NEXT: psrlw $1, %xmm2
-; GFNISSE-NEXT: pand %xmm4, %xmm2
-; GFNISSE-NEXT: pxor %xmm5, %xmm2
-; GFNISSE-NEXT: psubb %xmm5, %xmm2
-; GFNISSE-NEXT: psrlw $1, %xmm3
-; GFNISSE-NEXT: pand %xmm4, %xmm3
-; GFNISSE-NEXT: pxor %xmm5, %xmm3
-; GFNISSE-NEXT: psubb %xmm5, %xmm3
+; GFNISSE-NEXT: movdqa {{.*#+}} xmm4 = [145249953336295552,145249953336295552]
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm4, %xmm0
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm4, %xmm1
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm4, %xmm2
+; GFNISSE-NEXT: gf2p8affineqb $0, %xmm4, %xmm3
; GFNISSE-NEXT: retq
;
; GFNIAVX1-LABEL: splatconstant_ashr_v64i8:
; GFNIAVX1: # %bb.0:
-; GFNIAVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
-; GFNIAVX1-NEXT: vpsrlw $1, %xmm2, %xmm2
-; GFNIAVX1-NEXT: vbroadcastss {{.*#+}} xmm3 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127]
-; GFNIAVX1-NEXT: vpand %xmm3, %xmm2, %xmm2
-; GFNIAVX1-NEXT: vbroadcastss {{.*#+}} xmm4 = [64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64]
-; GFNIAVX1-NEXT: vpxor %xmm4, %xmm2, %xmm2
-; GFNIAVX1-NEXT: vpsubb %xmm4, %xmm2, %xmm2
-; GFNIAVX1-NEXT: vpsrlw $1, %xmm0, %xmm0
-; GFNIAVX1-NEXT: vpand %xmm3, %xmm0, %xmm0
-; GFNIAVX1-NEXT: vpxor %xmm4, %xmm0, %xmm0
-; GFNIAVX1-NEXT: vpsubb %xmm4, %xmm0, %xmm0
-; GFNIAVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
-; GFNIAVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
-; GFNIAVX1-NEXT: vpsrlw $1, %xmm2, %xmm2
-; GFNIAVX1-NEXT: vpand %xmm3, %xmm2, %xmm2
-; GFNIAVX1-NEXT: vpxor %xmm4, %xmm2, %xmm2
-; GFNIAVX1-NEXT: vpsubb %xmm4, %xmm2, %xmm2
-; GFNIAVX1-NEXT: vpsrlw $1, %xmm1, %xmm1
-; GFNIAVX1-NEXT: vpand %xmm3, %xmm1, %xmm1
-; GFNIAVX1-NEXT: vpxor %xmm4, %xmm1, %xmm1
-; GFNIAVX1-NEXT: vpsubb %xmm4, %xmm1, %xmm1
-; GFNIAVX1-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1
+; GFNIAVX1-NEXT: vbroadcastsd {{.*#+}} ymm2 = [128,128,64,32,16,8,4,2,128,128,64,32,16,8,4,2,128,128,64,32,16,8,4,2,128,128,64,32,16,8,4,2]
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %ymm2, %ymm0, %ymm0
+; GFNIAVX1-NEXT: vgf2p8affineqb $0, %ymm2, %ymm1, %ymm1
; GFNIAVX1-NEXT: retq
;
; GFNIAVX2-LABEL: splatconstant_ashr_v64i8:
; GFNIAVX2: # %bb.0:
-; GFNIAVX2-NEXT: vpsrlw $1, %ymm0, %ymm0
-; GFNIAVX2-NEXT: vpbroadcastb {{.*#+}} ymm2 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127]
-; GFNIAVX2-NEXT: vpand %ymm2, %ymm0, %ymm0
-; GFNIAVX2-NEXT: vpbroadcastb {{.*#+}} ymm3 = [64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64]
-; GFNIAVX2-NEXT: vpxor %ymm3, %ymm0, %ymm0
-; GFNIAVX2-NEXT: vpsubb %ymm3, %ymm0, %ymm0
-; GFNIAVX2-NEXT: vpsrlw $1, %ymm1, %ymm1
-; GFNIAVX2-NEXT: vpand %ymm2, %ymm1, %ymm1
-; GFNIAVX2-NEXT: vpxor %ymm3, %ymm1, %ymm1
-; GFNIAVX2-NEXT: vpsubb %ymm3, %ymm1, %ymm1
+; GFNIAVX2-NEXT: vpbroadcastq {{.*#+}} ymm2 = [145249953336295552,145249953336295552,145249953336295552,145249953336295552]
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, %ymm2, %ymm0, %ymm0
+; GFNIAVX2-NEXT: vgf2p8affineqb $0, %ymm2, %ymm1, %ymm1
; GFNIAVX2-NEXT: retq
;
-; GFNIAVX512VL-LABEL: splatconstant_ashr_v64i8:
-; GFNIAVX512VL: # %bb.0:
-; GFNIAVX512VL-NEXT: vextracti64x4 $1, %zmm0, %ymm1
-; GFNIAVX512VL-NEXT: vpsrlw $1, %ymm1, %ymm1
-; GFNIAVX512VL-NEXT: vpbroadcastd {{.*#+}} ymm2 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127]
-; GFNIAVX512VL-NEXT: vpbroadcastd {{.*#+}} ymm3 = [64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64]
-; GFNIAVX512VL-NEXT: vpternlogq $108, %ymm2, %ymm3, %ymm1
-; GFNIAVX512VL-NEXT: vpsubb %ymm3, %ymm1, %ymm1
-; GFNIAVX512VL-NEXT: vpsrlw $1, %ymm0, %ymm0
-; GFNIAVX512VL-NEXT: vpternlogq $108, %ymm2, %ymm3, %ymm0
-; GFNIAVX512VL-NEXT: vpsubb %ymm3, %ymm0, %ymm0
-; GFNIAVX512VL-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; GFNIAVX512VL-NEXT: retq
-;
-; GFNIAVX512BW-LABEL: splatconstant_ashr_v64i8:
-; GFNIAVX512BW: # %bb.0:
-; GFNIAVX512BW-NEXT: vpsrlw $1, %zmm0, %zmm0
-; GFNIAVX512BW-NEXT: vpbroadcastb {{.*#+}} zmm1 = [64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64]
-; GFNIAVX512BW-NEXT: vpternlogd $108, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm1, %zmm0
-; GFNIAVX512BW-NEXT: vpsubb %zmm1, %zmm0, %zmm0
-; GFNIAVX512BW-NEXT: retq
+; GFNIAVX512-LABEL: splatconstant_ashr_v64i8:
+; GFNIAVX512: # %bb.0:
+; GFNIAVX512-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0
+; GFNIAVX512-NEXT: retq
%shift = ashr <64 x i8> %a, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
ret <64 x i8> %shift
}
diff --git a/llvm/test/CodeGen/X86/min-legal-vector-width.ll b/llvm/test/CodeGen/X86/min-legal-vector-width.ll
index a953c505cd8ee8..f3a8ca4de9975f 100644
--- a/llvm/test/CodeGen/X86/min-legal-vector-width.ll
+++ b/llvm/test/CodeGen/X86/min-legal-vector-width.ll
@@ -5,10 +5,10 @@
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=skylake-avx512 | FileCheck %s --check-prefixes=CHECK,CHECK-AVX512
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=-avx512vnni -mcpu=cascadelake | FileCheck %s --check-prefixes=CHECK,CHECK-AVX512
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=-avx512vnni -mcpu=cooperlake | FileCheck %s --check-prefixes=CHECK,CHECK-AVX512
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=cannonlake | FileCheck %s --check-prefixes=CHECK,CHECK-VBMI
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=-avx512vnni -mcpu=icelake-client | FileCheck %s --check-prefixes=CHECK,CHECK-VBMI
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=-avx512vnni -mcpu=icelake-server | FileCheck %s --check-prefixes=CHECK,CHECK-VBMI
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=-avx512vnni -mcpu=tigerlake | FileCheck %s --check-prefixes=CHECK,CHECK-VBMI
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=cannonlake | FileCheck %s --check-prefixes=CHECK,CHECK-VBMI,CHECK-VBMI1
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=-avx512vnni -mcpu=icelake-client | FileCheck %s --check-prefixes=CHECK,CHECK-VBMI,CHECK-GFNI
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=-avx512vnni -mcpu=icelake-server | FileCheck %s --check-prefixes=CHECK,CHECK-VBMI,CHECK-GFNI
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=-avx512vnni -mcpu=tigerlake | FileCheck %s --check-prefixes=CHECK,CHECK-VBMI,CHECK-GFNI
; This file primarily contains tests for specific places in X86ISelLowering.cpp that needed be made aware of the legalizer not allowing 512-bit vectors due to prefer-256-bit even though AVX512 is enabled.
@@ -2006,12 +2006,31 @@ define <32 x i8> @constant_rotate_v32i8(<32 x i8> %a) nounwind "min-legal-vector
}
define <32 x i8> @splatconstant_rotate_v32i8(<32 x i8> %a) nounwind "min-legal-vector-width"="256" {
-; CHECK-LABEL: splatconstant_rotate_v32i8:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vpsllw $4, %ymm0, %ymm1
-; CHECK-NEXT: vpsrlw $4, %ymm0, %ymm0
-; CHECK-NEXT: vpternlogd $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm1, %ymm0
-; CHECK-NEXT: retq
+; CHECK-SKX-LABEL: splatconstant_rotate_v32i8:
+; CHECK-SKX: # %bb.0:
+; CHECK-SKX-NEXT: vpsllw $4, %ymm0, %ymm1
+; CHECK-SKX-NEXT: vpsrlw $4, %ymm0, %ymm0
+; CHECK-SKX-NEXT: vpternlogd $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm1, %ymm0
+; CHECK-SKX-NEXT: retq
+;
+; CHECK-AVX512-LABEL: splatconstant_rotate_v32i8:
+; CHECK-AVX512: # %bb.0:
+; CHECK-AVX512-NEXT: vpsllw $4, %ymm0, %ymm1
+; CHECK-AVX512-NEXT: vpsrlw $4, %ymm0, %ymm0
+; CHECK-AVX512-NEXT: vpternlogd $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm1, %ymm0
+; CHECK-AVX512-NEXT: retq
+;
+; CHECK-VBMI1-LABEL: splatconstant_rotate_v32i8:
+; CHECK-VBMI1: # %bb.0:
+; CHECK-VBMI1-NEXT: vpsllw $4, %ymm0, %ymm1
+; CHECK-VBMI1-NEXT: vpsrlw $4, %ymm0, %ymm0
+; CHECK-VBMI1-NEXT: vpternlogd $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm1, %ymm0
+; CHECK-VBMI1-NEXT: retq
+;
+; CHECK-GFNI-LABEL: splatconstant_rotate_v32i8:
+; CHECK-GFNI: # %bb.0:
+; CHECK-GFNI-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %ymm0
+; CHECK-GFNI-NEXT: retq
%shl = shl <32 x i8> %a, <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4>
%lshr = lshr <32 x i8> %a, <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4>
%or = or <32 x i8> %shl, %lshr
@@ -2019,13 +2038,35 @@ define <32 x i8> @splatconstant_rotate_v32i8(<32 x i8> %a) nounwind "min-legal-v
}
define <32 x i8> @splatconstant_rotate_mask_v32i8(<32 x i8> %a) nounwind "min-legal-vector-width"="256" {
-; CHECK-LABEL: splatconstant_rotate_mask_v32i8:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vpsllw $4, %ymm0, %ymm1
-; CHECK-NEXT: vpsrlw $4, %ymm0, %ymm0
-; CHECK-NEXT: vpternlogd $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm1, %ymm0
-; CHECK-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %ymm0
-; CHECK-NEXT: retq
+; CHECK-SKX-LABEL: splatconstant_rotate_mask_v32i8:
+; CHECK-SKX: # %bb.0:
+; CHECK-SKX-NEXT: vpsllw $4, %ymm0, %ymm1
+; CHECK-SKX-NEXT: vpsrlw $4, %ymm0, %ymm0
+; CHECK-SKX-NEXT: vpternlogd $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm1, %ymm0
+; CHECK-SKX-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %ymm0
+; CHECK-SKX-NEXT: retq
+;
+; CHECK-AVX512-LABEL: splatconstant_rotate_mask_v32i8:
+; CHECK-AVX512: # %bb.0:
+; CHECK-AVX512-NEXT: vpsllw $4, %ymm0, %ymm1
+; CHECK-AVX512-NEXT: vpsrlw $4, %ymm0, %ymm0
+; CHECK-AVX512-NEXT: vpternlogd $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm1, %ymm0
+; CHECK-AVX512-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %ymm0
+; CHECK-AVX512-NEXT: retq
+;
+; CHECK-VBMI1-LABEL: splatconstant_rotate_mask_v32i8:
+; CHECK-VBMI1: # %bb.0:
+; CHECK-VBMI1-NEXT: vpsllw $4, %ymm0, %ymm1
+; CHECK-VBMI1-NEXT: vpsrlw $4, %ymm0, %ymm0
+; CHECK-VBMI1-NEXT: vpternlogd $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm1, %ymm0
+; CHECK-VBMI1-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %ymm0
+; CHECK-VBMI1-NEXT: retq
+;
+; CHECK-GFNI-LABEL: splatconstant_rotate_mask_v32i8:
+; CHECK-GFNI: # %bb.0:
+; CHECK-GFNI-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %ymm0
+; CHECK-GFNI-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %ymm0
+; CHECK-GFNI-NEXT: retq
%shl = shl <32 x i8> %a, <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4>
%lshr = lshr <32 x i8> %a, <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4>
%rmask = and <32 x i8> %lshr, <i8 55, i8 55, i8 55, i8 55, i8 55, i8 55, i8 55, i8 55, i8 55, i8 55, i8 55, i8 55, i8 55, i8 55, i8 55, i8 55, i8 55, i8 55, i8 55, i8 55, i8 55, i8 55, i8 55, i8 55, i8 55, i8 55, i8 55, i8 55, i8 55, i8 55, i8 55, i8 55>
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