[llvm] 4821882 - [RISCV][llvm-mca] Add vector crypto llvm-mca tests for P600
Michael Maitland via llvm-commits
llvm-commits at lists.llvm.org
Fri May 3 08:03:58 PDT 2024
Author: Michael Maitland
Date: 2024-05-03T08:03:39-07:00
New Revision: 4821882cdfe46b93935e01805ed413cf1272bcd4
URL: https://github.com/llvm/llvm-project/commit/4821882cdfe46b93935e01805ed413cf1272bcd4
DIFF: https://github.com/llvm/llvm-project/commit/4821882cdfe46b93935e01805ed413cf1272bcd4.diff
LOG: [RISCV][llvm-mca] Add vector crypto llvm-mca tests for P600
Added:
llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvbb.s
llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvbc.s
llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvkg.s
llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvkned.s
llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvknhb.s
llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvksed.s
llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvksh.s
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
index c8b31c13ce3f8c..f222ba9c20a26c 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
@@ -60,8 +60,7 @@ multiclass VROR_IV_V_X_I<string opcodestr, bits<6> funct6>
// op vd, vs2, vs1
class PALUVVNoVm<bits<6> funct6, RISCVVFormat opv, string opcodestr>
- : VALUVVNoVm<funct6, opv, opcodestr>,
- SchedUnaryMC<"WriteVIALUI", "ReadVIALUV"> {
+ : VALUVVNoVm<funct6, opv, opcodestr> {
let Inst{6-0} = OPC_OP_VE.Value;
}
@@ -69,8 +68,7 @@ class PALUVVNoVm<bits<6> funct6, RISCVVFormat opv, string opcodestr>
class PALUVVNoVmTernary<bits<6> funct6, RISCVVFormat opv, string opcodestr>
: RVInstVV<funct6, opv, (outs VR:$vd_wb),
(ins VR:$vd, VR:$vs2, VR:$vs1),
- opcodestr, "$vd, $vs2, $vs1">,
- SchedBinaryMC<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV"> {
+ opcodestr, "$vd, $vs2, $vs1"> {
let Constraints = "$vd = $vd_wb";
let vm = 1;
let Inst{6-0} = OPC_OP_VE.Value;
@@ -78,8 +76,7 @@ class PALUVVNoVmTernary<bits<6> funct6, RISCVVFormat opv, string opcodestr>
// op vd, vs2, imm
class PALUVINoVm<bits<6> funct6, string opcodestr, Operand optype>
- : VALUVINoVm<funct6, opcodestr, optype>,
- SchedUnaryMC<"WriteVIALUV", "ReadVIALUV"> {
+ : VALUVINoVm<funct6, opcodestr, optype> {
let Inst{6-0} = OPC_OP_VE.Value;
let Inst{14-12} = OPMVV.Value;
}
@@ -88,8 +85,7 @@ class PALUVINoVm<bits<6> funct6, string opcodestr, Operand optype>
class PALUVINoVmBinary<bits<6> funct6, string opcodestr, Operand optype>
: RVInstIVI<funct6, (outs VR:$vd_wb),
(ins VR:$vd, VR:$vs2, optype:$imm),
- opcodestr, "$vd, $vs2, $imm">,
- SchedBinaryMC<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV"> {
+ opcodestr, "$vd, $vs2, $imm"> {
let Constraints = "$vd = $vd_wb";
let vm = 1;
let Inst{6-0} = OPC_OP_VE.Value;
@@ -101,8 +97,7 @@ class PALUVINoVmBinary<bits<6> funct6, string opcodestr, Operand optype>
class PALUVs2NoVmBinary<bits<6> funct6, bits<5> vs1, RISCVVFormat opv,
string opcodestr>
: RVInstV<funct6, vs1, opv, (outs VR:$vd_wb), (ins VR:$vd, VR:$vs2),
- opcodestr, "$vd, $vs2">,
- SchedBinaryMC<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV"> {
+ opcodestr, "$vd, $vs2"> {
let Constraints = "$vd = $vd_wb";
let vm = 1;
let Inst{6-0} = OPC_OP_VE.Value;
@@ -111,9 +106,11 @@ class PALUVs2NoVmBinary<bits<6> funct6, bits<5> vs1, RISCVVFormat opv,
multiclass VAES_MV_V_S<bits<6> funct6_vv, bits<6> funct6_vs, bits<5> vs1,
RISCVVFormat opv, string opcodestr> {
let RVVConstraint = NoConstraint in
- def NAME # _VV : PALUVs2NoVmBinary<funct6_vv, vs1, opv, opcodestr # ".vv">;
+ def NAME # _VV : PALUVs2NoVmBinary<funct6_vv, vs1, opv, opcodestr # ".vv">,
+ SchedBinaryMC<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV">;
let RVVConstraint = VS2Constraint in
- def NAME # _VS : PALUVs2NoVmBinary<funct6_vs, vs1, opv, opcodestr # ".vs">;
+ def NAME # _VS : PALUVs2NoVmBinary<funct6_vs, vs1, opv, opcodestr # ".vs">,
+ SchedBinaryMC<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV">;
}
} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
@@ -144,14 +141,23 @@ let Predicates = [HasStdExtZvkb] in {
} // Predicates = [HasStdExtZvkb]
let Predicates = [HasStdExtZvkg], RVVConstraint = NoConstraint in {
- def VGHSH_VV : PALUVVNoVmTernary<0b101100, OPMVV, "vghsh.vv">;
- def VGMUL_VV : PALUVs2NoVmBinary<0b101000, 0b10001, OPMVV, "vgmul.vv">;
+ def VGHSH_VV : PALUVVNoVmTernary<0b101100, OPMVV, "vghsh.vv">,
+ SchedTernaryMC<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV",
+ "ReadVIALUV">;
+ def VGMUL_VV : PALUVs2NoVmBinary<0b101000, 0b10001, OPMVV, "vgmul.vv">,
+ SchedBinaryMC<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV">;
} // Predicates = [HasStdExtZvkg]
let Predicates = [HasStdExtZvknhaOrZvknhb], RVVConstraint = Sha2Constraint in {
- def VSHA2CH_VV : PALUVVNoVmTernary<0b101110, OPMVV, "vsha2ch.vv">;
- def VSHA2CL_VV : PALUVVNoVmTernary<0b101111, OPMVV, "vsha2cl.vv">;
- def VSHA2MS_VV : PALUVVNoVmTernary<0b101101, OPMVV, "vsha2ms.vv">;
+ def VSHA2CH_VV : PALUVVNoVmTernary<0b101110, OPMVV, "vsha2ch.vv">,
+ SchedTernaryMC<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV",
+ "ReadVIALUV">;
+ def VSHA2CL_VV : PALUVVNoVmTernary<0b101111, OPMVV, "vsha2cl.vv">,
+ SchedTernaryMC<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV",
+ "ReadVIALUV">;
+ def VSHA2MS_VV : PALUVVNoVmTernary<0b101101, OPMVV, "vsha2ms.vv">,
+ SchedTernaryMC<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV",
+ "ReadVIALUV">;
} // Predicates = [HasStdExtZvknhaOrZvknhb]
let Predicates = [HasStdExtZvkned] in {
@@ -159,21 +165,27 @@ let Predicates = [HasStdExtZvkned] in {
defm VAESDM : VAES_MV_V_S<0b101000, 0b101001, 0b00000, OPMVV, "vaesdm">;
defm VAESEF : VAES_MV_V_S<0b101000, 0b101001, 0b00011, OPMVV, "vaesef">;
defm VAESEM : VAES_MV_V_S<0b101000, 0b101001, 0b00010, OPMVV, "vaesem">;
- def VAESKF1_VI : PALUVINoVm<0b100010, "vaeskf1.vi", uimm5>;
- def VAESKF2_VI : PALUVINoVmBinary<0b101010, "vaeskf2.vi", uimm5>;
+ def VAESKF1_VI : PALUVINoVm<0b100010, "vaeskf1.vi", uimm5>,
+ SchedUnaryMC<"WriteVIALUV", "ReadVIALUV">;
+ def VAESKF2_VI : PALUVINoVmBinary<0b101010, "vaeskf2.vi", uimm5>,
+ SchedBinaryMC<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV">;
let RVVConstraint = VS2Constraint in
- def VAESZ_VS : PALUVs2NoVmBinary<0b101001, 0b00111, OPMVV, "vaesz.vs">;
+ def VAESZ_VS : PALUVs2NoVmBinary<0b101001, 0b00111, OPMVV, "vaesz.vs">,
+ SchedBinaryMC<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV">;
} // Predicates = [HasStdExtZvkned]
let Predicates = [HasStdExtZvksed] in {
let RVVConstraint = NoConstraint in
- def VSM4K_VI : PALUVINoVm<0b100001, "vsm4k.vi", uimm5>;
+ def VSM4K_VI : PALUVINoVm<0b100001, "vsm4k.vi", uimm5>,
+ SchedUnaryMC<"WriteVIALUV", "ReadVIALUV">;
defm VSM4R : VAES_MV_V_S<0b101000, 0b101001, 0b10000, OPMVV, "vsm4r">;
} // Predicates = [HasStdExtZvksed]
let Predicates = [HasStdExtZvksh], RVVConstraint = VS2Constraint in {
- def VSM3C_VI : PALUVINoVmBinary<0b101011, "vsm3c.vi", uimm5>;
- def VSM3ME_VV : PALUVVNoVm<0b100000, OPMVV, "vsm3me.vv">;
+ def VSM3C_VI : PALUVINoVmBinary<0b101011, "vsm3c.vi", uimm5>,
+ SchedBinaryMC<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV">;
+ def VSM3ME_VV : PALUVVNoVm<0b100000, OPMVV, "vsm3me.vv">,
+ SchedUnaryMC<"WriteVIALUI", "ReadVIALUV">;
} // Predicates = [HasStdExtZvksh]
//===----------------------------------------------------------------------===//
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvbb.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvbb.s
new file mode 100644
index 00000000000000..4207477d0e7ae2
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvbb.s
@@ -0,0 +1,461 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p670 -iterations=1 < %s | FileCheck %s
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vandn.vv v4, v8, v12
+vandn.vx v4, v8, a0
+vbrev.v v4, v8
+vbrev8.v v4, v8
+vrev8.v v4, v8
+vclz.v v4, v8
+vctz.v v4, v8
+vcpop.v v4, v8
+vrol.vv v4, v8, v12
+vrol.vx v4, v8, a0
+vror.vv v4, v8, v12
+vror.vx v4, v8, a0
+vror.vi v4, v8, 8
+
+vwsll.vv v4, v8, v12
+vwsll.vx v4, v8, a0
+vwsll.vi v4, v8, 8
+
+vsetvli zero, zero, e16, mf4, tu, mu
+vandn.vv v4, v8, v12
+vandn.vx v4, v8, a0
+vbrev.v v4, v8
+vbrev8.v v4, v8
+vrev8.v v4, v8
+vclz.v v4, v8
+vctz.v v4, v8
+vcpop.v v4, v8
+vrol.vv v4, v8, v12
+vrol.vx v4, v8, a0
+vror.vv v4, v8, v12
+vror.vx v4, v8, a0
+vror.vi v4, v8, 8
+
+vwsll.vv v4, v8, v12
+vwsll.vx v4, v8, a0
+vwsll.vi v4, v8, 8
+
+vsetvli zero, zero, e32, mf2, tu, mu
+vandn.vv v4, v8, v12
+vandn.vx v4, v8, a0
+vbrev.v v4, v8
+vbrev8.v v4, v8
+vrev8.v v4, v8
+vclz.v v4, v8
+vctz.v v4, v8
+vcpop.v v4, v8
+vrol.vv v4, v8, v12
+vrol.vx v4, v8, a0
+vror.vv v4, v8, v12
+vror.vx v4, v8, a0
+vror.vi v4, v8, 8
+
+vwsll.vv v4, v8, v12
+vwsll.vx v4, v8, a0
+vwsll.vi v4, v8, 8
+
+vsetvli zero, zero, e32, m1, tu, mu
+vandn.vv v4, v8, v12
+vandn.vx v4, v8, a0
+vbrev.v v4, v8
+vbrev8.v v4, v8
+vrev8.v v4, v8
+vclz.v v4, v8
+vctz.v v4, v8
+vcpop.v v4, v8
+vrol.vv v4, v8, v12
+vrol.vx v4, v8, a0
+vror.vv v4, v8, v12
+vror.vx v4, v8, a0
+vror.vi v4, v8, 8
+
+vwsll.vv v4, v8, v12
+vwsll.vx v4, v8, a0
+vwsll.vi v4, v8, 8
+
+vsetvli zero, zero, e32, m2, tu, mu
+vandn.vv v4, v8, v12
+vandn.vx v4, v8, a0
+vbrev.v v4, v8
+vbrev8.v v4, v8
+vrev8.v v4, v8
+vclz.v v4, v8
+vctz.v v4, v8
+vcpop.v v4, v8
+vrol.vv v4, v8, v12
+vrol.vx v4, v8, a0
+vror.vv v4, v8, v12
+vror.vx v4, v8, a0
+vror.vi v4, v8, 8
+
+vwsll.vv v4, v8, v12
+vwsll.vx v4, v8, a0
+vwsll.vi v4, v8, 8
+
+vsetvli zero, zero, e32, m4, tu, mu
+vandn.vv v4, v8, v12
+vandn.vx v4, v8, a0
+vbrev.v v4, v8
+vbrev8.v v4, v8
+vrev8.v v4, v8
+vclz.v v4, v8
+vctz.v v4, v8
+vcpop.v v4, v8
+vrol.vv v4, v8, v12
+vrol.vx v4, v8, a0
+vror.vv v4, v8, v12
+vror.vx v4, v8, a0
+vror.vi v4, v8, 8
+
+vwsll.vv v8, v4, v12
+vwsll.vx v8, v4, a0
+vwsll.vi v8, v4, 8
+
+vsetvli zero, zero, e32, m8, tu, mu
+vandn.vv v8, v16, v24
+vandn.vx v8, v16, a0
+vbrev.v v8, v16
+vbrev8.v v8, v16
+vrev8.v v8, v16
+vclz.v v8, v16
+vctz.v v8, v16
+vcpop.v v8, v16
+vrol.vv v8, v16, v24
+vrol.vx v8, v16, a0
+vror.vv v8, v16, v24
+vror.vx v8, v16, a0
+vror.vi v8, v16, 8
+
+# Show SEW does not matter
+vsetvli zero, zero, e16, m4, tu, mu
+vandn.vv v4, v8, v12
+vandn.vx v4, v8, a0
+vbrev.v v4, v8
+vbrev8.v v4, v8
+vrev8.v v4, v8
+vclz.v v4, v8
+vctz.v v4, v8
+vcpop.v v4, v8
+vrol.vv v4, v8, v12
+vrol.vx v4, v8, a0
+vror.vv v4, v8, v12
+vror.vx v4, v8, a0
+vror.vi v4, v8, 8
+vwsll.vv v8, v4, v12
+vwsll.vx v8, v4, a0
+vwsll.vi v8, v4, 8
+
+# CHECK: Iterations: 1
+# CHECK-NEXT: Instructions: 133
+# CHECK-NEXT: Total Cycles: 170
+# CHECK-NEXT: Total uOps: 133
+
+# CHECK: Dispatch Width: 4
+# CHECK-NEXT: uOps Per Cycle: 0.78
+# CHECK-NEXT: IPC: 0.78
+# CHECK-NEXT: Block RThroughput: 164.0
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 0.50 vandn.vv v4, v8, v12
+# CHECK-NEXT: 1 1 0.50 vandn.vx v4, v8, a0
+# CHECK-NEXT: 1 1 0.50 vbrev.v v4, v8
+# CHECK-NEXT: 1 1 0.50 vbrev8.v v4, v8
+# CHECK-NEXT: 1 1 0.50 vrev8.v v4, v8
+# CHECK-NEXT: 1 1 0.50 vclz.v v4, v8
+# CHECK-NEXT: 1 1 0.50 vctz.v v4, v8
+# CHECK-NEXT: 1 1 0.50 vcpop.v v4, v8
+# CHECK-NEXT: 1 1 0.50 vrol.vv v4, v8, v12
+# CHECK-NEXT: 1 1 0.50 vrol.vx v4, v8, a0
+# CHECK-NEXT: 1 1 0.50 vror.vv v4, v8, v12
+# CHECK-NEXT: 1 1 0.50 vror.vx v4, v8, a0
+# CHECK-NEXT: 1 1 0.50 vror.vi v4, v8, 8
+# CHECK-NEXT: 1 6 0.50 vwsll.vv v4, v8, v12
+# CHECK-NEXT: 1 6 0.50 vwsll.vx v4, v8, a0
+# CHECK-NEXT: 1 6 0.50 vwsll.vi v4, v8, 8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.50 vandn.vv v4, v8, v12
+# CHECK-NEXT: 1 1 0.50 vandn.vx v4, v8, a0
+# CHECK-NEXT: 1 1 0.50 vbrev.v v4, v8
+# CHECK-NEXT: 1 1 0.50 vbrev8.v v4, v8
+# CHECK-NEXT: 1 1 0.50 vrev8.v v4, v8
+# CHECK-NEXT: 1 1 0.50 vclz.v v4, v8
+# CHECK-NEXT: 1 1 0.50 vctz.v v4, v8
+# CHECK-NEXT: 1 1 0.50 vcpop.v v4, v8
+# CHECK-NEXT: 1 1 0.50 vrol.vv v4, v8, v12
+# CHECK-NEXT: 1 1 0.50 vrol.vx v4, v8, a0
+# CHECK-NEXT: 1 1 0.50 vror.vv v4, v8, v12
+# CHECK-NEXT: 1 1 0.50 vror.vx v4, v8, a0
+# CHECK-NEXT: 1 1 0.50 vror.vi v4, v8, 8
+# CHECK-NEXT: 1 6 0.50 vwsll.vv v4, v8, v12
+# CHECK-NEXT: 1 6 0.50 vwsll.vx v4, v8, a0
+# CHECK-NEXT: 1 6 0.50 vwsll.vi v4, v8, 8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.50 vandn.vv v4, v8, v12
+# CHECK-NEXT: 1 1 0.50 vandn.vx v4, v8, a0
+# CHECK-NEXT: 1 1 0.50 vbrev.v v4, v8
+# CHECK-NEXT: 1 1 0.50 vbrev8.v v4, v8
+# CHECK-NEXT: 1 1 0.50 vrev8.v v4, v8
+# CHECK-NEXT: 1 1 0.50 vclz.v v4, v8
+# CHECK-NEXT: 1 1 0.50 vctz.v v4, v8
+# CHECK-NEXT: 1 1 0.50 vcpop.v v4, v8
+# CHECK-NEXT: 1 1 0.50 vrol.vv v4, v8, v12
+# CHECK-NEXT: 1 1 0.50 vrol.vx v4, v8, a0
+# CHECK-NEXT: 1 1 0.50 vror.vv v4, v8, v12
+# CHECK-NEXT: 1 1 0.50 vror.vx v4, v8, a0
+# CHECK-NEXT: 1 1 0.50 vror.vi v4, v8, 8
+# CHECK-NEXT: 1 6 0.50 vwsll.vv v4, v8, v12
+# CHECK-NEXT: 1 6 0.50 vwsll.vx v4, v8, a0
+# CHECK-NEXT: 1 6 0.50 vwsll.vi v4, v8, 8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 0.50 vandn.vv v4, v8, v12
+# CHECK-NEXT: 1 1 0.50 vandn.vx v4, v8, a0
+# CHECK-NEXT: 1 1 0.50 vbrev.v v4, v8
+# CHECK-NEXT: 1 1 0.50 vbrev8.v v4, v8
+# CHECK-NEXT: 1 1 0.50 vrev8.v v4, v8
+# CHECK-NEXT: 1 1 0.50 vclz.v v4, v8
+# CHECK-NEXT: 1 1 0.50 vctz.v v4, v8
+# CHECK-NEXT: 1 1 0.50 vcpop.v v4, v8
+# CHECK-NEXT: 1 1 0.50 vrol.vv v4, v8, v12
+# CHECK-NEXT: 1 1 0.50 vrol.vx v4, v8, a0
+# CHECK-NEXT: 1 1 0.50 vror.vv v4, v8, v12
+# CHECK-NEXT: 1 1 0.50 vror.vx v4, v8, a0
+# CHECK-NEXT: 1 1 0.50 vror.vi v4, v8, 8
+# CHECK-NEXT: 1 6 0.50 vwsll.vv v4, v8, v12
+# CHECK-NEXT: 1 6 0.50 vwsll.vx v4, v8, a0
+# CHECK-NEXT: 1 6 0.50 vwsll.vi v4, v8, 8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 vandn.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 vandn.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 vbrev.v v4, v8
+# CHECK-NEXT: 1 1 1.00 vbrev8.v v4, v8
+# CHECK-NEXT: 1 1 1.00 vrev8.v v4, v8
+# CHECK-NEXT: 1 1 1.00 vclz.v v4, v8
+# CHECK-NEXT: 1 1 1.00 vctz.v v4, v8
+# CHECK-NEXT: 1 1 1.00 vcpop.v v4, v8
+# CHECK-NEXT: 1 1 1.00 vrol.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 vrol.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 vror.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 vror.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 vror.vi v4, v8, 8
+# CHECK-NEXT: 1 6 1.00 vwsll.vv v4, v8, v12
+# CHECK-NEXT: 1 6 1.00 vwsll.vx v4, v8, a0
+# CHECK-NEXT: 1 6 1.00 vwsll.vi v4, v8, 8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 2.00 vandn.vv v4, v8, v12
+# CHECK-NEXT: 1 1 2.00 vandn.vx v4, v8, a0
+# CHECK-NEXT: 1 1 2.00 vbrev.v v4, v8
+# CHECK-NEXT: 1 1 2.00 vbrev8.v v4, v8
+# CHECK-NEXT: 1 1 2.00 vrev8.v v4, v8
+# CHECK-NEXT: 1 1 2.00 vclz.v v4, v8
+# CHECK-NEXT: 1 1 2.00 vctz.v v4, v8
+# CHECK-NEXT: 1 1 2.00 vcpop.v v4, v8
+# CHECK-NEXT: 1 1 2.00 vrol.vv v4, v8, v12
+# CHECK-NEXT: 1 1 2.00 vrol.vx v4, v8, a0
+# CHECK-NEXT: 1 1 2.00 vror.vv v4, v8, v12
+# CHECK-NEXT: 1 1 2.00 vror.vx v4, v8, a0
+# CHECK-NEXT: 1 1 2.00 vror.vi v4, v8, 8
+# CHECK-NEXT: 1 6 2.00 vwsll.vv v8, v4, v12
+# CHECK-NEXT: 1 6 2.00 vwsll.vx v8, v4, a0
+# CHECK-NEXT: 1 6 2.00 vwsll.vi v8, v4, 8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 4.00 vandn.vv v8, v16, v24
+# CHECK-NEXT: 1 1 4.00 vandn.vx v8, v16, a0
+# CHECK-NEXT: 1 1 4.00 vbrev.v v8, v16
+# CHECK-NEXT: 1 1 4.00 vbrev8.v v8, v16
+# CHECK-NEXT: 1 1 4.00 vrev8.v v8, v16
+# CHECK-NEXT: 1 1 4.00 vclz.v v8, v16
+# CHECK-NEXT: 1 1 4.00 vctz.v v8, v16
+# CHECK-NEXT: 1 1 4.00 vcpop.v v8, v16
+# CHECK-NEXT: 1 1 4.00 vrol.vv v8, v16, v24
+# CHECK-NEXT: 1 1 4.00 vrol.vx v8, v16, a0
+# CHECK-NEXT: 1 1 4.00 vror.vv v8, v16, v24
+# CHECK-NEXT: 1 1 4.00 vror.vx v8, v16, a0
+# CHECK-NEXT: 1 1 4.00 vror.vi v8, v16, 8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 2.00 vandn.vv v4, v8, v12
+# CHECK-NEXT: 1 1 2.00 vandn.vx v4, v8, a0
+# CHECK-NEXT: 1 1 2.00 vbrev.v v4, v8
+# CHECK-NEXT: 1 1 2.00 vbrev8.v v4, v8
+# CHECK-NEXT: 1 1 2.00 vrev8.v v4, v8
+# CHECK-NEXT: 1 1 2.00 vclz.v v4, v8
+# CHECK-NEXT: 1 1 2.00 vctz.v v4, v8
+# CHECK-NEXT: 1 1 2.00 vcpop.v v4, v8
+# CHECK-NEXT: 1 1 2.00 vrol.vv v4, v8, v12
+# CHECK-NEXT: 1 1 2.00 vrol.vx v4, v8, a0
+# CHECK-NEXT: 1 1 2.00 vror.vv v4, v8, v12
+# CHECK-NEXT: 1 1 2.00 vror.vx v4, v8, a0
+# CHECK-NEXT: 1 1 2.00 vror.vi v4, v8, 8
+# CHECK-NEXT: 1 6 2.00 vwsll.vv v8, v4, v12
+# CHECK-NEXT: 1 6 2.00 vwsll.vx v8, v4, a0
+# CHECK-NEXT: 1 6 2.00 vwsll.vi v8, v4, 8
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP600Div
+# CHECK-NEXT: [1] - SiFiveP600FEXQ0
+# CHECK-NEXT: [2] - SiFiveP600FEXQ1
+# CHECK-NEXT: [3] - SiFiveP600FloatDiv
+# CHECK-NEXT: [4] - SiFiveP600IEXQ0
+# CHECK-NEXT: [5] - SiFiveP600IEXQ1
+# CHECK-NEXT: [6] - SiFiveP600IEXQ2
+# CHECK-NEXT: [7] - SiFiveP600IEXQ3
+# CHECK-NEXT: [8.0] - SiFiveP600LDST
+# CHECK-NEXT: [8.1] - SiFiveP600LDST
+# CHECK-NEXT: [9] - SiFiveP600VDiv
+# CHECK-NEXT: [10] - SiFiveP600VEXQ0
+# CHECK-NEXT: [11] - SiFiveP600VEXQ1
+# CHECK-NEXT: [12] - SiFiveP600VFloatDiv
+# CHECK-NEXT: [13] - SiFiveP600VLD
+# CHECK-NEXT: [14] - SiFiveP600VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14]
+# CHECK-NEXT: - - - - 8.00 - - - - - - 164.00 164.00 - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14] Instructions:
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vandn.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vandn.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vbrev.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vbrev8.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vrev8.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vclz.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vctz.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vcpop.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vrol.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vrol.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vror.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vror.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vror.vi v4, v8, 8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vwsll.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vwsll.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vwsll.vi v4, v8, 8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vandn.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vandn.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vbrev.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vbrev8.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vrev8.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vclz.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vctz.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vcpop.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vrol.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vrol.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vror.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vror.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vror.vi v4, v8, 8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vwsll.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vwsll.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vwsll.vi v4, v8, 8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vandn.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vandn.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vbrev.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vbrev8.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vrev8.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vclz.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vctz.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vcpop.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vrol.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vrol.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vror.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vror.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vror.vi v4, v8, 8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vwsll.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vwsll.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vwsll.vi v4, v8, 8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vandn.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vandn.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vbrev.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vbrev8.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vrev8.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vclz.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vctz.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vcpop.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vrol.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vrol.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vror.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vror.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vror.vi v4, v8, 8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vwsll.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vwsll.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vwsll.vi v4, v8, 8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 - - - vandn.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vandn.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 - - - vbrev.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vbrev8.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 - - - vrev8.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vclz.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 - - - vctz.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vcpop.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 - - - vrol.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vrol.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 - - - vror.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vror.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 - - - vror.vi v4, v8, 8
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vwsll.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 - - - vwsll.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vwsll.vi v4, v8, 8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vandn.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vandn.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vbrev.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vbrev8.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vrev8.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vclz.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vctz.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vcpop.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vrol.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vrol.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vror.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vror.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vror.vi v4, v8, 8
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vwsll.vv v8, v4, v12
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vwsll.vx v8, v4, a0
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vwsll.vi v8, v4, 8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vandn.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vandn.vx v8, v16, a0
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vbrev.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vbrev8.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vrev8.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vclz.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vctz.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vcpop.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vrol.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vrol.vx v8, v16, a0
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vror.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vror.vx v8, v16, a0
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vror.vi v8, v16, 8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vandn.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vandn.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vbrev.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vbrev8.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vrev8.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vclz.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vctz.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vcpop.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vrol.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vrol.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vror.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vror.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vror.vi v4, v8, 8
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vwsll.vv v8, v4, v12
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vwsll.vx v8, v4, a0
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vwsll.vi v8, v4, 8
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvbc.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvbc.s
new file mode 100644
index 00000000000000..291befcd8ba442
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvbc.s
@@ -0,0 +1,113 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p670 -iterations=1 < %s | FileCheck %s
+
+# These instructions only work with e64
+
+vsetvli zero, zero, e64, m1, tu, mu
+vclmul.vv v4, v8, v12
+vclmul.vx v4, v8, a0
+vclmulh.vv v4, v8, v12
+vclmulh.vx v4, v8, a0
+
+vsetvli zero, zero, e64, m2, tu, mu
+vclmul.vv v4, v8, v12
+vclmul.vx v4, v8, a0
+vclmulh.vv v4, v8, v12
+vclmulh.vx v4, v8, a0
+
+vsetvli zero, zero, e64, m4, tu, mu
+vclmul.vv v4, v8, v12
+vclmul.vx v4, v8, a0
+vclmulh.vv v4, v8, v12
+vclmulh.vx v4, v8, a0
+
+vsetvli zero, zero, e64, m8, tu, mu
+vclmul.vv v8, v12, v24
+vclmul.vx v8, v12, a0
+vclmulh.vv v8, v12, v24
+vclmulh.vx v8, v12, a0
+
+# CHECK: Iterations: 1
+# CHECK-NEXT: Instructions: 20
+# CHECK-NEXT: Total Cycles: 27
+# CHECK-NEXT: Total uOps: 20
+
+# CHECK: Dispatch Width: 4
+# CHECK-NEXT: uOps Per Cycle: 0.74
+# CHECK-NEXT: IPC: 0.74
+# CHECK-NEXT: Block RThroughput: 30.0
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 0.50 vclmul.vv v4, v8, v12
+# CHECK-NEXT: 1 1 0.50 vclmul.vx v4, v8, a0
+# CHECK-NEXT: 1 1 0.50 vclmulh.vv v4, v8, v12
+# CHECK-NEXT: 1 1 0.50 vclmulh.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 vclmul.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 vclmul.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 vclmulh.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 vclmulh.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 2.00 vclmul.vv v4, v8, v12
+# CHECK-NEXT: 1 1 2.00 vclmul.vx v4, v8, a0
+# CHECK-NEXT: 1 1 2.00 vclmulh.vv v4, v8, v12
+# CHECK-NEXT: 1 1 2.00 vclmulh.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 4.00 vclmul.vv v8, v12, v24
+# CHECK-NEXT: 1 1 4.00 vclmul.vx v8, v12, a0
+# CHECK-NEXT: 1 1 4.00 vclmulh.vv v8, v12, v24
+# CHECK-NEXT: 1 1 4.00 vclmulh.vx v8, v12, a0
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP600Div
+# CHECK-NEXT: [1] - SiFiveP600FEXQ0
+# CHECK-NEXT: [2] - SiFiveP600FEXQ1
+# CHECK-NEXT: [3] - SiFiveP600FloatDiv
+# CHECK-NEXT: [4] - SiFiveP600IEXQ0
+# CHECK-NEXT: [5] - SiFiveP600IEXQ1
+# CHECK-NEXT: [6] - SiFiveP600IEXQ2
+# CHECK-NEXT: [7] - SiFiveP600IEXQ3
+# CHECK-NEXT: [8.0] - SiFiveP600LDST
+# CHECK-NEXT: [8.1] - SiFiveP600LDST
+# CHECK-NEXT: [9] - SiFiveP600VDiv
+# CHECK-NEXT: [10] - SiFiveP600VEXQ0
+# CHECK-NEXT: [11] - SiFiveP600VEXQ1
+# CHECK-NEXT: [12] - SiFiveP600VFloatDiv
+# CHECK-NEXT: [13] - SiFiveP600VLD
+# CHECK-NEXT: [14] - SiFiveP600VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14]
+# CHECK-NEXT: - - - - 4.00 - - - - - - 30.00 30.00 - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14] Instructions:
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vclmul.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vclmul.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vclmulh.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vclmulh.vx v4, v8, a0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 - - - vclmul.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vclmul.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 - - - vclmulh.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vclmulh.vx v4, v8, a0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vclmul.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vclmul.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vclmulh.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vclmulh.vx v4, v8, a0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vclmul.vv v8, v12, v24
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vclmul.vx v8, v12, a0
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vclmulh.vv v8, v12, v24
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vclmulh.vx v8, v12, a0
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvkg.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvkg.s
new file mode 100644
index 00000000000000..9a64ac92769460
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvkg.s
@@ -0,0 +1,128 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p670 -iterations=1 < %s | FileCheck %s
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vghsh.vv v4, v8, v12
+vgmul.vv v4, v8
+
+vsetvli zero, zero, e16, mf4, tu, mu
+vghsh.vv v4, v8, v12
+vgmul.vv v4, v8
+
+vsetvli zero, zero, e32, mf2, tu, mu
+vghsh.vv v4, v8, v12
+vgmul.vv v4, v8
+
+vsetvli zero, zero, e32, m1, tu, mu
+vghsh.vv v4, v8, v12
+vgmul.vv v4, v8
+
+vsetvli zero, zero, e32, m2, tu, mu
+vghsh.vv v4, v8, v12
+vgmul.vv v4, v8
+
+vsetvli zero, zero, e32, m4, tu, mu
+vghsh.vv v4, v8, v12
+vgmul.vv v4, v8
+
+vsetvli zero, zero, e32, m8, tu, mu
+vghsh.vv v8, v16, v24
+vgmul.vv v8, v16
+
+# Show SEW does not matter
+vsetvli zero, zero, e64, m4, tu, mu
+vghsh.vv v4, v8, v12
+vgmul.vv v4, v8
+
+# CHECK: Iterations: 1
+# CHECK-NEXT: Instructions: 24
+# CHECK-NEXT: Total Cycles: 38
+# CHECK-NEXT: Total uOps: 24
+
+# CHECK: Dispatch Width: 4
+# CHECK-NEXT: uOps Per Cycle: 0.63
+# CHECK-NEXT: IPC: 0.63
+# CHECK-NEXT: Block RThroughput: 36.0
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 4.00 vghsh.vv v4, v8, v12
+# CHECK-NEXT: 1 1 4.00 vgmul.vv v4, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 4.00 vghsh.vv v4, v8, v12
+# CHECK-NEXT: 1 1 4.00 vgmul.vv v4, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.50 vghsh.vv v4, v8, v12
+# CHECK-NEXT: 1 1 0.50 vgmul.vv v4, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 0.50 vghsh.vv v4, v8, v12
+# CHECK-NEXT: 1 1 0.50 vgmul.vv v4, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 vghsh.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 vgmul.vv v4, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 2.00 vghsh.vv v4, v8, v12
+# CHECK-NEXT: 1 1 2.00 vgmul.vv v4, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 4.00 vghsh.vv v8, v16, v24
+# CHECK-NEXT: 1 1 4.00 vgmul.vv v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 2.00 vghsh.vv v4, v8, v12
+# CHECK-NEXT: 1 1 2.00 vgmul.vv v4, v8
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP600Div
+# CHECK-NEXT: [1] - SiFiveP600FEXQ0
+# CHECK-NEXT: [2] - SiFiveP600FEXQ1
+# CHECK-NEXT: [3] - SiFiveP600FloatDiv
+# CHECK-NEXT: [4] - SiFiveP600IEXQ0
+# CHECK-NEXT: [5] - SiFiveP600IEXQ1
+# CHECK-NEXT: [6] - SiFiveP600IEXQ2
+# CHECK-NEXT: [7] - SiFiveP600IEXQ3
+# CHECK-NEXT: [8.0] - SiFiveP600LDST
+# CHECK-NEXT: [8.1] - SiFiveP600LDST
+# CHECK-NEXT: [9] - SiFiveP600VDiv
+# CHECK-NEXT: [10] - SiFiveP600VEXQ0
+# CHECK-NEXT: [11] - SiFiveP600VEXQ1
+# CHECK-NEXT: [12] - SiFiveP600VFloatDiv
+# CHECK-NEXT: [13] - SiFiveP600VLD
+# CHECK-NEXT: [14] - SiFiveP600VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14]
+# CHECK-NEXT: - - - - 8.00 - - - - - - 35.00 37.00 - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14] Instructions:
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vghsh.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vgmul.vv v4, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vghsh.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vgmul.vv v4, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vghsh.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vgmul.vv v4, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vghsh.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vgmul.vv v4, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vghsh.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vgmul.vv v4, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vghsh.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vgmul.vv v4, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vghsh.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vgmul.vv v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vghsh.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vgmul.vv v4, v8
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvkned.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvkned.s
new file mode 100644
index 00000000000000..beea3efeaed066
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvkned.s
@@ -0,0 +1,204 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p670 -iterations=1 < %s | FileCheck %s
+
+# These instructions only support e32
+
+vsetvli zero, zero, e32, mf2, tu, mu
+vaesef.vv v4, v8
+vaesef.vs v4, v8
+vaesem.vv v4, v8
+vaesem.vs v4, v8
+vaesdm.vv v4, v8
+vaesdm.vs v4, v8
+vaeskf1.vi v4, v8, 8
+vaeskf2.vi v4, v8, 8
+vaesz.vs v4, v8
+
+vsetvli zero, zero, e32, m1, tu, mu
+vaesef.vv v4, v8
+vaesef.vs v4, v8
+vaesem.vv v4, v8
+vaesem.vs v4, v8
+vaesdm.vv v4, v8
+vaesdm.vs v4, v8
+vaeskf1.vi v4, v8, 8
+vaeskf2.vi v4, v8, 8
+vaesz.vs v4, v8
+
+vsetvli zero, zero, e32, m2, tu, mu
+vaesef.vv v4, v8
+vaesef.vs v4, v8
+vaesem.vv v4, v8
+vaesem.vs v4, v8
+vaesdm.vv v4, v8
+vaesdm.vs v4, v8
+vaeskf1.vi v4, v8, 8
+vaeskf2.vi v4, v8, 8
+vaesz.vs v4, v8
+
+vsetvli zero, zero, e32, m4, tu, mu
+vaesef.vv v4, v8
+vaesef.vs v4, v8
+vaesem.vv v4, v8
+vaesem.vs v4, v8
+vaesdm.vv v4, v8
+vaesdm.vs v4, v8
+vaeskf1.vi v4, v8, 8
+vaeskf2.vi v4, v8, 8
+vaesz.vs v4, v8
+
+vsetvli zero, zero, e32, m8, tu, mu
+vaesef.vv v8, v16
+vaesef.vs v8, v16
+vaesem.vv v8, v16
+vaesem.vs v8, v16
+vaesdm.vv v8, v16
+vaesdm.vs v8, v16
+vaeskf1.vi v8, v16, 8
+vaeskf2.vi v8, v16, 8
+vaesz.vs v8, v16
+
+# CHECK: Iterations: 1
+# CHECK-NEXT: Instructions: 50
+# CHECK-NEXT: Total Cycles: 72
+# CHECK-NEXT: Total uOps: 50
+
+# CHECK: Dispatch Width: 4
+# CHECK-NEXT: uOps Per Cycle: 0.69
+# CHECK-NEXT: IPC: 0.69
+# CHECK-NEXT: Block RThroughput: 72.0
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.50 vaesef.vv v4, v8
+# CHECK-NEXT: 1 1 0.50 vaesef.vs v4, v8
+# CHECK-NEXT: 1 1 0.50 vaesem.vv v4, v8
+# CHECK-NEXT: 1 1 0.50 vaesem.vs v4, v8
+# CHECK-NEXT: 1 1 0.50 vaesdm.vv v4, v8
+# CHECK-NEXT: 1 1 0.50 vaesdm.vs v4, v8
+# CHECK-NEXT: 1 1 0.50 vaeskf1.vi v4, v8, 8
+# CHECK-NEXT: 1 1 0.50 vaeskf2.vi v4, v8, 8
+# CHECK-NEXT: 1 1 0.50 vaesz.vs v4, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 0.50 vaesef.vv v4, v8
+# CHECK-NEXT: 1 1 0.50 vaesef.vs v4, v8
+# CHECK-NEXT: 1 1 0.50 vaesem.vv v4, v8
+# CHECK-NEXT: 1 1 0.50 vaesem.vs v4, v8
+# CHECK-NEXT: 1 1 0.50 vaesdm.vv v4, v8
+# CHECK-NEXT: 1 1 0.50 vaesdm.vs v4, v8
+# CHECK-NEXT: 1 1 0.50 vaeskf1.vi v4, v8, 8
+# CHECK-NEXT: 1 1 0.50 vaeskf2.vi v4, v8, 8
+# CHECK-NEXT: 1 1 0.50 vaesz.vs v4, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 vaesef.vv v4, v8
+# CHECK-NEXT: 1 1 1.00 vaesef.vs v4, v8
+# CHECK-NEXT: 1 1 1.00 vaesem.vv v4, v8
+# CHECK-NEXT: 1 1 1.00 vaesem.vs v4, v8
+# CHECK-NEXT: 1 1 1.00 vaesdm.vv v4, v8
+# CHECK-NEXT: 1 1 1.00 vaesdm.vs v4, v8
+# CHECK-NEXT: 1 1 1.00 vaeskf1.vi v4, v8, 8
+# CHECK-NEXT: 1 1 1.00 vaeskf2.vi v4, v8, 8
+# CHECK-NEXT: 1 1 1.00 vaesz.vs v4, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 2.00 vaesef.vv v4, v8
+# CHECK-NEXT: 1 1 2.00 vaesef.vs v4, v8
+# CHECK-NEXT: 1 1 2.00 vaesem.vv v4, v8
+# CHECK-NEXT: 1 1 2.00 vaesem.vs v4, v8
+# CHECK-NEXT: 1 1 2.00 vaesdm.vv v4, v8
+# CHECK-NEXT: 1 1 2.00 vaesdm.vs v4, v8
+# CHECK-NEXT: 1 1 2.00 vaeskf1.vi v4, v8, 8
+# CHECK-NEXT: 1 1 2.00 vaeskf2.vi v4, v8, 8
+# CHECK-NEXT: 1 1 2.00 vaesz.vs v4, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 4.00 vaesef.vv v8, v16
+# CHECK-NEXT: 1 1 4.00 vaesef.vs v8, v16
+# CHECK-NEXT: 1 1 4.00 vaesem.vv v8, v16
+# CHECK-NEXT: 1 1 4.00 vaesem.vs v8, v16
+# CHECK-NEXT: 1 1 4.00 vaesdm.vv v8, v16
+# CHECK-NEXT: 1 1 4.00 vaesdm.vs v8, v16
+# CHECK-NEXT: 1 1 4.00 vaeskf1.vi v8, v16, 8
+# CHECK-NEXT: 1 1 4.00 vaeskf2.vi v8, v16, 8
+# CHECK-NEXT: 1 1 4.00 vaesz.vs v8, v16
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP600Div
+# CHECK-NEXT: [1] - SiFiveP600FEXQ0
+# CHECK-NEXT: [2] - SiFiveP600FEXQ1
+# CHECK-NEXT: [3] - SiFiveP600FloatDiv
+# CHECK-NEXT: [4] - SiFiveP600IEXQ0
+# CHECK-NEXT: [5] - SiFiveP600IEXQ1
+# CHECK-NEXT: [6] - SiFiveP600IEXQ2
+# CHECK-NEXT: [7] - SiFiveP600IEXQ3
+# CHECK-NEXT: [8.0] - SiFiveP600LDST
+# CHECK-NEXT: [8.1] - SiFiveP600LDST
+# CHECK-NEXT: [9] - SiFiveP600VDiv
+# CHECK-NEXT: [10] - SiFiveP600VEXQ0
+# CHECK-NEXT: [11] - SiFiveP600VEXQ1
+# CHECK-NEXT: [12] - SiFiveP600VFloatDiv
+# CHECK-NEXT: [13] - SiFiveP600VLD
+# CHECK-NEXT: [14] - SiFiveP600VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14]
+# CHECK-NEXT: - - - - 5.00 - - - - - - 69.00 75.00 - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14] Instructions:
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vaesef.vv v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vaesef.vs v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vaesem.vv v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vaesem.vs v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vaesdm.vv v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vaesdm.vs v4, v8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vaeskf1.vi v4, v8, 8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vaeskf2.vi v4, v8, 8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vaesz.vs v4, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vaesef.vv v4, v8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vaesef.vs v4, v8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vaesem.vv v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vaesem.vs v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vaesdm.vv v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vaesdm.vs v4, v8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vaeskf1.vi v4, v8, 8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vaeskf2.vi v4, v8, 8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vaesz.vs v4, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 - - - vaesef.vv v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 - - - vaesef.vs v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 - - - vaesem.vv v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 - - - vaesem.vs v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 - - - vaesdm.vv v4, v8
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vaesdm.vs v4, v8
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vaeskf1.vi v4, v8, 8
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vaeskf2.vi v4, v8, 8
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vaesz.vs v4, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vaesef.vv v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vaesef.vs v4, v8
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vaesem.vv v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vaesem.vs v4, v8
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vaesdm.vv v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vaesdm.vs v4, v8
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vaeskf1.vi v4, v8, 8
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vaeskf2.vi v4, v8, 8
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vaesz.vs v4, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vaesef.vv v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vaesef.vs v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vaesem.vv v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vaesem.vs v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vaesdm.vv v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vaesdm.vs v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vaeskf1.vi v8, v16, 8
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vaeskf2.vi v8, v16, 8
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vaesz.vs v8, v16
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvknhb.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvknhb.s
new file mode 100644
index 00000000000000..0e26e5bacaf21b
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvknhb.s
@@ -0,0 +1,153 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p670 -iterations=1 < %s | FileCheck %s
+
+# SEW is only e32 or e64
+
+vsetvli zero, zero, e32, m1, tu, mu
+vsha2ms.vv v4, v8, v12
+vsha2ch.vv v4, v8, v12
+vsha2cl.vv v4, v8, v12
+
+vsetvli zero, zero, e32, m2, tu, mu
+vsha2ms.vv v4, v8, v12
+vsha2ch.vv v4, v8, v12
+vsha2cl.vv v4, v8, v12
+
+vsetvli zero, zero, e32, m4, tu, mu
+vsha2ms.vv v4, v8, v12
+vsha2ch.vv v4, v8, v12
+vsha2cl.vv v4, v8, v12
+
+vsetvli zero, zero, e32, m8, tu, mu
+vsha2ms.vv v8, v16, v24
+vsha2ch.vv v8, v16, v24
+vsha2cl.vv v8, v16, v24
+
+vsetvli zero, zero, e64, m1, tu, mu
+vsha2ms.vv v4, v8, v12
+vsha2ch.vv v4, v8, v12
+vsha2cl.vv v4, v8, v12
+
+vsetvli zero, zero, e64, m2, tu, mu
+vsha2ms.vv v4, v8, v12
+vsha2ch.vv v4, v8, v12
+vsha2cl.vv v4, v8, v12
+
+vsetvli zero, zero, e64, m4, tu, mu
+vsha2ms.vv v4, v8, v12
+vsha2ch.vv v4, v8, v12
+vsha2cl.vv v4, v8, v12
+
+vsetvli zero, zero, e64, m8, tu, mu
+vsha2ms.vv v8, v16, v24
+vsha2ch.vv v8, v16, v24
+vsha2cl.vv v8, v16, v24
+
+# CHECK: Iterations: 1
+# CHECK-NEXT: Instructions: 32
+# CHECK-NEXT: Total Cycles: 45
+# CHECK-NEXT: Total uOps: 32
+
+# CHECK: Dispatch Width: 4
+# CHECK-NEXT: uOps Per Cycle: 0.71
+# CHECK-NEXT: IPC: 0.71
+# CHECK-NEXT: Block RThroughput: 45.0
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 0.50 vsha2ms.vv v4, v8, v12
+# CHECK-NEXT: 1 1 0.50 vsha2ch.vv v4, v8, v12
+# CHECK-NEXT: 1 1 0.50 vsha2cl.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 vsha2ms.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 vsha2ch.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 vsha2cl.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 2.00 vsha2ms.vv v4, v8, v12
+# CHECK-NEXT: 1 1 2.00 vsha2ch.vv v4, v8, v12
+# CHECK-NEXT: 1 1 2.00 vsha2cl.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 4.00 vsha2ms.vv v8, v16, v24
+# CHECK-NEXT: 1 1 4.00 vsha2ch.vv v8, v16, v24
+# CHECK-NEXT: 1 1 4.00 vsha2cl.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 0.50 vsha2ms.vv v4, v8, v12
+# CHECK-NEXT: 1 1 0.50 vsha2ch.vv v4, v8, v12
+# CHECK-NEXT: 1 1 0.50 vsha2cl.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 vsha2ms.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 vsha2ch.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 vsha2cl.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 2.00 vsha2ms.vv v4, v8, v12
+# CHECK-NEXT: 1 1 2.00 vsha2ch.vv v4, v8, v12
+# CHECK-NEXT: 1 1 2.00 vsha2cl.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 4.00 vsha2ms.vv v8, v16, v24
+# CHECK-NEXT: 1 1 4.00 vsha2ch.vv v8, v16, v24
+# CHECK-NEXT: 1 1 4.00 vsha2cl.vv v8, v16, v24
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP600Div
+# CHECK-NEXT: [1] - SiFiveP600FEXQ0
+# CHECK-NEXT: [2] - SiFiveP600FEXQ1
+# CHECK-NEXT: [3] - SiFiveP600FloatDiv
+# CHECK-NEXT: [4] - SiFiveP600IEXQ0
+# CHECK-NEXT: [5] - SiFiveP600IEXQ1
+# CHECK-NEXT: [6] - SiFiveP600IEXQ2
+# CHECK-NEXT: [7] - SiFiveP600IEXQ3
+# CHECK-NEXT: [8.0] - SiFiveP600LDST
+# CHECK-NEXT: [8.1] - SiFiveP600LDST
+# CHECK-NEXT: [9] - SiFiveP600VDiv
+# CHECK-NEXT: [10] - SiFiveP600VEXQ0
+# CHECK-NEXT: [11] - SiFiveP600VEXQ1
+# CHECK-NEXT: [12] - SiFiveP600VFloatDiv
+# CHECK-NEXT: [13] - SiFiveP600VLD
+# CHECK-NEXT: [14] - SiFiveP600VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14]
+# CHECK-NEXT: - - - - 8.00 - - - - - - 46.00 44.00 - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14] Instructions:
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vsha2ms.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vsha2ch.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vsha2cl.vv v4, v8, v12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vsha2ms.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vsha2ch.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vsha2cl.vv v4, v8, v12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vsha2ms.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vsha2ch.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vsha2cl.vv v4, v8, v12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vsha2ms.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vsha2ch.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vsha2cl.vv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vsha2ms.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vsha2ch.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vsha2cl.vv v4, v8, v12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vsha2ms.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vsha2ch.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vsha2cl.vv v4, v8, v12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vsha2ms.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vsha2ch.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vsha2cl.vv v4, v8, v12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vsha2ms.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vsha2ch.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vsha2cl.vv v8, v16, v24
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvksed.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvksed.s
new file mode 100644
index 00000000000000..5cfd266bf14a77
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvksed.s
@@ -0,0 +1,114 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p670 -iterations=1 < %s | FileCheck %s
+
+# These instructions only support e32
+
+vsetvli zero, zero, e32, mf2, tu, mu
+vsm4k.vi v4, v8, 8
+vsm4r.vv v4, v8
+vsm4r.vs v4, v8
+
+vsetvli zero, zero, e32, m1, tu, mu
+vsm4k.vi v4, v8, 8
+vsm4r.vv v4, v8
+vsm4r.vs v4, v8
+
+vsetvli zero, zero, e32, m2, tu, mu
+vsm4k.vi v4, v8, 8
+vsm4r.vv v4, v8
+vsm4r.vs v4, v8
+
+vsetvli zero, zero, e32, m4, tu, mu
+vsm4k.vi v4, v8, 8
+vsm4r.vv v4, v8
+vsm4r.vs v4, v8
+
+vsetvli zero, zero, e32, m8, tu, mu
+vsm4k.vi v8, v16, 8
+vsm4r.vv v8, v16
+vsm4r.vs v8, v16
+
+# CHECK: Iterations: 1
+# CHECK-NEXT: Instructions: 20
+# CHECK-NEXT: Total Cycles: 24
+# CHECK-NEXT: Total uOps: 20
+
+# CHECK: Dispatch Width: 4
+# CHECK-NEXT: uOps Per Cycle: 0.83
+# CHECK-NEXT: IPC: 0.83
+# CHECK-NEXT: Block RThroughput: 24.0
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.50 vsm4k.vi v4, v8, 8
+# CHECK-NEXT: 1 1 0.50 vsm4r.vv v4, v8
+# CHECK-NEXT: 1 1 0.50 vsm4r.vs v4, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 0.50 vsm4k.vi v4, v8, 8
+# CHECK-NEXT: 1 1 0.50 vsm4r.vv v4, v8
+# CHECK-NEXT: 1 1 0.50 vsm4r.vs v4, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 vsm4k.vi v4, v8, 8
+# CHECK-NEXT: 1 1 1.00 vsm4r.vv v4, v8
+# CHECK-NEXT: 1 1 1.00 vsm4r.vs v4, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 2.00 vsm4k.vi v4, v8, 8
+# CHECK-NEXT: 1 1 2.00 vsm4r.vv v4, v8
+# CHECK-NEXT: 1 1 2.00 vsm4r.vs v4, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 4.00 vsm4k.vi v8, v16, 8
+# CHECK-NEXT: 1 1 4.00 vsm4r.vv v8, v16
+# CHECK-NEXT: 1 1 4.00 vsm4r.vs v8, v16
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP600Div
+# CHECK-NEXT: [1] - SiFiveP600FEXQ0
+# CHECK-NEXT: [2] - SiFiveP600FEXQ1
+# CHECK-NEXT: [3] - SiFiveP600FloatDiv
+# CHECK-NEXT: [4] - SiFiveP600IEXQ0
+# CHECK-NEXT: [5] - SiFiveP600IEXQ1
+# CHECK-NEXT: [6] - SiFiveP600IEXQ2
+# CHECK-NEXT: [7] - SiFiveP600IEXQ3
+# CHECK-NEXT: [8.0] - SiFiveP600LDST
+# CHECK-NEXT: [8.1] - SiFiveP600LDST
+# CHECK-NEXT: [9] - SiFiveP600VDiv
+# CHECK-NEXT: [10] - SiFiveP600VEXQ0
+# CHECK-NEXT: [11] - SiFiveP600VEXQ1
+# CHECK-NEXT: [12] - SiFiveP600VFloatDiv
+# CHECK-NEXT: [13] - SiFiveP600VLD
+# CHECK-NEXT: [14] - SiFiveP600VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14]
+# CHECK-NEXT: - - - - 5.00 - - - - - - 21.00 27.00 - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14] Instructions:
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vsm4k.vi v4, v8, 8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vsm4r.vv v4, v8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vsm4r.vs v4, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vsm4k.vi v4, v8, 8
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vsm4r.vv v4, v8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vsm4r.vs v4, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 - - - vsm4k.vi v4, v8, 8
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vsm4r.vv v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 - - - vsm4r.vs v4, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vsm4k.vi v4, v8, 8
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vsm4r.vv v4, v8
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vsm4r.vs v4, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vsm4k.vi v8, v16, 8
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vsm4r.vv v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vsm4r.vs v8, v16
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvksh.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvksh.s
new file mode 100644
index 00000000000000..670a5caeca98ac
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvksh.s
@@ -0,0 +1,99 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p670 -iterations=1 < %s | FileCheck %s
+
+# These instructions only support e32
+
+vsetvli zero, zero, e32, mf2, tu, mu
+vsm3me.vv v4, v8, v12
+vsm3c.vi v4, v8, 8
+
+vsetvli zero, zero, e32, m1, tu, mu
+vsm3me.vv v4, v8, v12
+vsm3c.vi v4, v8, 8
+
+vsetvli zero, zero, e32, m2, tu, mu
+vsm3me.vv v4, v8, v12
+vsm3c.vi v4, v8, 8
+
+vsetvli zero, zero, e32, m4, tu, mu
+vsm3me.vv v4, v8, v12
+vsm3c.vi v4, v8, 8
+
+vsetvli zero, zero, e32, m8, tu, mu
+vsm3me.vv v8, v16, v24
+vsm3c.vi v8, v16, 8
+
+# CHECK: Iterations: 1
+# CHECK-NEXT: Instructions: 15
+# CHECK-NEXT: Total Cycles: 14
+# CHECK-NEXT: Total uOps: 15
+
+# CHECK: Dispatch Width: 4
+# CHECK-NEXT: uOps Per Cycle: 1.07
+# CHECK-NEXT: IPC: 1.07
+# CHECK-NEXT: Block RThroughput: 16.0
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.50 vsm3me.vv v4, v8, v12
+# CHECK-NEXT: 1 1 0.50 vsm3c.vi v4, v8, 8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 0.50 vsm3me.vv v4, v8, v12
+# CHECK-NEXT: 1 1 0.50 vsm3c.vi v4, v8, 8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 vsm3me.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 vsm3c.vi v4, v8, 8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 2.00 vsm3me.vv v4, v8, v12
+# CHECK-NEXT: 1 1 2.00 vsm3c.vi v4, v8, 8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 4.00 vsm3me.vv v8, v16, v24
+# CHECK-NEXT: 1 1 4.00 vsm3c.vi v8, v16, 8
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP600Div
+# CHECK-NEXT: [1] - SiFiveP600FEXQ0
+# CHECK-NEXT: [2] - SiFiveP600FEXQ1
+# CHECK-NEXT: [3] - SiFiveP600FloatDiv
+# CHECK-NEXT: [4] - SiFiveP600IEXQ0
+# CHECK-NEXT: [5] - SiFiveP600IEXQ1
+# CHECK-NEXT: [6] - SiFiveP600IEXQ2
+# CHECK-NEXT: [7] - SiFiveP600IEXQ3
+# CHECK-NEXT: [8.0] - SiFiveP600LDST
+# CHECK-NEXT: [8.1] - SiFiveP600LDST
+# CHECK-NEXT: [9] - SiFiveP600VDiv
+# CHECK-NEXT: [10] - SiFiveP600VEXQ0
+# CHECK-NEXT: [11] - SiFiveP600VEXQ1
+# CHECK-NEXT: [12] - SiFiveP600VFloatDiv
+# CHECK-NEXT: [13] - SiFiveP600VLD
+# CHECK-NEXT: [14] - SiFiveP600VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14]
+# CHECK-NEXT: - - - - 5.00 - - - - - - 16.00 16.00 - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14] Instructions:
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vsm3me.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vsm3c.vi v4, v8, 8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - vsm3me.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vsm3c.vi v4, v8, 8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 - - - vsm3me.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vsm3c.vi v4, v8, 8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 - - - vsm3me.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vsm3c.vi v4, v8, 8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 - - - vsm3me.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vsm3c.vi v8, v16, 8
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