[llvm] [RISCV] Support postRA vsetvl insertion pass (PR #70549)

[Luke Lau via llvm-commits]

lukel97 wrote:

I think the codegen changes are overall looking quite good now.

On TSVC there's no change in the number spills nor any change to the vsetvlis.

On llvm-test-suite w/ SPEC CPU 2017 I'm seeing a geomean 0.6% reduction in spills and a 1.2% increase in the number of vsetvlis emitted. 

I'm not too concerned about the increase in vsetvlis though, since at a first glance we seem to be rescheduling a lot more vector instructions, especially around the more exotic load and store instructions (vlseg,vsox, etc.). I would expect these to need more toggles. 

https://github.com/llvm/llvm-project/pull/70549