[llvm] [RISCV] Support postRA vsetvl insertion pass (PR #70549)

[Piyou Chen via llvm-commits]

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@@ -1502,14 +1668,14 @@ void RISCVInsertVSETVLI::doPRE(MachineBasicBlock &MBB) {
   // we need to prove the value is available at the point we're going
   // to insert the vsetvli at.
   if (AvailableInfo.hasAVLReg()) {
-    const MachineInstr *AVLDefMI = &AvailableInfo.getAVLDefMI();
+    SlotIndex SI = AvailableInfo.getAVLVNInfo()->def;
     // This is an inline dominance check which covers the case of
     // UnavailablePred being the preheader of a loop.
-    if (AVLDefMI->getParent() != UnavailablePred)
+    if (LIS->getMBBFromIndex(SI) != UnavailablePred)
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BeMg wrote:

By the way `riscv-vsetvli-after-rvv-regalloc=false` situation, pass manager will invoke LiveIntervals and prepare LIS before into vsetvli pass. it is due to `AU.addRequired<LiveIntervals>();`.

---

I put the flag here for two reasons:

1. It provides a convenient way to compare the pre-RA/post-RA behavior of the vsetvli pass.
2. In case someone encounters a bug, they can disable the flag without modifying the source code.

But the final goal is use post-RA version replace the pre-RA version entirely. Therefore, removing the flag and pre-RA code paths in this patch is good and acceptable.


https://github.com/llvm/llvm-project/pull/70549