[llvm] SystemZ: Fold copy of vector immediate to gr128 (PR #90706)
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Fri May 3 01:21:36 PDT 2024
https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/90706
>From 2ff4183c723e625938c66e614560a4913067378b Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Wed, 1 May 2024 08:16:41 +0200
Subject: [PATCH 1/4] SystemZ: Add baseline test for peephole-opt immediate
folding
---
.../SystemZ/fold-copy-vector-immediate.mir | 181 ++++++++++++++++++
1 file changed, 181 insertions(+)
create mode 100644 llvm/test/CodeGen/SystemZ/fold-copy-vector-immediate.mir
diff --git a/llvm/test/CodeGen/SystemZ/fold-copy-vector-immediate.mir b/llvm/test/CodeGen/SystemZ/fold-copy-vector-immediate.mir
new file mode 100644
index 00000000000000..db6a43d2becd72
--- /dev/null
+++ b/llvm/test/CodeGen/SystemZ/fold-copy-vector-immediate.mir
@@ -0,0 +1,181 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
+# RUN: llc -mtriple=s390x-linux-gnu -mcpu=z13 -run-pass=peephole-opt -o - %s | FileCheck %s
+
+---
+name: fold_vgbm_0_copyvr128_to_gr128_virtreg
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $r2d
+ ; CHECK-LABEL: name: fold_vgbm_0_copyvr128_to_gr128_virtreg
+ ; CHECK: liveins: $r2d
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr64bit = COPY $r2d
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:addr64bit = COPY [[COPY]]
+ ; CHECK-NEXT: [[VGBM:%[0-9]+]]:vr128bit = VGBM 0
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr128bit = COPY [[VGBM]]
+ ; CHECK-NEXT: $r0q = COPY [[COPY2]]
+ ; CHECK-NEXT: Return implicit $r0q
+ %0:gr64bit = COPY $r2d
+ %1:addr64bit = COPY %0
+ %2:vr128bit = VGBM 0
+ %3:gr128bit = COPY %2
+ $r0q = COPY %3
+ Return implicit $r0q
+...
+
+---
+name: fold_vgbm_0_copyvr128_to_gr128_virtreg_multi_use
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $r2d
+ ; CHECK-LABEL: name: fold_vgbm_0_copyvr128_to_gr128_virtreg_multi_use
+ ; CHECK: liveins: $r2d
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr64bit = COPY $r2d
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:addr64bit = COPY [[COPY]]
+ ; CHECK-NEXT: [[VGBM:%[0-9]+]]:vr128bit = VGBM 0
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr128bit = COPY [[VGBM]]
+ ; CHECK-NEXT: $r0q = COPY [[COPY2]]
+ ; CHECK-NEXT: $r2q = COPY [[COPY2]]
+ ; CHECK-NEXT: Return implicit $r0q, implicit $r2q
+ %0:gr64bit = COPY $r2d
+ %1:addr64bit = COPY %0
+ %2:vr128bit = VGBM 0
+ %3:gr128bit = COPY %2
+ %4:gr128bit = COPY %2
+ $r0q = COPY %3
+ $r2q = COPY %4
+ Return implicit $r0q, implicit $r2q
+...
+
+---
+name: fold_vgbm_0_copyvr128_to_gr128_physreg
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $r2d
+ ; CHECK-LABEL: name: fold_vgbm_0_copyvr128_to_gr128_physreg
+ ; CHECK: liveins: $r2d
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr64bit = COPY $r2d
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:addr64bit = COPY [[COPY]]
+ ; CHECK-NEXT: [[VGBM:%[0-9]+]]:vr128bit = VGBM 0
+ ; CHECK-NEXT: $r0q = COPY [[VGBM]]
+ ; CHECK-NEXT: Return implicit $r0q
+ %0:gr64bit = COPY $r2d
+ %1:addr64bit = COPY %0
+ %2:vr128bit = VGBM 0
+ $r0q = COPY %2
+ Return implicit $r0q
+...
+
+---
+name: no_fold_vgbm_0_copyvr128_to_vr128_virtreg
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $r2d
+ ; CHECK-LABEL: name: no_fold_vgbm_0_copyvr128_to_vr128_virtreg
+ ; CHECK: liveins: $r2d
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr64bit = COPY $r2d
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:addr64bit = COPY [[COPY]]
+ ; CHECK-NEXT: [[VGBM:%[0-9]+]]:vr128bit = VGBM 0
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vr128bit = COPY [[VGBM]]
+ ; CHECK-NEXT: $v0 = COPY [[COPY2]]
+ ; CHECK-NEXT: Return implicit $v0
+ %0:gr64bit = COPY $r2d
+ %1:addr64bit = COPY %0
+ %2:vr128bit = VGBM 0
+ %3:vr128bit = COPY %2
+ $v0 = COPY %3
+ Return implicit $v0
+...
+
+---
+name: no_fold_vgbm_0_copyvr128_to_vr128_physreg
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $r2d
+ ; CHECK-LABEL: name: no_fold_vgbm_0_copyvr128_to_vr128_physreg
+ ; CHECK: liveins: $r2d
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr64bit = COPY $r2d
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:addr64bit = COPY [[COPY]]
+ ; CHECK-NEXT: [[VGBM:%[0-9]+]]:vr128bit = VGBM 0
+ ; CHECK-NEXT: $v0 = COPY [[VGBM]]
+ ; CHECK-NEXT: Return implicit $v0
+ %0:gr64bit = COPY $r2d
+ %1:addr64bit = COPY %0
+ %2:vr128bit = VGBM 0
+ $v0 = COPY %2
+ Return implicit $v0
+...
+
+---
+name: fold_vgbm_1_copyvr128_to_gr128_virtreg
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $r2d
+ ; CHECK-LABEL: name: fold_vgbm_1_copyvr128_to_gr128_virtreg
+ ; CHECK: liveins: $r2d
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr64bit = COPY $r2d
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:addr64bit = COPY [[COPY]]
+ ; CHECK-NEXT: [[VGBM:%[0-9]+]]:vr128bit = VGBM 1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr128bit = COPY [[VGBM]]
+ ; CHECK-NEXT: $r0q = COPY [[COPY2]]
+ ; CHECK-NEXT: Return implicit $r0q
+ %0:gr64bit = COPY $r2d
+ %1:addr64bit = COPY %0
+ %2:vr128bit = VGBM 1
+ %3:gr128bit = COPY %2
+ $r0q = COPY %3
+ Return implicit $r0q
+...
+
+---
+name: no_fold_vgbm_0_noncopy_use
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $r2d
+ ; CHECK-LABEL: name: no_fold_vgbm_0_noncopy_use
+ ; CHECK: liveins: $r2d
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr64bit = COPY $r2d
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:addr64bit = COPY [[COPY]]
+ ; CHECK-NEXT: [[VGBM:%[0-9]+]]:vr128bit = VGBM 0
+ ; CHECK-NEXT: Return implicit [[VGBM]]
+ %0:gr64bit = COPY $r2d
+ %1:addr64bit = COPY %0
+ %2:vr128bit = VGBM 0
+ Return implicit %2
+...
+
+---
+name: fold_vgbm_0_copyvr128_to_gr64_subreg_h64
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $r2d
+ ; CHECK-LABEL: name: fold_vgbm_0_copyvr128_to_gr64_subreg_h64
+ ; CHECK: liveins: $r2d
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr64bit = COPY $r2d
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:addr64bit = COPY [[COPY]]
+ ; CHECK-NEXT: [[VGBM:%[0-9]+]]:vr128bit = VGBM 0
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr64bit = COPY [[VGBM]].subreg_h64
+ ; CHECK-NEXT: $r0d = COPY [[COPY2]]
+ ; CHECK-NEXT: Return implicit $r0d
+ %0:gr64bit = COPY $r2d
+ %1:addr64bit = COPY %0
+ %2:vr128bit = VGBM 0
+ %3:gr64bit = COPY %2.subreg_h64
+ $r0d = COPY %3
+ Return implicit $r0d
+...
>From c845cc4fe10ae04a5880cc8a8874a260ac78e61f Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Wed, 1 May 2024 00:32:21 +0200
Subject: [PATCH 2/4] SystemZ: Fold copy of vector immediate to gr128
If materializing a constant in a vector register that is just
going to be copied to general registers, directly materialize
the immediate in the gpr. This will avoid a few lit test regressions
in a future commit.
---
llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp | 54 +++++++++++++++++++
llvm/lib/Target/SystemZ/SystemZInstrInfo.h | 3 ++
.../SystemZ/fold-copy-vector-immediate.mir | 10 ++--
3 files changed, 63 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
index b3517fb0ea77f5..e992ad53dc452c 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
@@ -640,6 +640,48 @@ bool SystemZInstrInfo::foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
Register Reg,
MachineRegisterInfo *MRI) const {
unsigned DefOpc = DefMI.getOpcode();
+
+ if (DefOpc == SystemZ::VGBM) {
+ // Fold gr128 = COPY (vr128 VGBM imm)
+ //
+ // %tmp:gr64 = LGHI 0
+ // to gr128 = REG_SEQUENCE %tmp, %tmp
+ assert(DefMI.getOperand(0).getReg() == Reg);
+
+ if (!UseMI.isCopy())
+ return false;
+
+ Register CopyDstReg = UseMI.getOperand(0).getReg();
+ if (CopyDstReg.isVirtual() &&
+ MRI->getRegClass(CopyDstReg) == &SystemZ::GR128BitRegClass &&
+ MRI->hasOneNonDBGUse(Reg)) {
+ // TODO: Handle physical registers
+ // TODO: Handle gr64 uses with subregister indexes
+ // TODO: Should this multi-use cases?
+ Register TmpReg = MRI->createVirtualRegister(&SystemZ::GR64BitRegClass);
+ MachineBasicBlock &MBB = *UseMI.getParent();
+
+ // FIXME: probably should be DeFMI's DebugLoc but this matches
+ // loadImmediate's guessing
+ const DebugLoc &DL = UseMI.getDebugLoc();
+
+ loadImmediate(MBB, UseMI.getIterator(), TmpReg,
+ DefMI.getOperand(1).getImm());
+
+ BuildMI(MBB, UseMI.getIterator(), DL, get(SystemZ::REG_SEQUENCE),
+ CopyDstReg)
+ .addReg(TmpReg)
+ .addImm(SystemZ::subreg_h64)
+ .addReg(TmpReg)
+ .addImm(SystemZ::subreg_l64);
+
+ UseMI.eraseFromParent();
+ return true;
+ }
+
+ return false;
+ }
+
if (DefOpc != SystemZ::LHIMux && DefOpc != SystemZ::LHI &&
DefOpc != SystemZ::LGHI)
return false;
@@ -2221,3 +2263,15 @@ areMemAccessesTriviallyDisjoint(const MachineInstr &MIa,
return false;
}
+
+bool SystemZInstrInfo::getConstValDefinedInReg(const MachineInstr &MI,
+ const Register Reg,
+ int64_t &ImmVal) const {
+
+ if (MI.getOpcode() == SystemZ::VGBM && Reg == MI.getOperand(0).getReg()) {
+ ImmVal = MI.getOperand(1).getImm();
+ return true;
+ }
+
+ return false;
+}
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.h b/llvm/lib/Target/SystemZ/SystemZInstrInfo.h
index aa10fb56496231..61338b0816155a 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.h
+++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.h
@@ -383,6 +383,9 @@ class SystemZInstrInfo : public SystemZGenInstrInfo {
bool
areMemAccessesTriviallyDisjoint(const MachineInstr &MIa,
const MachineInstr &MIb) const override;
+
+ bool getConstValDefinedInReg(const MachineInstr &MI, const Register Reg,
+ int64_t &ImmVal) const override;
};
} // end namespace llvm
diff --git a/llvm/test/CodeGen/SystemZ/fold-copy-vector-immediate.mir b/llvm/test/CodeGen/SystemZ/fold-copy-vector-immediate.mir
index db6a43d2becd72..78d98bba9d61a5 100644
--- a/llvm/test/CodeGen/SystemZ/fold-copy-vector-immediate.mir
+++ b/llvm/test/CodeGen/SystemZ/fold-copy-vector-immediate.mir
@@ -13,8 +13,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:gr64bit = COPY $r2d
; CHECK-NEXT: [[COPY1:%[0-9]+]]:addr64bit = COPY [[COPY]]
; CHECK-NEXT: [[VGBM:%[0-9]+]]:vr128bit = VGBM 0
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr128bit = COPY [[VGBM]]
- ; CHECK-NEXT: $r0q = COPY [[COPY2]]
+ ; CHECK-NEXT: [[LGHI:%[0-9]+]]:gr64bit = LGHI 0
+ ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:gr128bit = REG_SEQUENCE [[LGHI]], %subreg.subreg_h64, [[LGHI]], %subreg.subreg_l64
+ ; CHECK-NEXT: $r0q = COPY [[REG_SEQUENCE]]
; CHECK-NEXT: Return implicit $r0q
%0:gr64bit = COPY $r2d
%1:addr64bit = COPY %0
@@ -127,8 +128,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:gr64bit = COPY $r2d
; CHECK-NEXT: [[COPY1:%[0-9]+]]:addr64bit = COPY [[COPY]]
; CHECK-NEXT: [[VGBM:%[0-9]+]]:vr128bit = VGBM 1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr128bit = COPY [[VGBM]]
- ; CHECK-NEXT: $r0q = COPY [[COPY2]]
+ ; CHECK-NEXT: [[LGHI:%[0-9]+]]:gr64bit = LGHI 1
+ ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:gr128bit = REG_SEQUENCE [[LGHI]], %subreg.subreg_h64, [[LGHI]], %subreg.subreg_l64
+ ; CHECK-NEXT: $r0q = COPY [[REG_SEQUENCE]]
; CHECK-NEXT: Return implicit $r0q
%0:gr64bit = COPY $r2d
%1:addr64bit = COPY %0
>From 5f92f135e8955965b7ed16ffe54ebe268ebb2d8e Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Fri, 3 May 2024 10:11:51 +0200
Subject: [PATCH 3/4] Only handle 0
---
llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp | 12 ++++++++----
.../CodeGen/SystemZ/fold-copy-vector-immediate.mir | 5 ++---
2 files changed, 10 insertions(+), 7 deletions(-)
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
index 4302ef0f2385d5..9f363ee2d18964 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
@@ -642,6 +642,10 @@ bool SystemZInstrInfo::foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
unsigned DefOpc = DefMI.getOpcode();
if (DefOpc == SystemZ::VGBM) {
+ int64_t ImmVal = DefMI.getOperand(1).getImm();
+ if (ImmVal !=0) // TODO: Handle other values
+ return false;
+
// Fold gr128 = COPY (vr128 VGBM imm)
//
// %tmp:gr64 = LGHI 0
@@ -661,12 +665,11 @@ bool SystemZInstrInfo::foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
Register TmpReg = MRI->createVirtualRegister(&SystemZ::GR64BitRegClass);
MachineBasicBlock &MBB = *UseMI.getParent();
- // FIXME: probably should be DeFMI's DebugLoc but this matches
+ // FIXME: probably should be DefMI's DebugLoc but this matches
// loadImmediate's guessing
const DebugLoc &DL = UseMI.getDebugLoc();
- loadImmediate(MBB, UseMI.getIterator(), TmpReg,
- DefMI.getOperand(1).getImm());
+ loadImmediate(MBB, UseMI.getIterator(), TmpReg, ImmVal);
BuildMI(MBB, UseMI.getIterator(), DL, get(SystemZ::REG_SEQUENCE),
CopyDstReg)
@@ -2286,7 +2289,8 @@ bool SystemZInstrInfo::getConstValDefinedInReg(const MachineInstr &MI,
if (MI.getOpcode() == SystemZ::VGBM && Reg == MI.getOperand(0).getReg()) {
ImmVal = MI.getOperand(1).getImm();
- return true;
+ // TODO: Handle non-0 values
+ return ImmVal == 0;
}
return false;
diff --git a/llvm/test/CodeGen/SystemZ/fold-copy-vector-immediate.mir b/llvm/test/CodeGen/SystemZ/fold-copy-vector-immediate.mir
index 78d98bba9d61a5..2aee0cb521c4c8 100644
--- a/llvm/test/CodeGen/SystemZ/fold-copy-vector-immediate.mir
+++ b/llvm/test/CodeGen/SystemZ/fold-copy-vector-immediate.mir
@@ -128,9 +128,8 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:gr64bit = COPY $r2d
; CHECK-NEXT: [[COPY1:%[0-9]+]]:addr64bit = COPY [[COPY]]
; CHECK-NEXT: [[VGBM:%[0-9]+]]:vr128bit = VGBM 1
- ; CHECK-NEXT: [[LGHI:%[0-9]+]]:gr64bit = LGHI 1
- ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:gr128bit = REG_SEQUENCE [[LGHI]], %subreg.subreg_h64, [[LGHI]], %subreg.subreg_l64
- ; CHECK-NEXT: $r0q = COPY [[REG_SEQUENCE]]
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr128bit = COPY [[VGBM]]
+ ; CHECK-NEXT: $r0q = COPY [[COPY2]]
; CHECK-NEXT: Return implicit $r0q
%0:gr64bit = COPY $r2d
%1:addr64bit = COPY %0
>From 321f1a748766071933deae0dbdcc4a2cd6ffc6d8 Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Fri, 3 May 2024 10:21:23 +0200
Subject: [PATCH 4/4] Formatting
---
llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
index 9f363ee2d18964..3238b62218dbaa 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
@@ -643,7 +643,7 @@ bool SystemZInstrInfo::foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
if (DefOpc == SystemZ::VGBM) {
int64_t ImmVal = DefMI.getOperand(1).getImm();
- if (ImmVal !=0) // TODO: Handle other values
+ if (ImmVal != 0) // TODO: Handle other values
return false;
// Fold gr128 = COPY (vr128 VGBM imm)
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